diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
| commit | ccfdc533b9d679f1596d43d647a093885d5e74ab (patch) | |
| tree | 4c785a5e7a7e2d7244fbdbb0a316405898f99e75 /tests/long/fs/10.linux-boot/ref | |
| parent | 460cc77d6db46eef34b14a458816084bf6097b32 (diff) | |
| download | gem5-ccfdc533b9d679f1596d43d647a093885d5e74ab.tar.xz | |
stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref')
12 files changed, 17814 insertions, 16262 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 213dc1867..fc255dc72 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,135 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.902739 # Number of seconds simulated -sim_ticks 1902738973500 # Number of ticks simulated -final_tick 1902738973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.904665 # Number of seconds simulated +sim_ticks 1904665099500 # Number of ticks simulated +final_tick 1904665099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132013 # Simulator instruction rate (inst/s) -host_op_rate 132013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4427958303 # Simulator tick rate (ticks/s) -host_mem_usage 313120 # Number of bytes of host memory used -host_seconds 429.71 # Real time elapsed on the host -sim_insts 56727331 # Number of instructions simulated -sim_ops 56727331 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 900544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24806400 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 74944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 436992 # Number of bytes read from this memory -system.physmem.bytes_read::total 28869696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 900544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 74944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 975488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7821440 # Number of bytes written to this memory -system.physmem.bytes_written::total 7821440 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14071 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387600 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6828 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451089 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122210 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122210 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 473288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13037206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1393158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 39387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 229665 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15172704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 473288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 39387 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512676 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4110622 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4110622 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4110622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 473288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13037206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1393158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 39387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 229665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19283326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 451089 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 122210 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 451089 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 122210 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28869696 # Total number of bytes read from memory -system.physmem.bytesWritten 7821440 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28869696 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7821440 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4926 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28134 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28418 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27918 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28169 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27493 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27636 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28106 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28006 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28071 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28522 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28683 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28473 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28357 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7885 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7743 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8146 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7856 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7349 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7637 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7614 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6924 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 6873 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7305 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7296 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7454 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7954 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8175 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8091 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7908 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 1902738952500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 451089 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 122210 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 323917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64738 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3023 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1443 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2046 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2216 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 449 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +host_inst_rate 126318 # Simulator instruction rate (inst/s) +host_op_rate 126318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4285588150 # Simulator tick rate (ticks/s) +host_mem_usage 339596 # Number of bytes of host memory used +host_seconds 444.44 # Real time elapsed on the host +sim_insts 56140339 # Number of instructions simulated +sim_ops 56140339 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 734400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24199744 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 243008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1012480 # Number of bytes read from this memory +system.physmem.bytes_read::total 28839936 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 734400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 243008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7811840 # Number of bytes written to this memory +system.physmem.bytes_written::total 7811840 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11475 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 378121 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41411 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3797 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 15820 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450624 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122060 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122060 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 385580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12705511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1391480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 127586 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 531579 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15141736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 385580 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 127586 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513165 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4101424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4101424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4101424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 385580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12705511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1391480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 127586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 531579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19243160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450624 # Number of read requests accepted +system.physmem.writeReqs 122060 # Number of write requests accepted +system.physmem.readBursts 450624 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122060 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28836416 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3520 # Total number of bytes read from write queue +system.physmem.bytesWritten 7811520 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28839936 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7811840 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 3409 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28171 # Per bank write bursts +system.physmem.perBankRdBursts::1 27944 # Per bank write bursts +system.physmem.perBankRdBursts::2 28133 # Per bank write bursts +system.physmem.perBankRdBursts::3 27978 # Per bank write bursts +system.physmem.perBankRdBursts::4 27881 # Per bank write bursts +system.physmem.perBankRdBursts::5 28082 # Per bank write bursts +system.physmem.perBankRdBursts::6 28123 # Per bank write bursts +system.physmem.perBankRdBursts::7 28118 # Per bank write bursts +system.physmem.perBankRdBursts::8 28377 # Per bank write bursts +system.physmem.perBankRdBursts::9 28284 # Per bank write bursts +system.physmem.perBankRdBursts::10 27947 # Per bank write bursts +system.physmem.perBankRdBursts::11 28190 # Per bank write bursts +system.physmem.perBankRdBursts::12 28259 # Per bank write bursts +system.physmem.perBankRdBursts::13 28280 # Per bank write bursts +system.physmem.perBankRdBursts::14 28300 # Per bank write bursts +system.physmem.perBankRdBursts::15 28502 # Per bank write bursts +system.physmem.perBankWrBursts::0 7913 # Per bank write bursts +system.physmem.perBankWrBursts::1 7477 # Per bank write bursts +system.physmem.perBankWrBursts::2 7607 # Per bank write bursts +system.physmem.perBankWrBursts::3 7420 # Per bank write bursts +system.physmem.perBankWrBursts::4 7384 # Per bank write bursts +system.physmem.perBankWrBursts::5 7571 # Per bank write bursts +system.physmem.perBankWrBursts::6 7682 # Per bank write bursts +system.physmem.perBankWrBursts::7 7471 # Per bank write bursts +system.physmem.perBankWrBursts::8 7660 # Per bank write bursts +system.physmem.perBankWrBursts::9 7641 # Per bank write bursts +system.physmem.perBankWrBursts::10 7379 # Per bank write bursts +system.physmem.perBankWrBursts::11 7517 # Per bank write bursts +system.physmem.perBankWrBursts::12 7673 # Per bank write bursts +system.physmem.perBankWrBursts::13 7762 # Per bank write bursts +system.physmem.perBankWrBursts::14 7923 # Per bank write bursts +system.physmem.perBankWrBursts::15 7975 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1904663535000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 450624 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 122060 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 322714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33909 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -139,396 +141,458 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40469 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 906.491388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 223.789110 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2353.116019 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14451 35.71% 35.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6072 15.00% 50.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3826 9.45% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2468 6.10% 66.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1670 4.13% 70.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1520 3.76% 74.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1058 2.61% 76.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 819 2.02% 78.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 687 1.70% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 564 1.39% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 556 1.37% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 509 1.26% 84.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 268 0.66% 85.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 232 0.57% 85.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 203 0.50% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 288 0.71% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 119 0.29% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 109 0.27% 87.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 110 0.27% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 196 0.48% 88.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 187 0.46% 88.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 119 0.29% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 500 1.24% 90.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 628 1.55% 91.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 91 0.22% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 33 0.08% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 28 0.07% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 99 0.24% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 30 0.07% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 12 0.03% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 17 0.04% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 48 0.12% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 23 0.06% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 5 0.01% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 33 0.08% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 8 0.02% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 8 0.02% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 6 0.01% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 8 0.02% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 3 0.01% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 2 0.00% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 7 0.02% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 1 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 3 0.01% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 4 0.01% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 2 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 2 0.00% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 4 0.01% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.01% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 2 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 2 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 3 0.01% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 1 0.00% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 2 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 1 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 1 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 2 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 2 0.00% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 3 0.01% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 2 0.00% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 3 0.01% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 7 0.02% 93.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2429 6.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 243 0.60% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 4 0.01% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 5 0.01% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17347 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17731 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17795 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40469 # Bytes accessed per row activation -system.physmem.totQLat 6403559750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13868349750 # Sum of mem lat for all requests -system.physmem.totBusLat 2255080000 # Total cycles spent in databus access -system.physmem.totBankLat 5209710000 # Total cycles spent in bank access -system.physmem.avgQLat 14198.08 # Average queueing delay per request -system.physmem.avgBankLat 11551.05 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30749.13 # Average memory access latency -system.physmem.avgRdBW 15.17 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.17 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 46334 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 790.933310 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 228.010271 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1879.334417 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 16305 35.19% 35.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6714 14.49% 49.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4888 10.55% 60.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2813 6.07% 66.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1747 3.77% 70.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1443 3.11% 73.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1071 2.31% 75.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 878 1.89% 77.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 653 1.41% 78.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 584 1.26% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 640 1.38% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 489 1.06% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 295 0.64% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 293 0.63% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 217 0.47% 84.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 380 0.82% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 150 0.32% 85.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 199 0.43% 85.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 125 0.27% 86.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 135 0.29% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 141 0.30% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 397 0.86% 87.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 230 0.50% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 690 1.49% 89.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 125 0.27% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 87 0.19% 89.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 68 0.15% 90.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 129 0.28% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 56 0.12% 90.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 91 0.20% 90.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 45 0.10% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 78 0.17% 90.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 66 0.14% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 92 0.20% 91.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 29 0.06% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 29 0.06% 91.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 53 0.11% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 51 0.11% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 26 0.06% 91.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 27 0.06% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 25 0.05% 91.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 53 0.11% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 52 0.11% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 16 0.03% 92.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 30 0.06% 92.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 83 0.18% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 42 0.09% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 33 0.07% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 42 0.09% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 86 0.19% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 27 0.06% 92.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 14 0.03% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 51 0.11% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 53 0.11% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 26 0.06% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 25 0.05% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 24 0.05% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 50 0.11% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 51 0.11% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 12 0.03% 93.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 28 0.06% 93.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 84 0.18% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 42 0.09% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 39 0.08% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 87 0.19% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 25 0.05% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 14 0.03% 94.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 55 0.12% 94.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 50 0.11% 94.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 24 0.05% 94.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 21 0.05% 94.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 23 0.05% 94.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 49 0.11% 94.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 50 0.11% 94.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 11 0.02% 94.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 26 0.06% 94.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 86 0.19% 95.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 41 0.09% 95.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 30 0.06% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 38 0.08% 95.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 84 0.18% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 26 0.06% 95.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 9 0.02% 95.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 54 0.12% 95.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 52 0.11% 95.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 23 0.05% 95.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 22 0.05% 95.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 22 0.05% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 49 0.11% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 50 0.11% 96.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 9 0.02% 96.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 25 0.05% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 85 0.18% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 39 0.08% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 31 0.07% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 44 0.09% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 84 0.18% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 24 0.05% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 9 0.02% 96.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 51 0.11% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 50 0.11% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 23 0.05% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 20 0.04% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 23 0.05% 97.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 51 0.11% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 49 0.11% 97.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 7 0.02% 97.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 28 0.06% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 86 0.19% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 45 0.10% 97.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 319 0.69% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.00% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 8 0.02% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 15 0.03% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 7 0.02% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 1 0.00% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 2 0.00% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 319 0.69% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 3 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 4 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12803 3 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 3 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 5 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 38 0.08% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 173 0.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 46334 # Bytes accessed per row activation +system.physmem.totQLat 8608105750 # Total ticks spent queuing +system.physmem.totMemAccLat 16109367000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2252845000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5248416250 # Total ticks spent accessing banks +system.physmem.avgQLat 19104.97 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11648.42 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 35753.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 14.36 # Average write queue length over time -system.physmem.readRowHits 435126 # Number of row buffer hits during reads -system.physmem.writeRowHits 97620 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.88 # Row buffer hit rate for writes -system.physmem.avgGap 3318929.48 # Average gap between requests -system.membus.throughput 19341454 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296468 # Transaction distribution -system.membus.trans_dist::ReadResp 296394 # Transaction distribution -system.membus.trans_dist::WriteReq 13061 # Transaction distribution -system.membus.trans_dist::WriteResp 13061 # Transaction distribution -system.membus.trans_dist::Writeback 122210 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9880 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5735 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4929 # Transaction distribution -system.membus.trans_dist::ReadExReq 162867 # Transaction distribution -system.membus.trans_dist::ReadExResp 162463 # Transaction distribution -system.membus.trans_dist::BadAddressError 74 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40510 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 921241 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 148 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 961899 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1086565 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73866 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31383040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31456906 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36765002 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36765002 # Total data (bytes) -system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 37911498 # Layer occupancy (ticks) +system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.81 # Average write queue length when enqueuing +system.physmem.readRowHits 429097 # Number of row buffer hits during reads +system.physmem.writeRowHits 97193 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.23 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.63 # Row buffer hit rate for writes +system.physmem.avgGap 3325854.28 # Average gap between requests +system.physmem.pageHitRate 91.91 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 19299112 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296504 # Transaction distribution +system.membus.trans_dist::ReadResp 296255 # Transaction distribution +system.membus.trans_dist::WriteReq 12358 # Transaction distribution +system.membus.trans_dist::WriteResp 12358 # Transaction distribution +system.membus.trans_dist::Writeback 122060 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5288 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1522 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3409 # Transaction distribution +system.membus.trans_dist::ReadExReq 162296 # Transaction distribution +system.membus.trans_dist::ReadExResp 162161 # Transaction distribution +system.membus.trans_dist::BadAddressError 249 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 909601 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 498 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 949201 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1073861 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68234 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31344192 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31412426 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307584 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5307584 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36720010 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36720010 # Total data (bytes) +system.membus.snoop_data_through_bus 38336 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 36331000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1609327499 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1605524497 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 93500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 312000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3831145563 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3818350840 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376230495 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376337493 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 344151 # number of replacements -system.l2c.tags.tagsinuse 65253.870311 # Cycle average of tags in use -system.l2c.tags.total_refs 2581362 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 409161 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.308915 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 6889943750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53541.051154 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5362.839741 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6144.208257 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 141.383324 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 64.387836 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.816972 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081830 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.093753 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002157 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000982 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995695 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 862836 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 735075 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 214357 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 69353 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1881621 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 822225 # number of Writeback hits -system.l2c.Writeback_hits::total 822225 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 270 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 439 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 25 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 153625 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 26073 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179698 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 862836 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 888700 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 214357 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 95426 # number of demand (read+write) hits -system.l2c.demand_hits::total 2061319 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 862836 # number of overall hits -system.l2c.overall_hits::cpu0.data 888700 # number of overall hits -system.l2c.overall_hits::cpu1.inst 214357 # number of overall hits -system.l2c.overall_hits::cpu1.data 95426 # number of overall hits -system.l2c.overall_hits::total 2061319 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 14080 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273430 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1180 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 427 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289117 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2676 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1075 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3751 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 425 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 454 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 879 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114757 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6453 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121210 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 14080 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 388187 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1180 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6880 # number of demand (read+write) misses -system.l2c.demand_misses::total 410327 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 14080 # number of overall misses -system.l2c.overall_misses::cpu0.data 388187 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1180 # number of overall misses -system.l2c.overall_misses::cpu1.data 6880 # number of overall misses -system.l2c.overall_misses::total 410327 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1210878995 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17193583984 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 109764250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 37725999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18551953228 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1076463 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 4839759 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 5916222 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 977458 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 93496 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1070954 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9311235979 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 722690467 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10033926446 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1210878995 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 26504819963 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 109764250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 760416466 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 28585879674 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1210878995 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 26504819963 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 109764250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 760416466 # number of overall miss cycles -system.l2c.overall_miss_latency::total 28585879674 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 876916 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1008505 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 215537 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 69780 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2170738 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 822225 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 822225 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2845 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1345 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4190 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 468 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 479 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 947 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 268382 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 32526 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300908 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 876916 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1276887 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 215537 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 102306 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2471646 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 876916 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1276887 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 215537 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 102306 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2471646 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.016056 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.271124 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005475 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.006119 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.133188 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940598 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.799257 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.895227 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.908120 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.947808 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.928194 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.427588 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.198395 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.402814 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.016056 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.304010 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005475 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.067249 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.166014 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.016056 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.304010 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005475 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.067249 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.166014 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85999.928622 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 62881.117595 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 93020.550847 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 88351.285714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 64167.631886 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 402.265695 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4502.101395 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1577.238603 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2299.901176 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 205.938326 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1218.377702 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81138.719024 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 111992.943902 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 82781.341853 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 85999.928622 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 68278.484243 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 93020.550847 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 110525.649128 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 69666.094783 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 85999.928622 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 68278.484243 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 93020.550847 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 110525.649128 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 69666.094783 # average overall miss latency +system.l2c.tags.replacements 343738 # number of replacements +system.l2c.tags.tagsinuse 65291.635140 # Cycle average of tags in use +system.l2c.tags.total_refs 2609074 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 408707 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.383727 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7069563750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 53622.087129 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4120.650208 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5604.001242 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1368.077401 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 576.819161 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.818208 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062876 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.085510 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.020875 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008802 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 744945 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 568804 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 325372 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 253262 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1892383 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 840158 # number of Writeback hits +system.l2c.Writeback_hits::total 840158 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 141 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 87 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 228 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 35 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 143496 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 47101 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 190597 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 744945 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 712300 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 325372 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 300363 # number of demand (read+write) hits +system.l2c.demand_hits::total 2082980 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 744945 # number of overall hits +system.l2c.overall_hits::cpu0.data 712300 # number of overall hits +system.l2c.overall_hits::cpu1.inst 325372 # number of overall hits +system.l2c.overall_hits::cpu1.data 300363 # number of overall hits +system.l2c.overall_hits::total 2082980 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11483 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 272043 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3807 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1819 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289152 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2542 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 549 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3091 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 55 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 155 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 106452 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 14320 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 120772 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 11483 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 378495 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3807 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16139 # number of demand (read+write) misses +system.l2c.demand_misses::total 409924 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11483 # number of overall misses +system.l2c.overall_misses::cpu0.data 378495 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3807 # number of overall misses +system.l2c.overall_misses::cpu1.data 16139 # number of overall misses +system.l2c.overall_misses::total 409924 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 923162249 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 17695673499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 318789981 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 142364996 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 19079990725 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 555479 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 1281945 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1837424 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 201494 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 69497 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 270991 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8670131391 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1451250197 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10121381588 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 923162249 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 26365804890 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 318789981 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1593615193 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 29201372313 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 923162249 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 26365804890 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 318789981 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1593615193 # number of overall miss cycles +system.l2c.overall_miss_latency::total 29201372313 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 756428 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 840847 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 329179 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 255081 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2181535 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 840158 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 840158 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2683 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 636 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3319 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 90 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 131 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 221 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 249948 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 61421 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 311369 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 756428 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1090795 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 329179 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 316502 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2492904 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 756428 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1090795 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 329179 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 316502 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2492904 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015181 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.323534 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.011565 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.007131 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.132545 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947447 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.863208 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.931305 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.611111 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.763359 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.701357 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.425897 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.233145 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.387874 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015181 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.346990 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011565 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.050992 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.164436 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015181 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.346990 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011565 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.050992 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.164436 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80393.821214 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 65047.339939 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83737.846336 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 78265.528312 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 65986.023700 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 218.520456 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2335.054645 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 594.443222 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3663.527273 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 694.970000 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1748.329032 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81446.392656 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101344.287500 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 83805.696585 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 80393.821214 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 69659.585701 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 83737.846336 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 98743.118719 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71236.064034 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 80393.821214 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 69659.585701 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 83737.846336 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 98743.118719 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71236.064034 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -537,125 +601,125 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80690 # number of writebacks -system.l2c.writebacks::total 80690 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 80540 # number of writebacks +system.l2c.writebacks::total 80540 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 14072 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 273429 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1171 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 427 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289099 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2676 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1075 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3751 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 425 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 454 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 879 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 114757 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 6453 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 121210 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 14072 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 388186 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1171 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6880 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 410309 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 14072 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 388186 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1171 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6880 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 410309 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1031878505 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 13784019266 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 94337500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 32390501 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 14942625772 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 26984633 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 10773037 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 37757670 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4256416 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4544453 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 8800869 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7896551021 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 642755533 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8539306554 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1031878505 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 21680570287 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 94337500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 675146034 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 23481932326 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1031878505 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 21680570287 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 94337500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 675146034 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 23481932326 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1367321000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 22027000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1389348000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2025100000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 585946999 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2611046999 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3392421000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 607973999 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4000394999 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016047 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.271123 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005433 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006119 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.133180 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940598 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.799257 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.895227 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.908120 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.947808 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.928194 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.427588 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.198395 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.402814 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016047 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.304010 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005433 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.067249 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.166006 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016047 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.304010 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005433 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.067249 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.166006 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 73328.489554 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50411.694685 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 80561.485909 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75855.974239 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 51686.881560 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10083.943572 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.429767 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10066.027726 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.096471 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.808370 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.365188 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68811.061818 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99605.692391 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 70450.511954 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73328.489554 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55850.984546 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 80561.485909 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98131.690988 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57229.873890 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73328.489554 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55850.984546 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80561.485909 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98131.690988 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57229.873890 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 11476 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 272042 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 3797 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1819 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289134 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2542 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 549 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3091 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 55 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 100 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 155 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 106452 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 14320 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 120772 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 11476 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 378494 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 3797 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 16139 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 409906 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 11476 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 378494 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 3797 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 16139 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 409906 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 777853501 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14301350001 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270265519 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 144194502 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15493663523 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25563003 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5558045 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 31121048 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 600552 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1003598 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 1604150 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7364952609 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1275013301 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8639965910 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 777853501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 21666302610 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 270265519 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1419207803 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 24133629433 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 777853501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 21666302610 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 270265519 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1419207803 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 24133629433 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 929130500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 460152500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1389283000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1572515500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 890654999 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2463170499 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2501646000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1350807499 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3852453499 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.323533 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.007131 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.132537 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.947447 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.863208 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.931305 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.611111 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.763359 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.701357 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425897 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.233145 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.387874 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.346989 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.050992 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.164429 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.346989 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.050992 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.164429 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52570.375166 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79271.304013 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 53586.446156 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10056.256098 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10123.943534 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10068.278227 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10919.127273 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.980000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10349.354839 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69185.666864 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89037.241690 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 71539.478604 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57243.450649 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87936.539005 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58876.009214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57243.450649 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87936.539005 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58876.009214 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -666,39 +730,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.476417 # Cycle average of tags in use +system.iocache.tags.replacements 41697 # number of replacements +system.iocache.tags.tagsinuse 0.224170 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711329338000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.476417 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.029776 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.029776 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.tags.warmup_cycle 1712302770000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.224170 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.014011 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.014011 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses +system.iocache.ReadReq_misses::total 177 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21570383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21570383 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10493964012 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10493964012 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10515534395 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10515534395 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10515534395 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10515534395 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses +system.iocache.demand_misses::total 41729 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses +system.iocache.overall_misses::total 41729 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21589383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21589383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12994516805 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12994516805 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13016106188 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13016106188 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13016106188 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13016106188 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -707,40 +771,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123259.331429 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123259.331429 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 252550.154313 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 252550.154313 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 252007.918015 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 252007.918015 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 252007.918015 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 252007.918015 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 275771 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121973.915254 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 121973.915254 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312729.033621 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 312729.033621 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 311919.916317 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 311919.916317 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 404619 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27285 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29217 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.107055 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.848752 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12468883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12468883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8331886522 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8331886522 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8344355405 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8344355405 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8344355405 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8344355405 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12384383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12384383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10832260819 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10832260819 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10844645202 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10844645202 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10844645202 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10844645202 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -749,14 +813,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71250.760000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71250.760000 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 200517.099586 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 200517.099586 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199974.965969 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 199974.965969 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199974.965969 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 199974.965969 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69968.265537 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 69968.265537 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260691.683168 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 260691.683168 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -770,35 +834,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12458299 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10491650 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 332886 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8054816 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5283733 # Number of BTB hits +system.cpu0.branchPred.lookups 10889682 # Number of BP lookups +system.cpu0.branchPred.condPredicted 9229516 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 284462 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7161619 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4680131 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.597191 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 799392 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28656 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.350181 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 674122 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 25966 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8872852 # DTB read hits -system.cpu0.dtb.read_misses 32010 # DTB read misses -system.cpu0.dtb.read_acv 540 # DTB read access violations -system.cpu0.dtb.read_accesses 628428 # DTB read accesses -system.cpu0.dtb.write_hits 5797852 # DTB write hits -system.cpu0.dtb.write_misses 8130 # DTB write misses -system.cpu0.dtb.write_acv 348 # DTB write access violations -system.cpu0.dtb.write_accesses 210128 # DTB write accesses -system.cpu0.dtb.data_hits 14670704 # DTB hits -system.cpu0.dtb.data_misses 40140 # DTB misses -system.cpu0.dtb.data_acv 888 # DTB access violations -system.cpu0.dtb.data_accesses 838556 # DTB accesses -system.cpu0.itb.fetch_hits 994919 # ITB hits -system.cpu0.itb.fetch_misses 28800 # ITB misses -system.cpu0.itb.fetch_acv 922 # ITB acv -system.cpu0.itb.fetch_accesses 1023719 # ITB accesses +system.cpu0.dtb.read_hits 7794998 # DTB read hits +system.cpu0.dtb.read_misses 29740 # DTB read misses +system.cpu0.dtb.read_acv 552 # DTB read access violations +system.cpu0.dtb.read_accesses 624038 # DTB read accesses +system.cpu0.dtb.write_hits 5176736 # DTB write hits +system.cpu0.dtb.write_misses 7776 # DTB write misses +system.cpu0.dtb.write_acv 327 # DTB write access violations +system.cpu0.dtb.write_accesses 207382 # DTB write accesses +system.cpu0.dtb.data_hits 12971734 # DTB hits +system.cpu0.dtb.data_misses 37516 # DTB misses +system.cpu0.dtb.data_acv 879 # DTB access violations +system.cpu0.dtb.data_accesses 831420 # DTB accesses +system.cpu0.itb.fetch_hits 929400 # ITB hits +system.cpu0.itb.fetch_misses 28175 # ITB misses +system.cpu0.itb.fetch_acv 908 # ITB acv +system.cpu0.itb.fetch_accesses 957575 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -811,269 +875,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 114636003 # number of cpu cycles simulated +system.cpu0.numCycles 103787820 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25048083 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63888139 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12458299 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6083125 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12009946 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1716539 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 37364333 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31995 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 196940 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 358937 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 467 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7724257 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 222992 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 76114982 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.839364 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.177033 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 21704485 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 55964987 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 10889682 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5354253 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10541115 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1495269 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 32108430 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 29198 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 196165 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 243475 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 129 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6808420 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 194219 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 65778101 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.850815 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.187217 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64105036 84.22% 84.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 766655 1.01% 85.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1565630 2.06% 87.29% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 705022 0.93% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2586372 3.40% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 523946 0.69% 92.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 578047 0.76% 93.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 832534 1.09% 94.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4451740 5.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 55236986 83.97% 83.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 687368 1.04% 85.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1350712 2.05% 87.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 596944 0.91% 87.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2343219 3.56% 91.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 450390 0.68% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 484863 0.74% 92.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 769593 1.17% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3858026 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 76114982 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.108677 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.557313 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26317520 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36878715 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10917325 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 932522 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1068899 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 511897 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35733 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62704701 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 106993 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1068899 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27334042 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 15040257 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18326535 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10227103 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4118144 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59323627 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7153 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 638131 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1449994 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39722637 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72231674 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72093935 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 128190 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34859464 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4863165 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1453792 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 211881 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11242711 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9290886 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6078694 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1146384 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 744084 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52609114 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1811011 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51412755 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 100173 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5939256 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3114263 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1226583 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 76114982 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.675462 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.326460 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 65778101 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.104923 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.539225 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 22868260 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 31583202 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9551685 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 850413 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 924540 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 430365 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 30891 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 54921627 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 95919 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 924540 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 23764379 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12229388 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16273784 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8983229 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3602779 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 51919548 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6908 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 427524 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1365609 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 34775855 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 63273064 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 63154051 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 110251 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30610760 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4165087 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1306243 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 192817 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 9794386 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8157712 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5414054 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 996311 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 651476 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 46072688 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1607529 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 45052642 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 77910 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5101692 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2707567 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1088536 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 65778101 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.684919 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.328831 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 53279780 70.00% 70.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10372988 13.63% 83.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4693410 6.17% 89.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3092664 4.06% 93.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2443569 3.21% 97.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1213853 1.59% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 652140 0.86% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 314050 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52528 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 45611929 69.34% 69.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9242272 14.05% 83.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4206709 6.40% 89.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2691383 4.09% 93.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2059923 3.13% 97.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1077701 1.64% 98.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 567124 0.86% 99.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 276618 0.42% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 44442 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 76114982 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 65778101 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 82827 12.15% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 318873 46.78% 58.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 279966 41.07% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 64943 10.84% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 279384 46.63% 57.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 254855 42.53% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35420825 68.90% 68.90% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56384 0.11% 69.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.01% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15702 0.03% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9231506 17.96% 87.00% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5866326 11.41% 98.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 816348 1.59% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 30907747 68.60% 68.61% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47065 0.10% 68.72% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 14613 0.03% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8107891 18.00% 86.75% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5235503 11.62% 98.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 734167 1.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51412755 # Type of FU issued -system.cpu0.iq.rate 0.448487 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 681666 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013259 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 179170597 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60104783 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50356616 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 551733 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 267128 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 260409 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51801972 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 288664 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 541765 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 45052642 # Type of FU issued +system.cpu0.iq.rate 0.434084 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 599182 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013300 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 156086675 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 52562386 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44135345 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 473801 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 230205 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 223474 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 45400371 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 247676 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 493959 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1139912 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4116 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12815 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 456622 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 994643 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3486 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 10933 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 382957 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18431 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 154294 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13548 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 145981 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1068899 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10746647 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 795792 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57645786 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 623000 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9290886 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6078694 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1595130 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 581617 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5318 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12815 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 164656 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 351489 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 516145 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51022070 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8928198 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 390684 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 924540 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8545801 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 700799 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50460891 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 559365 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8157712 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5414054 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1419298 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 572111 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4914 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 10933 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 138244 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 310094 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 448338 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 44721018 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 7845228 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 331623 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3225661 # number of nop insts executed -system.cpu0.iew.exec_refs 14747797 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8123465 # Number of branches executed -system.cpu0.iew.exec_stores 5819599 # Number of stores executed -system.cpu0.iew.exec_rate 0.445079 # Inst execution rate -system.cpu0.iew.wb_sent 50710143 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50617025 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25247170 # num instructions producing a value -system.cpu0.iew.wb_consumers 34011376 # num instructions consuming a value +system.cpu0.iew.exec_nop 2780674 # number of nop insts executed +system.cpu0.iew.exec_refs 13041346 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7066025 # Number of branches executed +system.cpu0.iew.exec_stores 5196118 # Number of stores executed +system.cpu0.iew.exec_rate 0.430889 # Inst execution rate +system.cpu0.iew.wb_sent 44442278 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44358819 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22095606 # num instructions producing a value +system.cpu0.iew.wb_consumers 29563187 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.441546 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742315 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.427399 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.747403 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6411331 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 584428 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 481702 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75046083 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.681415 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.595696 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5494607 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 518993 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 418437 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 64853561 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.691924 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.608025 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 55785925 74.34% 74.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8029512 10.70% 85.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4410175 5.88% 90.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2388789 3.18% 94.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1317256 1.76% 95.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 560978 0.75% 96.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 472301 0.63% 97.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 435634 0.58% 97.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1645513 2.19% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 47955107 73.94% 73.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7091089 10.93% 84.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3807248 5.87% 90.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2121571 3.27% 94.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1151711 1.78% 95.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 474089 0.73% 96.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 405970 0.63% 97.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 383893 0.59% 97.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1462883 2.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75046083 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51137491 # Number of instructions committed -system.cpu0.commit.committedOps 51137491 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 64853561 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 44873722 # Number of instructions committed +system.cpu0.commit.committedOps 44873722 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13773046 # Number of memory references committed -system.cpu0.commit.loads 8150974 # Number of loads committed -system.cpu0.commit.membars 198820 # Number of memory barriers committed -system.cpu0.commit.branches 7724848 # Number of branches committed -system.cpu0.commit.fp_insts 258424 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47356368 # Number of committed integer instructions. -system.cpu0.commit.function_calls 655486 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1645513 # number cycles where commit BW limit reached +system.cpu0.commit.refs 12194166 # Number of memory references committed +system.cpu0.commit.loads 7163069 # Number of loads committed +system.cpu0.commit.membars 173899 # Number of memory barriers committed +system.cpu0.commit.branches 6736138 # Number of branches committed +system.cpu0.commit.fp_insts 221634 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 41596674 # Number of committed integer instructions. +system.cpu0.commit.function_calls 557213 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1462883 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 130752703 # The number of ROB reads -system.cpu0.rob.rob_writes 116166541 # The number of ROB writes -system.cpu0.timesIdled 1097555 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 38521021 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3690835342 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48197169 # Number of Instructions Simulated -system.cpu0.committedOps 48197169 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 48197169 # Number of Instructions Simulated -system.cpu0.cpi 2.378480 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.378480 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.420437 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.420437 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67125195 # number of integer regfile reads -system.cpu0.int_regfile_writes 36645952 # number of integer regfile writes -system.cpu0.fp_regfile_reads 127833 # number of floating regfile reads -system.cpu0.fp_regfile_writes 129422 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1709874 # number of misc regfile reads -system.cpu0.misc_regfile_writes 817230 # number of misc regfile writes +system.cpu0.rob.rob_reads 113567039 # The number of ROB reads +system.cpu0.rob.rob_writes 101661188 # The number of ROB writes +system.cpu0.timesIdled 942687 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 38009719 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3705537551 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 42330060 # Number of Instructions Simulated +system.cpu0.committedOps 42330060 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 42330060 # Number of Instructions Simulated +system.cpu0.cpi 2.451870 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.451870 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.407852 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.407852 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 58864464 # number of integer regfile reads +system.cpu0.int_regfile_writes 32110567 # number of integer regfile writes +system.cpu0.fp_regfile_reads 109878 # number of floating regfile reads +system.cpu0.fp_regfile_writes 110737 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1513799 # number of misc regfile reads +system.cpu0.misc_regfile_writes 739168 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1105,49 +1169,49 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 111571177 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2198759 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2198668 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13061 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13061 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 822225 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10020 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5803 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 15823 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 343740 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302191 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 74 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1753935 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3363647 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 431103 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 300395 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5849080 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56122624 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 129969996 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13794368 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 11000190 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 210887178 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 210876874 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 1413952 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4971684979 # Layer occupancy (ticks) +system.toL2Bus.throughput 112875870 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2213010 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2212746 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12358 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12358 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 840158 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 5353 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1588 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 6941 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 354001 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 312453 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 249 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1512954 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2808902 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 658389 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 920655 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5900900 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48411392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 107554025 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21067456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 36346017 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 213378890 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 213368266 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 1622464 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5059270351 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3951712593 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3408360184 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5887546567 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5017953643 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 970657716 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1482953497 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 517795038 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1437659 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7369 # Transaction distribution -system.iobus.trans_dist::ReadResp 7369 # Transaction distribution -system.iobus.trans_dist::WriteReq 54613 # Transaction distribution -system.iobus.trans_dist::WriteResp 54613 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer3.occupancy 1519289016 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) +system.iobus.throughput 1433257 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7370 # Transaction distribution +system.iobus.trans_dist::ReadResp 7370 # Transaction distribution +system.iobus.trans_dist::WriteReq 53910 # Transaction distribution +system.iobus.trans_dist::WriteResp 53910 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10510 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1158,12 +1222,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40510 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123964 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122560 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1174,14 +1238,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 73866 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2735490 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2735490 # Total data (bytes) -system.iobus.reqLayer0.occupancy 11269000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 68234 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2729874 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2729874 # Total data (bytes) +system.iobus.reqLayer0.occupancy 9865000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 350000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1201,253 +1265,253 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378285900 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377768695 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27449000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26744000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43112505 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42672507 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 876399 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.760309 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6802362 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 876908 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.757213 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26019048250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.760309 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995626 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995626 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6802362 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6802362 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6802362 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6802362 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6802362 # number of overall hits -system.cpu0.icache.overall_hits::total 6802362 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 921891 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 921891 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 921891 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 921891 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 921891 # number of overall misses -system.cpu0.icache.overall_misses::total 921891 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13290047828 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13290047828 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13290047828 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13290047828 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13290047828 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13290047828 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7724253 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7724253 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7724253 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7724253 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7724253 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7724253 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119350 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.119350 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119350 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.119350 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119350 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.119350 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14416.072863 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14416.072863 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14416.072863 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14416.072863 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14416.072863 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14416.072863 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6191 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1109 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 232 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.685345 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 554.500000 # average number of cycles each access was blocked +system.cpu0.icache.tags.replacements 755849 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.693536 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6013634 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 756358 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.950777 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26716185250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693536 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995495 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995495 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6013634 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6013634 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6013634 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6013634 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6013634 # number of overall hits +system.cpu0.icache.overall_hits::total 6013634 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 794785 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 794785 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 794785 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 794785 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 794785 # number of overall misses +system.cpu0.icache.overall_misses::total 794785 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11289773018 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11289773018 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11289773018 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11289773018 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11289773018 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11289773018 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6808419 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6808419 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6808419 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6808419 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6808419 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6808419 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116736 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.116736 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116736 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.116736 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116736 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.116736 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14204.813903 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14204.813903 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14204.813903 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14204.813903 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14204.813903 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14204.813903 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5327 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 127 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 41.944882 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44872 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 44872 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 44872 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 44872 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 44872 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 44872 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 877019 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 877019 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 877019 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 877019 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 877019 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 877019 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10904529395 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10904529395 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10904529395 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10904529395 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10904529395 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10904529395 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113541 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113541 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113541 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12433.629596 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12433.629596 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12433.629596 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 38259 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 38259 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 38259 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 38259 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 38259 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 38259 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 756526 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 756526 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 756526 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 756526 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 756526 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 756526 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9285394312 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9285394312 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9285394312 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9285394312 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9285394312 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9285394312 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111116 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.111116 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.111116 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12273.727951 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12273.727951 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12273.727951 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1278910 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.619274 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10469394 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1279422 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.182909 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 25842000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.619274 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987538 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.987538 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6440836 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6440836 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3667453 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3667453 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 162740 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 162740 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 187465 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 187465 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10108289 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10108289 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10108289 # number of overall hits -system.cpu0.dcache.overall_hits::total 10108289 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1585845 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1585845 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1749611 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1749611 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20563 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20563 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2808 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2808 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3335456 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3335456 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3335456 # number of overall misses -system.cpu0.dcache.overall_misses::total 3335456 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40055257591 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 40055257591 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78246234000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 78246234000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 299434996 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 299434996 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20885924 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20885924 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 118301491591 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 118301491591 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 118301491591 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 118301491591 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8026681 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8026681 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5417064 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5417064 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183303 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183303 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190273 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 190273 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13443745 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13443745 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13443745 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13443745 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197572 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197572 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322981 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.322981 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112180 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112180 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014758 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014758 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248105 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248105 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248105 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248105 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25257.990277 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25257.990277 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44722.074793 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44722.074793 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14561.834168 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14561.834168 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7438.007123 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7438.007123 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35467.861543 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35467.861543 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35467.861543 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35467.861543 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2886351 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1258 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 51822 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 55.697407 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 179.714286 # average number of cycles each access was blocked +system.cpu0.dcache.tags.replacements 1092682 # number of replacements +system.cpu0.dcache.tags.tagsinuse 465.850340 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9201265 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1093194 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.416864 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 25754000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 465.850340 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.909864 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.909864 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5673895 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5673895 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3199282 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3199282 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148885 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 148885 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 172652 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 172652 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8873177 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8873177 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8873177 # number of overall hits +system.cpu0.dcache.overall_hits::total 8873177 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1348613 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1348613 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1646140 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1646140 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16729 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16729 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 773 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 773 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2994753 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2994753 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2994753 # number of overall misses +system.cpu0.dcache.overall_misses::total 2994753 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36556454998 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 36556454998 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 72896722210 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 72896722210 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251362748 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 251362748 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4670052 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4670052 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 109453177208 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 109453177208 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 109453177208 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 109453177208 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7022508 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7022508 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4845422 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4845422 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 165614 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 165614 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 173425 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 173425 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11867930 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11867930 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11867930 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11867930 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.192042 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.192042 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.339731 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.339731 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101012 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101012 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004457 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004457 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.252340 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.252340 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.252340 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.252340 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27106.705184 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27106.705184 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44283.428026 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44283.428026 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15025.569251 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15025.569251 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6041.464424 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6041.464424 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36548.315406 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36548.315406 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36548.315406 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36548.315406 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2779952 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1302 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 46345 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 59.983860 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 162.750000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 752999 # number of writebacks -system.cpu0.dcache.writebacks::total 752999 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 583027 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 583027 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1475561 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1475561 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4528 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4528 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2058588 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2058588 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2058588 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2058588 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1002818 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1002818 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 274050 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 274050 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16035 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16035 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2807 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2807 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1276868 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1276868 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1276868 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1276868 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26563866972 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26563866972 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11468217837 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11468217837 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 177500254 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 177500254 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15271076 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15271076 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38032084809 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38032084809 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38032084809 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38032084809 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459298500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459298500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2147907499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2147907499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3607205999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3607205999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.124936 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.124936 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050590 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050590 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087478 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087478 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014752 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014752 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094979 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094979 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094979 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094979 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26489.220349 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26489.220349 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41847.173279 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41847.173279 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11069.551232 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11069.551232 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5440.354827 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5440.354827 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29785.447524 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29785.447524 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29785.447524 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29785.447524 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 588957 # number of writebacks +system.cpu0.dcache.writebacks::total 588957 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 514989 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 514989 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1392541 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1392541 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3960 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3960 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1907530 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1907530 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1907530 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1907530 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 833624 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 833624 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 253599 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 253599 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12769 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12769 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 773 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 773 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1087223 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1087223 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1087223 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1087223 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24857542918 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24857542918 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10684541815 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10684541815 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 151212250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 151212250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3123948 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3123948 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35542084733 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 35542084733 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35542084733 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 35542084733 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 990981000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 990981000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1668402499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1668402499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2659383499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2659383499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118707 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118707 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052338 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052338 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.077101 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.077101 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004457 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004457 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091610 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.091610 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091610 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.091610 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29818.650756 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29818.650756 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42131.640168 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42131.640168 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11842.137207 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11842.137207 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4041.329884 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4041.329884 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32690.703501 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32690.703501 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32690.703501 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32690.703501 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1455,35 +1519,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2517085 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2083961 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 72869 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1481224 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 844711 # Number of BTB hits +system.cpu1.branchPred.lookups 4005476 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3286567 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 126561 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2463252 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1409799 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.027904 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 172550 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7415 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.233243 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 290076 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 11654 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1869470 # DTB read hits -system.cpu1.dtb.read_misses 10476 # DTB read misses -system.cpu1.dtb.read_acv 22 # DTB read access violations -system.cpu1.dtb.read_accesses 321268 # DTB read accesses -system.cpu1.dtb.write_hits 1203365 # DTB write hits -system.cpu1.dtb.write_misses 2061 # DTB write misses -system.cpu1.dtb.write_acv 64 # DTB write access violations -system.cpu1.dtb.write_accesses 130567 # DTB write accesses -system.cpu1.dtb.data_hits 3072835 # DTB hits -system.cpu1.dtb.data_misses 12537 # DTB misses -system.cpu1.dtb.data_acv 86 # DTB access violations -system.cpu1.dtb.data_accesses 451835 # DTB accesses -system.cpu1.itb.fetch_hits 424254 # ITB hits -system.cpu1.itb.fetch_misses 6539 # ITB misses -system.cpu1.itb.fetch_acv 190 # ITB acv -system.cpu1.itb.fetch_accesses 430793 # ITB accesses +system.cpu1.dtb.read_hits 2861061 # DTB read hits +system.cpu1.dtb.read_misses 13171 # DTB read misses +system.cpu1.dtb.read_acv 26 # DTB read access violations +system.cpu1.dtb.read_accesses 327320 # DTB read accesses +system.cpu1.dtb.write_hits 1771736 # DTB write hits +system.cpu1.dtb.write_misses 2413 # DTB write misses +system.cpu1.dtb.write_acv 61 # DTB write access violations +system.cpu1.dtb.write_accesses 133954 # DTB write accesses +system.cpu1.dtb.data_hits 4632797 # DTB hits +system.cpu1.dtb.data_misses 15584 # DTB misses +system.cpu1.dtb.data_acv 87 # DTB access violations +system.cpu1.dtb.data_accesses 461274 # DTB accesses +system.cpu1.itb.fetch_hits 484886 # ITB hits +system.cpu1.itb.fetch_misses 6783 # ITB misses +system.cpu1.itb.fetch_acv 213 # ITB acv +system.cpu1.itb.fetch_accesses 491669 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1496,508 +1560,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 15249987 # number of cpu cycles simulated +system.cpu1.numCycles 26365345 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5781097 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 11894429 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2517085 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1017261 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2131045 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 385761 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 6016414 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 25794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 62392 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 56888 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1433413 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 48410 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14320297 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.830599 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.206016 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8788859 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 19229785 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4005476 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1699875 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 3495206 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 620790 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 10702778 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65519 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 161249 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 2272198 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 84032 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 23644267 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.813296 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.175765 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12189252 85.12% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 136413 0.95% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 229060 1.60% 87.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 170637 1.19% 88.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 294592 2.06% 90.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 114916 0.80% 91.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 126454 0.88% 92.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 195471 1.36% 93.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 863502 6.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 20149061 85.22% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 201364 0.85% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 434975 1.84% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 271433 1.15% 89.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 534220 2.26% 91.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 181805 0.77% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 209247 0.88% 92.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 254511 1.08% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1407651 5.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14320297 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.165055 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.779963 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5724387 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6255039 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1992849 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 108261 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 239760 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 108451 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 6971 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 11669639 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 20547 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 239760 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5925475 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 420572 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5212839 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1896462 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 625187 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10812976 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 71 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 55937 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 153486 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 7119549 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12930789 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12872049 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52940 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6082585 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1036964 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 436590 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 40484 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1926881 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1976180 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1276143 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 178422 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 98267 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9491737 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 473513 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9233560 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 29148 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1376057 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 698810 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 340347 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14320297 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.644788 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.319506 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 23644267 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.151922 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.729358 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8879389 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 10928600 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 3243065 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 199967 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 393245 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 183870 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 12999 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 18844715 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 38529 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 393245 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 9206755 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3122476 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6754638 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 3034107 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1133044 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 17630254 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 270 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 267231 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 248854 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 11666322 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 21081705 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 21016911 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58919 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 9884504 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1781818 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 561630 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 56869 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3357033 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 3030330 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1870850 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 319037 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 184061 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 15497472 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 666578 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 15021403 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 38685 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2244261 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1133404 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 478003 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 23644267 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.635308 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.316901 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10263877 71.67% 71.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1860247 12.99% 84.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 792265 5.53% 90.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 533948 3.73% 93.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 454852 3.18% 97.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 207190 1.45% 98.55% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 132078 0.92% 99.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 67607 0.47% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 8233 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 17155384 72.56% 72.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2869349 12.14% 84.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1269974 5.37% 90.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 909350 3.85% 93.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 787037 3.33% 97.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 325991 1.38% 98.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 202457 0.86% 99.47% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 106589 0.45% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 18136 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14320297 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 23644267 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3147 1.66% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 101977 53.82% 55.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 84363 44.52% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 18902 7.17% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 136410 51.75% 58.92% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 108303 41.08% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5756733 62.35% 62.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16005 0.17% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10795 0.12% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1955574 21.18% 83.87% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1226577 13.28% 97.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 262587 2.84% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 9862540 65.66% 65.68% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 23545 0.16% 65.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11158 0.07% 65.91% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.91% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.91% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.91% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2986833 19.88% 85.81% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1799237 11.98% 97.78% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 332801 2.22% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9233560 # Type of FU issued -system.cpu1.iq.rate 0.605480 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 189487 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020522 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 32803401 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11243674 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8968182 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 202651 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 99238 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 96146 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9314130 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 105391 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 90243 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 15021403 # Type of FU issued +system.cpu1.iq.rate 0.569740 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 263615 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.017549 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 53759316 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 18299643 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 14636122 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 230057 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 112007 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 108764 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 15161393 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 120099 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 139894 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 277299 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1341 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1688 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 122180 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 437460 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1072 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3446 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 176357 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 318 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 14956 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 5243 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 21515 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 239760 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 255964 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 40163 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10453412 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 142319 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1976180 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1276143 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 429143 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 33341 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1750 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1688 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 32963 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 95419 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 128382 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9148055 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1886987 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 85505 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 393245 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2412385 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 142199 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 17062579 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 198140 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 3030330 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1870850 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 597759 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 52684 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2595 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3446 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 61011 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 139338 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 200349 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 14878419 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2882425 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 142984 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 488162 # number of nop insts executed -system.cpu1.iew.exec_refs 3098273 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1362461 # Number of branches executed -system.cpu1.iew.exec_stores 1211286 # Number of stores executed -system.cpu1.iew.exec_rate 0.599873 # Inst execution rate -system.cpu1.iew.wb_sent 9092483 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9064328 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4254481 # num instructions producing a value -system.cpu1.iew.wb_consumers 5984515 # num instructions consuming a value +system.cpu1.iew.exec_nop 898529 # number of nop insts executed +system.cpu1.iew.exec_refs 4662637 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2338044 # Number of branches executed +system.cpu1.iew.exec_stores 1780212 # Number of stores executed +system.cpu1.iew.exec_rate 0.564317 # Inst execution rate +system.cpu1.iew.wb_sent 14784457 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 14744886 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 7139948 # num instructions producing a value +system.cpu1.iew.wb_consumers 10043269 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.594383 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.710915 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.559253 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.710919 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1421128 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 133166 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 121427 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 14080537 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.636506 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.577564 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2396118 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 188575 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 186792 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 23251022 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.628108 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.559407 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10719102 76.13% 76.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1572221 11.17% 87.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 583613 4.14% 91.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 356342 2.53% 93.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 255998 1.82% 95.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 100117 0.71% 96.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 105425 0.75% 97.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 105001 0.75% 97.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 282718 2.01% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 17812881 76.61% 76.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2343231 10.08% 86.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1160626 4.99% 91.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 598215 2.57% 94.25% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 379804 1.63% 95.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 180518 0.78% 96.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 173796 0.75% 97.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 135154 0.58% 97.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 466797 2.01% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 14080537 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8962351 # Number of instructions committed -system.cpu1.commit.committedOps 8962351 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 23251022 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 14604164 # Number of instructions committed +system.cpu1.commit.committedOps 14604164 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2852844 # Number of memory references committed -system.cpu1.commit.loads 1698881 # Number of loads committed -system.cpu1.commit.membars 42409 # Number of memory barriers committed -system.cpu1.commit.branches 1280511 # Number of branches committed -system.cpu1.commit.fp_insts 94891 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8306060 # Number of committed integer instructions. -system.cpu1.commit.function_calls 141484 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 282718 # number cycles where commit BW limit reached +system.cpu1.commit.refs 4287363 # Number of memory references committed +system.cpu1.commit.loads 2592870 # Number of loads committed +system.cpu1.commit.membars 62980 # Number of memory barriers committed +system.cpu1.commit.branches 2183593 # Number of branches committed +system.cpu1.commit.fp_insts 107360 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 13494360 # Number of committed integer instructions. +system.cpu1.commit.function_calls 233831 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 466797 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 24092433 # The number of ROB reads -system.cpu1.rob.rob_writes 21005155 # The number of ROB writes -system.cpu1.timesIdled 128904 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 929690 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3789568266 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8530162 # Number of Instructions Simulated -system.cpu1.committedOps 8530162 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 8530162 # Number of Instructions Simulated -system.cpu1.cpi 1.787772 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.787772 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.559355 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.559355 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11798212 # number of integer regfile reads -system.cpu1.int_regfile_writes 6449971 # number of integer regfile writes -system.cpu1.fp_regfile_reads 52607 # number of floating regfile reads -system.cpu1.fp_regfile_writes 52314 # number of floating regfile writes -system.cpu1.misc_regfile_reads 504098 # number of misc regfile reads -system.cpu1.misc_regfile_writes 209723 # number of misc regfile writes -system.cpu1.icache.tags.replacements 214995 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.564735 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1210101 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 215507 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.615135 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1878702632250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.564735 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919072 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.919072 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1210101 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1210101 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1210101 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1210101 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1210101 # number of overall hits -system.cpu1.icache.overall_hits::total 1210101 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 223312 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 223312 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 223312 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 223312 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 223312 # number of overall misses -system.cpu1.icache.overall_misses::total 223312 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3028009139 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3028009139 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3028009139 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3028009139 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3028009139 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3028009139 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1433413 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1433413 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1433413 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1433413 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1433413 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1433413 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.155790 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.155790 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.155790 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.155790 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.155790 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.155790 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13559.545116 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13559.545116 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13559.545116 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13559.545116 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13559.545116 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13559.545116 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 273 # number of cycles access was blocked +system.cpu1.rob.rob_reads 39695803 # The number of ROB reads +system.cpu1.rob.rob_writes 34392702 # The number of ROB writes +system.cpu1.timesIdled 272923 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2721078 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3782349185 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 13810279 # Number of Instructions Simulated +system.cpu1.committedOps 13810279 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 13810279 # Number of Instructions Simulated +system.cpu1.cpi 1.909110 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.909110 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.523804 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.523804 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 19249115 # number of integer regfile reads +system.cpu1.int_regfile_writes 10558811 # number of integer regfile writes +system.cpu1.fp_regfile_reads 58616 # number of floating regfile reads +system.cpu1.fp_regfile_writes 58623 # number of floating regfile writes +system.cpu1.misc_regfile_reads 636847 # number of misc regfile reads +system.cpu1.misc_regfile_writes 274262 # number of misc regfile writes +system.cpu1.icache.tags.replacements 328629 # number of replacements +system.cpu1.icache.tags.tagsinuse 504.249918 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1927863 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 329141 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.857256 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 49124844500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.249918 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984863 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.984863 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1927863 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1927863 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1927863 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1927863 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1927863 # number of overall hits +system.cpu1.icache.overall_hits::total 1927863 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 344335 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 344335 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 344335 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 344335 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 344335 # number of overall misses +system.cpu1.icache.overall_misses::total 344335 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4815194513 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4815194513 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4815194513 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4815194513 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4815194513 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4815194513 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2272198 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2272198 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2272198 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2272198 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2272198 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2272198 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.151543 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.151543 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.151543 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.151543 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.151543 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.151543 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13984.040289 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13984.040289 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13984.040289 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13984.040289 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1435 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 32 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 51 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 8.531250 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 28.137255 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7746 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 7746 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 7746 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 7746 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 7746 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 7746 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 215566 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 215566 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 215566 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 215566 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 215566 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 215566 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2508977533 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2508977533 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2508977533 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2508977533 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2508977533 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2508977533 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.150387 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.150387 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.150387 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.150387 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.150387 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.150387 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11639.022541 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11639.022541 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11639.022541 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11639.022541 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11639.022541 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11639.022541 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15125 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 15125 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 15125 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 15125 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 15125 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 15125 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329210 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 329210 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 329210 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 329210 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 329210 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 329210 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3979739752 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3979739752 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3979739752 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3979739752 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3979739752 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3979739752 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.144886 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.144886 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.144886 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12088.757182 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12088.757182 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12088.757182 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 104218 # number of replacements -system.cpu1.dcache.tags.tagsinuse 490.671059 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2506866 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 104618 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.962091 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 44824844250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 490.671059 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.958342 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.958342 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1537129 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1537129 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 905397 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 905397 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 30937 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 30937 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29831 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 29831 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2442526 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2442526 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2442526 # number of overall hits -system.cpu1.dcache.overall_hits::total 2442526 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 200186 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 200186 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 209846 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 209846 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5149 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5149 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2998 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2998 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 410032 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 410032 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 410032 # number of overall misses -system.cpu1.dcache.overall_misses::total 410032 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2816563957 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2816563957 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7378261443 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7378261443 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51136995 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 51136995 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22092953 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 22092953 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 10194825400 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 10194825400 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 10194825400 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 10194825400 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1737315 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1737315 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1115243 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1115243 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 36086 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 36086 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32829 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 32829 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2852558 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2852558 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2852558 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2852558 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.115227 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.115227 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188162 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.188162 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.142687 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142687 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.091322 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.091322 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143742 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.143742 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143742 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.143742 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14069.734932 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14069.734932 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35160.362566 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 35160.362566 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9931.442028 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9931.442028 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7369.230487 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7369.230487 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24863.487240 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 24863.487240 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24863.487240 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24863.487240 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 240672 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 330658 # number of replacements +system.cpu1.dcache.tags.tagsinuse 495.877996 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3531981 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 331060 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 10.668704 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 42038170500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 495.877996 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968512 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.968512 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2174883 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2174883 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1270139 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1270139 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 43234 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 43234 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 46255 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 46255 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3445022 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3445022 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3445022 # number of overall hits +system.cpu1.dcache.overall_hits::total 3445022 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 478937 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 478937 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 369959 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 369959 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7995 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 7995 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 815 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 815 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 848896 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 848896 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 848896 # number of overall misses +system.cpu1.dcache.overall_misses::total 848896 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7393539723 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 7393539723 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13842081157 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 13842081157 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 114418247 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 114418247 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5712098 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5712098 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 21235620880 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 21235620880 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 21235620880 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 21235620880 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2653820 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2653820 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1640098 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1640098 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 51229 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 51229 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 47070 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 47070 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4293918 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4293918 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4293918 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4293918 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.180471 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.180471 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.225571 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.225571 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156064 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156064 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.017315 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.017315 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.197697 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.197697 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.197697 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.197697 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15437.395154 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15437.395154 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37415.176160 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 37415.176160 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14311.225391 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14311.225391 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7008.709202 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7008.709202 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25015.574205 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 25015.574205 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25015.574205 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 25015.574205 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 432228 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3904 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 7570 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 61.647541 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 57.097490 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 69226 # number of writebacks -system.cpu1.dcache.writebacks::total 69226 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 124077 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 124077 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 172447 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 172447 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 558 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 558 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 296524 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 296524 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 296524 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 296524 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 76109 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 76109 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 37399 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 37399 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4591 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4591 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2996 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2996 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 113508 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 113508 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 113508 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 113508 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 856275217 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 856275217 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1088322932 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1088322932 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 34640753 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 34640753 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16100047 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16100047 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1944598149 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1944598149 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1944598149 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1944598149 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23613000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23613000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 620064002 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 620064002 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 643677002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 643677002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043808 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043808 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033534 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033534 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.127224 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.127224 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.091261 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.091261 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039792 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039792 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039792 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039792 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11250.643380 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11250.643380 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29100.321720 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29100.321720 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7545.361141 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7545.361141 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5373.847463 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5373.847463 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17131.815810 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17131.815810 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17131.815810 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17131.815810 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 251201 # number of writebacks +system.cpu1.dcache.writebacks::total 251201 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 211025 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 211025 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306586 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 306586 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1580 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1580 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 517611 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 517611 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 517611 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 517611 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 267912 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 267912 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 63373 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 63373 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6415 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6415 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 815 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 815 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 331285 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 331285 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 331285 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 331285 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3418270202 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3418270202 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2068179649 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2068179649 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71253503 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71253503 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4081902 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4081902 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5486449851 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5486449851 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5486449851 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5486449851 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 491833500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 491833500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 943255503 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 943255503 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1435089003 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1435089003 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.100953 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.100953 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038640 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038640 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.125222 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.125222 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.017315 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.017315 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.077152 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.077152 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.077152 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.077152 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12758.929059 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12758.929059 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32635.028309 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32635.028309 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11107.327046 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11107.327046 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5008.468712 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5008.468712 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16561.117621 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16561.117621 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16561.117621 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16561.117621 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2006,170 +2070,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6603 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 184198 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65080 40.52% 40.52% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.20% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 193 0.12% 41.92% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 93271 58.08% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 160599 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64086 49.21% 49.21% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.48% 50.79% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 193 0.15% 50.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63894 49.06% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 130228 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1861779564000 97.85% 97.85% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63861000 0.00% 97.85% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 571607000 0.03% 97.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 92660000 0.00% 97.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 40230450500 2.11% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1902738142500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984726 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4829 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 164539 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56531 39.74% 39.74% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 39.83% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.35% 41.18% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.20% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 83653 58.80% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 142256 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 55584 49.09% 49.09% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.21% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.70% 50.91% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.01% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55568 49.08% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 113224 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1866804619500 98.01% 98.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 62415000 0.00% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 563852000 0.03% 98.05% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8731500 0.00% 98.05% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 37224635500 1.95% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1904664253500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983248 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.685036 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810889 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed -system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed -system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 211 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.664268 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.795917 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed +system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed +system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.50% 38.61% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.49% 40.10% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.47% 43.56% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.99% 44.55% # number of syscalls executed +system.cpu0.kern.syscall::45 34 16.83% 61.39% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.49% 62.87% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.96% 66.83% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.46% 71.29% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.50% 71.78% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.48% 74.26% # number of syscalls executed +system.cpu0.kern.syscall::71 25 12.38% 86.63% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.49% 88.12% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.97% 91.09% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.50% 91.58% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.99% 92.57% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.47% 96.04% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.99% 97.03% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.99% 98.02% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 202 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3514 2.08% 2.25% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.27% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed -system.cpu0.kern.callpal::swpipl 153834 90.90% 93.18% # number of callpals executed -system.cpu0.kern.callpal::rdps 6534 3.86% 97.04% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.04% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.04% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.05% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.05% # number of callpals executed -system.cpu0.kern.callpal::rti 4517 2.67% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 345 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 169239 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7061 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1286 # number of protection mode switches +system.cpu0.kern.callpal::wripir 108 0.07% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2969 1.98% 2.05% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed +system.cpu0.kern.callpal::swpipl 135909 90.65% 92.74% # number of callpals executed +system.cpu0.kern.callpal::rdps 6127 4.09% 96.83% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.83% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.83% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.01% 96.83% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.84% # number of callpals executed +system.cpu0.kern.callpal::rti 4274 2.85% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 333 0.22% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 149930 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6311 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1285 -system.cpu0.kern.mode_good::user 1286 +system.cpu0.kern.mode_good::kernel 1257 +system.cpu0.kern.mode_good::user 1258 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.181986 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.199176 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.308015 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1900726417500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2011717000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.332276 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1902741106000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1923139500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3515 # number of times the context was actually changed +system.cpu0.kern.swap_context 2970 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2440 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 55424 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 17233 36.50% 36.50% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1922 4.07% 40.57% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 284 0.60% 41.17% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 27775 58.83% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 47214 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16850 47.30% 47.30% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1922 5.40% 52.70% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 284 0.80% 53.50% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 16566 46.50% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 35622 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871948155000 98.40% 98.40% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 531300500 0.03% 98.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 128640500 0.01% 98.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29802235500 1.57% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1902410331500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.977775 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3864 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 73072 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 25114 39.08% 39.08% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 2.99% 42.08% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 108 0.17% 42.25% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 37111 57.75% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 64257 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 24684 48.12% 48.12% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 3.75% 51.88% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 108 0.21% 52.09% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 24576 47.91% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 51292 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870089135500 98.20% 98.20% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533638000 0.03% 98.23% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 50840000 0.00% 98.23% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 33685568500 1.77% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1904359182000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.982878 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.596436 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.754480 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed -system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed -system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed -system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed -system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 115 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.662230 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.798232 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed +system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed +system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed +system.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.42% 37.10% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.23% 40.32% # number of syscalls executed +system.cpu1.kern.syscall::45 20 16.13% 56.45% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.42% 58.87% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.61% 60.48% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.81% 61.29% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.61% 62.90% # number of syscalls executed +system.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed +system.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 124 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 193 0.40% 0.40% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.40% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.40% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1095 2.25% 2.65% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.66% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.67% # number of callpals executed -system.cpu1.kern.callpal::swpipl 41959 86.06% 88.73% # number of callpals executed -system.cpu1.kern.callpal::rdps 2221 4.56% 93.29% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.29% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 93.30% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.30% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.31% # number of callpals executed -system.cpu1.kern.callpal::rti 3048 6.25% 99.56% # number of callpals executed -system.cpu1.kern.callpal::callsys 172 0.35% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1277 1.92% 1.95% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 1.96% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 1.97% # number of callpals executed +system.cpu1.kern.callpal::swpipl 59282 89.28% 91.25% # number of callpals executed +system.cpu1.kern.callpal::rdps 2633 3.97% 95.21% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 95.21% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 95.22% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 95.22% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 95.23% # number of callpals executed +system.cpu1.kern.callpal::rti 2942 4.43% 99.66% # number of callpals executed +system.cpu1.kern.callpal::callsys 184 0.28% 99.93% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 48756 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1363 # number of protection mode switches -system.cpu1.kern.mode_switch::user 459 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2408 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 668 -system.cpu1.kern.mode_good::user 459 -system.cpu1.kern.mode_good::idle 209 -system.cpu1.kern.mode_switch_good::kernel 0.490095 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 66403 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1747 # number of protection mode switches +system.cpu1.kern.mode_switch::user 488 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2062 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 557 +system.cpu1.kern.mode_good::user 488 +system.cpu1.kern.mode_good::idle 69 +system.cpu1.kern.mode_switch_good::kernel 0.318832 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.086794 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.315839 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4405402000 0.23% 0.23% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 814709500 0.04% 0.27% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1897179577000 99.73% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1096 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.033463 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.259251 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 38709369000 2.03% 2.03% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 835914500 0.04% 2.08% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1864803541000 97.92% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1278 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 56fb70faf..cb131fc03 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,125 +1,127 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860201 # Number of seconds simulated -sim_ticks 1860200687500 # Number of ticks simulated -final_tick 1860200687500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.860198 # Number of seconds simulated +sim_ticks 1860197608000 # Number of ticks simulated +final_tick 1860197608000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133673 # Simulator instruction rate (inst/s) -host_op_rate 133673 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4693486883 # Simulator tick rate (ticks/s) -host_mem_usage 310052 # Number of bytes of host memory used -host_seconds 396.34 # Real time elapsed on the host -sim_insts 52979577 # Number of instructions simulated -sim_ops 52979577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879296 # Number of bytes read from this memory +host_inst_rate 128608 # Simulator instruction rate (inst/s) +host_op_rate 128608 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4515644283 # Simulator tick rate (ticks/s) +host_mem_usage 336512 # Number of bytes of host memory used +host_seconds 411.95 # Real time elapsed on the host +sim_insts 52979573 # Number of instructions simulated +sim_ops 52979573 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 964544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879808 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28495552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7515968 # Number of bytes written to this memory -system.physmem.bytes_written::total 7515968 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388739 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28496640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 964544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7516672 # Number of bytes written to this memory +system.physmem.bytes_written::total 7516672 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15071 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388747 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445243 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117437 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117437 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13374523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1425807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15318536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4040407 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4040407 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4040407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13374523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1425807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19358943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445243 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 117437 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 445243 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 117437 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28495552 # Total number of bytes read from memory -system.physmem.bytesWritten 7515968 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28495552 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7515968 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28218 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28424 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28004 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27230 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27265 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27330 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27264 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28015 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27528 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27551 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28325 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28321 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7923 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7495 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7940 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7495 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7349 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6687 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6775 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6715 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7135 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6683 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7403 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6968 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7888 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8047 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7823 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 1860195209000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445243 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 117437 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 330882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19901 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3039 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1564 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1464 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see +system.physmem.num_reads::total 445260 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117448 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117448 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13374820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1425810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15319147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518517 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518517 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4040792 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4040792 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4040792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13374820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1425810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19359939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445260 # Number of read requests accepted +system.physmem.writeReqs 117448 # Number of write requests accepted +system.physmem.readBursts 445260 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117448 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28493888 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2752 # Total number of bytes read from write queue +system.physmem.bytesWritten 7515904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28496640 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7516672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 177 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28229 # Per bank write bursts +system.physmem.perBankRdBursts::1 27970 # Per bank write bursts +system.physmem.perBankRdBursts::2 28438 # Per bank write bursts +system.physmem.perBankRdBursts::3 28034 # Per bank write bursts +system.physmem.perBankRdBursts::4 27800 # Per bank write bursts +system.physmem.perBankRdBursts::5 27233 # Per bank write bursts +system.physmem.perBankRdBursts::6 27248 # Per bank write bursts +system.physmem.perBankRdBursts::7 27300 # Per bank write bursts +system.physmem.perBankRdBursts::8 27656 # Per bank write bursts +system.physmem.perBankRdBursts::9 27404 # Per bank write bursts +system.physmem.perBankRdBursts::10 27929 # Per bank write bursts +system.physmem.perBankRdBursts::11 27540 # Per bank write bursts +system.physmem.perBankRdBursts::12 27555 # Per bank write bursts +system.physmem.perBankRdBursts::13 28228 # Per bank write bursts +system.physmem.perBankRdBursts::14 28334 # Per bank write bursts +system.physmem.perBankRdBursts::15 28319 # Per bank write bursts +system.physmem.perBankWrBursts::0 7929 # Per bank write bursts +system.physmem.perBankWrBursts::1 7498 # Per bank write bursts +system.physmem.perBankWrBursts::2 7947 # Per bank write bursts +system.physmem.perBankWrBursts::3 7517 # Per bank write bursts +system.physmem.perBankWrBursts::4 7338 # Per bank write bursts +system.physmem.perBankWrBursts::5 6689 # Per bank write bursts +system.physmem.perBankWrBursts::6 6763 # Per bank write bursts +system.physmem.perBankWrBursts::7 6689 # Per bank write bursts +system.physmem.perBankWrBursts::8 7098 # Per bank write bursts +system.physmem.perBankWrBursts::9 6803 # Per bank write bursts +system.physmem.perBankWrBursts::10 7320 # Per bank write bursts +system.physmem.perBankWrBursts::11 6984 # Per bank write bursts +system.physmem.perBankWrBursts::12 7119 # Per bank write bursts +system.physmem.perBankWrBursts::13 7873 # Per bank write bursts +system.physmem.perBankWrBursts::14 8054 # Per bank write bursts +system.physmem.perBankWrBursts::15 7815 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 1860192151000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 445260 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 117448 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 332300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1086 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -129,242 +131,288 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37668 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 955.810131 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 232.523406 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2430.690638 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 13031 34.59% 34.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5648 14.99% 49.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3558 9.45% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2240 5.95% 64.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1644 4.36% 69.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1436 3.81% 73.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 989 2.63% 75.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 804 2.13% 77.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 676 1.79% 79.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 516 1.37% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 573 1.52% 82.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 541 1.44% 84.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 276 0.73% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 231 0.61% 85.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 160 0.42% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 263 0.70% 86.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 87 0.23% 86.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 129 0.34% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 75 0.20% 87.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 153 0.41% 87.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 242 0.64% 88.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 113 0.30% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 462 1.23% 89.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 590 1.57% 91.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 81 0.22% 91.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 28 0.07% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 16 0.04% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 89 0.24% 91.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 26 0.07% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 8 0.02% 92.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 14 0.04% 92.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 43 0.11% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 28 0.07% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 4 0.01% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 1 0.00% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 18 0.05% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 7 0.02% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 5 0.01% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 5 0.01% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 3 0.01% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 3 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 3 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 6 0.02% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.01% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 2 0.01% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 2 0.01% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 2 0.01% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 2 0.01% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 2 0.01% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 1 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 2 0.01% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 3 0.01% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 1 0.00% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 1 0.00% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 2 0.01% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 1 0.00% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 1 0.00% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 4 0.01% 92.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 92.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 3 0.01% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 2 0.01% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 2 0.01% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.01% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 5 0.01% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2432 6.46% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 3 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 2 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 13 0.03% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 240 0.64% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 5 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 4 0.01% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 5 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 5 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37668 # Bytes accessed per row activation -system.physmem.totQLat 6113897250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13475242250 # Sum of mem lat for all requests -system.physmem.totBusLat 2225940000 # Total cycles spent in databus access -system.physmem.totBankLat 5135405000 # Total cycles spent in bank access -system.physmem.avgQLat 13733.29 # Average queueing delay per request -system.physmem.avgBankLat 11535.36 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30268.66 # Average memory access latency -system.physmem.avgRdBW 15.32 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.32 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.04 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 43193 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 833.653601 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 238.014185 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1939.409877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 14703 34.04% 34.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6277 14.53% 48.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4438 10.27% 58.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2692 6.23% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1642 3.80% 68.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1371 3.17% 72.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 939 2.17% 74.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 792 1.83% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 658 1.52% 77.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 515 1.19% 78.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 623 1.44% 80.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 600 1.39% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 275 0.64% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 275 0.64% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 263 0.61% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 360 0.83% 84.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 192 0.44% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 168 0.39% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 100 0.23% 85.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 208 0.48% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 111 0.26% 86.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 353 0.82% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 185 0.43% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 668 1.55% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 85 0.20% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 28 0.06% 89.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 47 0.11% 89.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 186 0.43% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 41 0.09% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 74 0.17% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 86 0.20% 90.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 80 0.19% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 97 0.22% 90.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 73 0.17% 90.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 19 0.04% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 108 0.25% 91.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 28 0.06% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 15 0.03% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 1 0.00% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 16 0.04% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 2 0.00% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 13 0.03% 91.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 24 0.06% 91.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 101 0.23% 91.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 13 0.03% 91.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 66 0.15% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 82 0.19% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 39 0.09% 91.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 82 0.19% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 66 0.15% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 13 0.03% 92.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 95 0.22% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 22 0.05% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 10 0.02% 92.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 4 0.01% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 12 0.03% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 3 0.01% 92.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 11 0.03% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 24 0.06% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 91 0.21% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 11 0.03% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 66 0.15% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 81 0.19% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 39 0.09% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 79 0.18% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 68 0.16% 93.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 12 0.03% 93.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 94 0.22% 94.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 22 0.05% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 12 0.03% 94.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 4 0.01% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 11 0.03% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 4 0.01% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 12 0.03% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 21 0.05% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 92 0.21% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 13 0.03% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 67 0.16% 94.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 81 0.19% 94.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 35 0.08% 94.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 79 0.18% 95.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 68 0.16% 95.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 12 0.03% 95.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 99 0.23% 95.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 22 0.05% 95.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 11 0.03% 95.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 1 0.00% 95.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 12 0.03% 95.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 11 0.03% 95.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 21 0.05% 95.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 92 0.21% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 14 0.03% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 64 0.15% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 83 0.19% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 39 0.09% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 81 0.19% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 67 0.16% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 13 0.03% 96.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 94 0.22% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 21 0.05% 96.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 8 0.02% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.00% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 12 0.03% 97.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 3 0.01% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 10 0.02% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 24 0.06% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 89 0.21% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 13 0.03% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 66 0.15% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 81 0.19% 97.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 309 0.72% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 2 0.00% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 16 0.04% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 4 0.01% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 3 0.01% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 18 0.04% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 3 0.01% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 331 0.77% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 2 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 5 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 2 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9411 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 2 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 3 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11907 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 37 0.09% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 176 0.41% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 43193 # Bytes accessed per row activation +system.physmem.totQLat 8380902250 # Total ticks spent queuing +system.physmem.totMemAccLat 15783312250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2226085000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5176325000 # Total ticks spent accessing banks +system.physmem.avgQLat 18824.31 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11626.52 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 35450.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 9.67 # Average write queue length over time -system.physmem.readRowHits 430049 # Number of row buffer hits during reads -system.physmem.writeRowHits 94886 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes -system.physmem.avgGap 3305955.80 # Average gap between requests -system.membus.throughput 19401806 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295958 # Transaction distribution -system.membus.trans_dist::ReadResp 295878 # Transaction distribution +system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.37 # Average write queue length when enqueuing +system.physmem.readRowHits 424661 # Number of row buffer hits during reads +system.physmem.writeRowHits 94799 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.72 # Row buffer hit rate for writes +system.physmem.avgGap 3305785.86 # Average gap between requests +system.physmem.pageHitRate 92.32 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.40 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 19402801 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 295960 # Transaction distribution +system.membus.trans_dist::ReadResp 295877 # Transaction distribution system.membus.trans_dist::WriteReq 9598 # Transaction distribution system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::Writeback 117437 # Transaction distribution -system.membus.trans_dist::UpgradeReq 178 # Transaction distribution -system.membus.trans_dist::UpgradeResp 178 # Transaction distribution -system.membus.trans_dist::ReadExReq 156851 # Transaction distribution -system.membus.trans_dist::ReadExResp 156851 # Transaction distribution -system.membus.trans_dist::BadAddressError 80 # Transaction distribution +system.membus.trans_dist::Writeback 117448 # Transaction distribution +system.membus.trans_dist::UpgradeReq 180 # Transaction distribution +system.membus.trans_dist::UpgradeResp 180 # Transaction distribution +system.membus.trans_dist::ReadExReq 156869 # Transaction distribution +system.membus.trans_dist::ReadExResp 156869 # Transaction distribution +system.membus.trans_dist::BadAddressError 83 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884153 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917369 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884202 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917424 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042048 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042103 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702464 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30746612 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704256 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30748404 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36055668 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36055668 # Total data (bytes) +system.membus.tot_pkt_size::total 36057460 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36057460 # Total data (bytes) system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29849000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 29954500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1552225748 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1551414500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 97500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 106000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3765192546 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3763341794 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376215241 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376305243 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.261083 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.261102 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710344305000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.261083 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078818 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078818 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710341438000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.261102 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078819 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078819 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -373,14 +421,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21345883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21345883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10482445518 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10482445518 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10503791401 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10503791401 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10503791401 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10503791401 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21133883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21133883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12983817806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12983817806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13004951689 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13004951689 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13004951689 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13004951689 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -397,19 +445,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123386.606936 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123386.606936 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 252272.947584 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 252272.947584 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 251738.559641 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 251738.559641 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 251738.559641 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 251738.559641 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 274094 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122161.173410 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312471.549047 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 312471.549047 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 311682.485057 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 311682.485057 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 311682.485057 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 311682.485057 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 402476 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27191 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29170 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.080321 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.797600 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -423,14 +471,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12348383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12348383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8320362536 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8320362536 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8332710919 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8332710919 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8332710919 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8332710919 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12136883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10821554320 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10821554320 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10833691203 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10833691203 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10833691203 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10833691203 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -439,14 +487,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71377.936416 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71377.936416 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 200239.760685 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 200239.760685 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199705.474392 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 199705.474392 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199705.474392 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 199705.474392 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260434.018098 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 260434.018098 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259645.085752 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 259645.085752 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259645.085752 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 259645.085752 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -460,35 +508,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13856452 # Number of BP lookups -system.cpu.branchPred.condPredicted 11625252 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 398822 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9666189 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5826807 # Number of BTB hits +system.cpu.branchPred.lookups 13864479 # Number of BP lookups +system.cpu.branchPred.condPredicted 11634507 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 398117 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9551974 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5822395 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 60.280292 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 904750 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39047 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 60.954887 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 906213 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 38605 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9922890 # DTB read hits -system.cpu.dtb.read_misses 41426 # DTB read misses -system.cpu.dtb.read_acv 537 # DTB read access violations -system.cpu.dtb.read_accesses 941977 # DTB read accesses -system.cpu.dtb.write_hits 6601888 # DTB write hits -system.cpu.dtb.write_misses 10414 # DTB write misses -system.cpu.dtb.write_acv 409 # DTB write access violations -system.cpu.dtb.write_accesses 338180 # DTB write accesses -system.cpu.dtb.data_hits 16524778 # DTB hits -system.cpu.dtb.data_misses 51840 # DTB misses -system.cpu.dtb.data_acv 946 # DTB access violations -system.cpu.dtb.data_accesses 1280157 # DTB accesses -system.cpu.itb.fetch_hits 1306702 # ITB hits -system.cpu.itb.fetch_misses 37996 # ITB misses -system.cpu.itb.fetch_acv 1078 # ITB acv -system.cpu.itb.fetch_accesses 1344698 # ITB accesses +system.cpu.dtb.read_hits 9930859 # DTB read hits +system.cpu.dtb.read_misses 42001 # DTB read misses +system.cpu.dtb.read_acv 541 # DTB read access violations +system.cpu.dtb.read_accesses 942214 # DTB read accesses +system.cpu.dtb.write_hits 6592411 # DTB write hits +system.cpu.dtb.write_misses 10345 # DTB write misses +system.cpu.dtb.write_acv 410 # DTB write access violations +system.cpu.dtb.write_accesses 337923 # DTB write accesses +system.cpu.dtb.data_hits 16523270 # DTB hits +system.cpu.dtb.data_misses 52346 # DTB misses +system.cpu.dtb.data_acv 951 # DTB access violations +system.cpu.dtb.data_accesses 1280137 # DTB accesses +system.cpu.itb.fetch_hits 1308071 # ITB hits +system.cpu.itb.fetch_misses 36703 # ITB misses +system.cpu.itb.fetch_acv 1058 # ITB acv +system.cpu.itb.fetch_accesses 1344774 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -501,134 +549,134 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 120724090 # number of cpu cycles simulated +system.cpu.numCycles 121927488 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28054756 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70765698 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13856452 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6731557 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13261846 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1996538 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 38180961 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33921 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 253688 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 362223 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8553305 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 264520 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81438491 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.868947 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.211995 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28039089 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70847333 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13864479 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6728608 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13268188 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1998523 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38187764 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33374 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 253703 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 358378 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 313 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8556240 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 264321 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81433386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.870004 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.213508 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68176645 83.72% 83.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 854498 1.05% 84.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1700203 2.09% 86.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 823613 1.01% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2757448 3.39% 91.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 566024 0.70% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 644448 0.79% 92.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1011541 1.24% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4904071 6.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68165198 83.71% 83.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 850053 1.04% 84.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1699284 2.09% 86.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 821371 1.01% 87.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2763942 3.39% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 562061 0.69% 91.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 645266 0.79% 92.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1012758 1.24% 93.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4913453 6.03% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81438491 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.114778 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.586177 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29237679 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37865551 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12126902 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 959687 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1248671 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 585551 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42601 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69445978 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129475 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1248671 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30384491 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14146796 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20012830 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11334710 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4310991 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65667162 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7173 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 505660 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1537414 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43855524 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79710296 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79531258 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 166586 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38179970 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5675546 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682539 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240064 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12233478 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10440283 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6900737 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1318689 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 855517 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58206235 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2050936 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56823082 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 100209 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6920159 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3549975 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1389936 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81438491 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697742 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.359996 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81433386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.113711 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.581061 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29221081 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37872240 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12130703 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 959021 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1250340 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 583021 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69509272 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129850 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1250340 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30372674 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14147971 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20014852 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11335195 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4312352 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65701425 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7084 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 503729 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1544223 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43873094 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79768312 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79589398 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 166462 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38180112 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5692974 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682864 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240315 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12255388 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10448429 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6906827 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1318660 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 851527 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58223534 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2050984 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56812947 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113805 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6931173 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3605221 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1390018 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81433386 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.697662 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.359692 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56732960 69.66% 69.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10881055 13.36% 83.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5157432 6.33% 89.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3394617 4.17% 93.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2629816 3.23% 96.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1458992 1.79% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 753848 0.93% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 332168 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 97603 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56726750 69.66% 69.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10882649 13.36% 83.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5163201 6.34% 89.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3388782 4.16% 93.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2628492 3.23% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1462722 1.80% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 751690 0.92% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 332968 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96132 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81438491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81433386 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91824 11.60% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 372747 47.08% 58.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 327090 41.32% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91250 11.56% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 372174 47.14% 58.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326051 41.30% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38740473 68.18% 68.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61726 0.11% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38733166 68.18% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61715 0.11% 68.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued @@ -656,114 +704,114 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10354642 18.22% 86.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6680643 11.76% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949069 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10362094 18.24% 86.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6670366 11.74% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56823082 # Type of FU issued -system.cpu.iq.rate 0.470686 # Inst issue rate -system.cpu.iq.fu_busy_cnt 791661 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013932 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195283781 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66854445 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55585028 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692743 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336682 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327940 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57245966 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361491 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 598566 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56812947 # Type of FU issued +system.cpu.iq.rate 0.465957 # Inst issue rate +system.cpu.iq.fu_busy_cnt 789475 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013896 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195270080 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66882864 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55570085 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692479 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336490 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327821 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57233809 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361327 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 596971 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1347977 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3312 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14180 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 522824 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1356016 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3236 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14012 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 528856 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17906 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 181081 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17919 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 183461 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1248671 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10233873 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 701956 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63782733 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 684936 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10440283 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6900737 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1806230 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512408 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17686 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14180 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 202063 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 410564 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 612627 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56356224 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9992501 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 466857 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1250340 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10233655 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 702274 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63801966 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 688802 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10448429 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6906827 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1805093 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512952 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17454 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14012 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 201109 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411560 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 612669 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56346471 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10001011 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 466475 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3525562 # number of nop insts executed -system.cpu.iew.exec_refs 16620030 # number of memory reference insts executed -system.cpu.iew.exec_branches 8925380 # Number of branches executed -system.cpu.iew.exec_stores 6627529 # Number of stores executed -system.cpu.iew.exec_rate 0.466818 # Inst execution rate -system.cpu.iew.wb_sent 56027730 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55912968 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27713014 # num instructions producing a value -system.cpu.iew.wb_consumers 37524402 # num instructions consuming a value +system.cpu.iew.exec_nop 3527448 # number of nop insts executed +system.cpu.iew.exec_refs 16619020 # number of memory reference insts executed +system.cpu.iew.exec_branches 8923746 # Number of branches executed +system.cpu.iew.exec_stores 6618009 # Number of stores executed +system.cpu.iew.exec_rate 0.462131 # Inst execution rate +system.cpu.iew.wb_sent 56013491 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55897906 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27708487 # num instructions producing a value +system.cpu.iew.wb_consumers 37528450 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.463147 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738533 # average fanout of values written-back +system.cpu.iew.wb_rate 0.458452 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738333 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7495675 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661000 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 567647 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80189820 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.700468 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.629642 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7515002 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660966 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 566897 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80183046 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.700527 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.629598 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59377156 74.05% 74.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8657171 10.80% 84.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4615541 5.76% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2519398 3.14% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1507686 1.88% 95.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 611065 0.76% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 523948 0.65% 97.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 528681 0.66% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1849174 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59370328 74.04% 74.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8654728 10.79% 84.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4617014 5.76% 90.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2519187 3.14% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1509953 1.88% 95.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 613300 0.76% 96.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 523538 0.65% 97.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 523484 0.65% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1851514 2.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80189820 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56170363 # Number of instructions committed -system.cpu.commit.committedOps 56170363 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 80183046 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56170357 # Number of instructions committed +system.cpu.commit.committedOps 56170357 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470219 # Number of memory references committed -system.cpu.commit.loads 9092306 # Number of loads committed -system.cpu.commit.membars 226376 # Number of memory barriers committed -system.cpu.commit.branches 8439998 # Number of branches committed +system.cpu.commit.refs 15470384 # Number of memory references committed +system.cpu.commit.loads 9092413 # Number of loads committed +system.cpu.commit.membars 226354 # Number of memory barriers committed +system.cpu.commit.branches 8439829 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52019946 # Number of committed integer instructions. -system.cpu.commit.function_calls 740578 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1849174 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52019973 # Number of committed integer instructions. +system.cpu.commit.function_calls 740579 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1851514 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141757103 # The number of ROB reads -system.cpu.rob.rob_writes 128582546 # The number of ROB writes -system.cpu.timesIdled 1193264 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 39285599 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599670846 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52979577 # Number of Instructions Simulated -system.cpu.committedOps 52979577 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52979577 # Number of Instructions Simulated -system.cpu.cpi 2.278691 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.278691 # CPI: Total CPI of All Threads -system.cpu.ipc 0.438848 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.438848 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73899188 # number of integer regfile reads -system.cpu.int_regfile_writes 40322867 # number of integer regfile writes -system.cpu.fp_regfile_reads 166085 # number of floating regfile reads +system.cpu.rob.rob_reads 141767299 # The number of ROB reads +system.cpu.rob.rob_writes 128622610 # The number of ROB writes +system.cpu.timesIdled 1192878 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 40494102 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598461292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52979573 # Number of Instructions Simulated +system.cpu.committedOps 52979573 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52979573 # Number of Instructions Simulated +system.cpu.cpi 2.301406 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.301406 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434517 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434517 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73879526 # number of integer regfile reads +system.cpu.int_regfile_writes 40317649 # number of integer regfile writes +system.cpu.fp_regfile_reads 165968 # number of floating regfile reads system.cpu.fp_regfile_writes 167427 # number of floating regfile writes -system.cpu.misc_regfile_reads 1985758 # number of misc regfile reads -system.cpu.misc_regfile_writes 938984 # number of misc regfile writes +system.cpu.misc_regfile_reads 1984782 # number of misc regfile reads +system.cpu.misc_regfile_writes 938976 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -795,7 +843,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1454551 # Throughput (bytes/s) +system.iobus.throughput 1454553 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51150 # Transaction distribution @@ -855,225 +903,225 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378268160 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377740446 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43098759 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42670757 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 111927083 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2117675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2117578 # Transaction distribution +system.cpu.toL2Bus.throughput 111891693 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2116597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2116497 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 840831 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 840887 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 63 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 342614 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301063 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2019865 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5697325 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64631872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143567348 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 208199220 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 208189172 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 17664 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2480161498 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 342605 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301054 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 83 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2016984 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3678218 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5695202 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64539584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143593268 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 208132852 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 208122804 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 17856 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2479701498 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1518735644 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1516139861 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194600669 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2192873665 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1009263 # number of replacements -system.cpu.icache.tags.tagsinuse 509.727374 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7487430 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1009771 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.414978 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 25799742250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.727374 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995561 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995561 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7487431 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7487431 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7487431 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7487431 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7487431 # number of overall hits -system.cpu.icache.overall_hits::total 7487431 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1065872 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065872 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1065872 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065872 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1065872 # number of overall misses -system.cpu.icache.overall_misses::total 1065872 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14976021459 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14976021459 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14976021459 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14976021459 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14976021459 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14976021459 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8553303 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8553303 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8553303 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8553303 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8553303 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8553303 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124615 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124615 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124615 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124615 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124615 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124615 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14050.487731 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14050.487731 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14050.487731 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14050.487731 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14050.487731 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14050.487731 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8372 # number of cycles access was blocked +system.cpu.icache.tags.replacements 1007825 # number of replacements +system.cpu.icache.tags.tagsinuse 509.660233 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7491263 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1008333 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.429354 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26489829250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.660233 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995430 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995430 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7491264 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7491264 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7491264 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7491264 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7491264 # number of overall hits +system.cpu.icache.overall_hits::total 7491264 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1064974 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1064974 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1064974 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1064974 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1064974 # number of overall misses +system.cpu.icache.overall_misses::total 1064974 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14872208186 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14872208186 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14872208186 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14872208186 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14872208186 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14872208186 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8556238 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8556238 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8556238 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8556238 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8556238 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8556238 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124468 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124468 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124468 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124468 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124468 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124468 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13964.855655 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13964.855655 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13964.855655 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13964.855655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13964.855655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13964.855655 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5226 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 186 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 214 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 45.010753 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 24.420561 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55880 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 55880 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 55880 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 55880 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 55880 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 55880 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009992 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1009992 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1009992 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1009992 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1009992 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1009992 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12273344851 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12273344851 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12273344851 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12273344851 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12273344851 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12273344851 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118082 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.118082 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.118082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12151.922838 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12151.922838 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12151.922838 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12151.922838 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12151.922838 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12151.922838 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56421 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 56421 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 56421 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 56421 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 56421 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 56421 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1008553 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1008553 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1008553 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1008553 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1008553 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1008553 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12184986133 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12184986133 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12184986133 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12184986133 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12184986133 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12184986133 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117873 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117873 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117873 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.117873 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117873 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.117873 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12081.651765 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12081.651765 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12081.651765 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12081.651765 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12081.651765 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12081.651765 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338298 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65343.107599 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2545731 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403463 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.309701 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5353022750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53859.326644 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5308.706799 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6175.074156 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.821828 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081004 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.094224 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997057 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 994809 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 826788 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1821597 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 840831 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 840831 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.cpu.l2cache.tags.replacements 338320 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65339.826573 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2544675 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 403486 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.306724 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 5511908750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 53856.157750 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5301.221918 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6182.446905 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.821780 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080890 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.094337 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 993358 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 827156 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1820514 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 840887 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 840887 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 24 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 24 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185623 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185623 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 994809 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1012411 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2007220 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 994809 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1012411 # number of overall hits -system.cpu.l2cache.overall_hits::total 2007220 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15064 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273792 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 288856 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 38 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 38 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115439 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115439 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15064 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389231 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404295 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15064 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389231 # number of overall misses -system.cpu.l2cache.overall_misses::total 404295 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1289741743 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17221594730 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18511336473 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 285497 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 285497 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9397410357 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9397410357 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1289741743 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 26619005087 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27908746830 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1289741743 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 26619005087 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27908746830 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009873 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1100580 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2110453 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 840831 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 840831 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 64 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 64 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 185595 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 185595 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 993358 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1012751 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2006109 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 993358 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1012751 # number of overall hits +system.cpu.l2cache.overall_hits::total 2006109 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 15073 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 273785 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 288858 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 39 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 39 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 115458 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115458 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15073 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389243 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404316 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15073 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389243 # number of overall misses +system.cpu.l2cache.overall_misses::total 404316 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1217060992 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17822778727 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19039839719 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 308496 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 308496 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9541842859 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9541842859 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1217060992 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 27364621586 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28581682578 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1217060992 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 27364621586 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28581682578 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1008431 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1100941 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2109372 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 840887 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 840887 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 63 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 63 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 301062 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 301062 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1009873 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1401642 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2411515 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1009873 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1401642 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2411515 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014917 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248771 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.136869 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.593750 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.593750 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383439 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383439 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014917 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277696 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.167652 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014917 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277696 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.167652 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 85617.481612 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62900.284632 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 64084.999006 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7513.078947 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7513.078947 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81405.853802 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81405.853802 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85617.481612 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68388.707701 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69030.650466 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85617.481612 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68388.707701 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69030.650466 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 301053 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 301053 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1008431 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1401994 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2410425 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1008431 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1401994 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2410425 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014947 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248683 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.136940 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.619048 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.619048 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383514 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383514 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014947 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277635 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.167736 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014947 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277635 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.167736 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80744.443177 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65097.718016 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 65914.185236 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7910.153846 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7910.153846 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82643.410236 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82643.410236 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80744.443177 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70302.154659 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70691.445745 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80744.443177 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70302.154659 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70691.445745 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1082,72 +1130,72 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75925 # number of writebacks -system.cpu.l2cache.writebacks::total 75925 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75936 # number of writebacks +system.cpu.l2cache.writebacks::total 75936 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15063 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273792 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288855 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 38 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115439 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115439 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15063 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389231 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404294 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15063 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389231 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404294 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1098682007 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13807789270 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14906471277 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 531034 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 531034 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7972002643 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7972002643 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1098682007 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21779791913 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22878473920 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1098682007 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21779791913 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22878473920 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333925000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333925000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882616000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882616000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216541000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216541000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014916 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248771 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136869 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.593750 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.593750 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383439 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383439 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014916 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277696 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.167651 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014916 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277696 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.167651 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 72939.122817 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50431.675396 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51605.377359 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13974.578947 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13974.578947 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69058.140169 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69058.140169 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72939.122817 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55955.953953 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56588.705051 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72939.122817 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55955.953953 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56588.705051 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15072 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273785 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288857 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 39 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 39 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115458 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115458 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15072 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389243 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404315 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15072 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389243 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404315 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1026861258 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14410483773 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15437345031 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 542534 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 542534 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8118910641 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8118910641 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1026861258 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22529394414 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23556255672 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1026861258 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22529394414 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23556255672 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334047500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334047500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882613000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882613000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216660500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216660500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248683 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136940 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.619048 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.619048 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277635 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167736 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277635 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167736 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68130.391322 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52634.307113 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53442.862839 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13911.128205 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13911.128205 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70319.169230 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70319.169230 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68130.391322 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57880.024596 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58262.136384 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68130.391322 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57880.024596 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58262.136384 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1155,161 +1203,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1401048 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994535 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11808107 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1401560 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.424974 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25348250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994535 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1401398 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994568 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11815525 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1401910 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.428162 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25477000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994568 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7202464 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7202464 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4203713 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4203713 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186169 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186169 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215520 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215520 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11406177 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11406177 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11406177 # number of overall hits -system.cpu.dcache.overall_hits::total 11406177 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1806828 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1806828 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1943975 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1943975 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22707 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22707 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 7210216 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7210216 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203313 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203313 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186240 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186240 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215515 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215515 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11413529 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11413529 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11413529 # number of overall hits +system.cpu.dcache.overall_hits::total 11413529 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1806580 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1806580 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1944438 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1944438 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22731 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22731 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3750803 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3750803 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3750803 # number of overall misses -system.cpu.dcache.overall_misses::total 3750803 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39803546178 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39803546178 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 76325479834 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 76325479834 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321955499 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 321955499 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3751018 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3751018 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3751018 # number of overall misses +system.cpu.dcache.overall_misses::total 3751018 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40329752439 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40329752439 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 77181819403 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77181819403 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321716499 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 321716499 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 116129026012 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 116129026012 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 116129026012 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 116129026012 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9009292 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9009292 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147688 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147688 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208876 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 208876 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215522 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215522 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15156980 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15156980 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15156980 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15156980 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200552 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.200552 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316212 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316212 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108710 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108710 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 117511571842 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117511571842 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117511571842 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117511571842 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9016796 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9016796 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208971 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 208971 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215517 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215517 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15164547 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15164547 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15164547 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15164547 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200357 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200357 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316284 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316284 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108776 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247464 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247464 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247464 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247464 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22029.515913 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22029.515913 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39262.583024 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39262.583024 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14178.689347 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14178.689347 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.247354 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247354 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247354 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247354 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22323.812086 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22323.812086 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39693.638678 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39693.638678 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14153.204830 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14153.204830 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30961.110464 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30961.110464 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30961.110464 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30961.110464 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2958985 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31327.914673 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31327.914673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31327.914673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31327.914673 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3032993 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 97398 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 98350 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.380347 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.838770 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840831 # number of writebacks -system.cpu.dcache.writebacks::total 840831 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 723109 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 723109 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643505 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1643505 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5191 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5191 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2366614 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2366614 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2366614 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2366614 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083719 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083719 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300470 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300470 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17516 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17516 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 840887 # number of writebacks +system.cpu.dcache.writebacks::total 840887 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722519 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 722519 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643978 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1643978 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5197 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5197 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2366497 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2366497 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2366497 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2366497 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084061 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1084061 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300460 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300460 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17534 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17534 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384189 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384189 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384189 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384189 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26582228002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26582228002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11613303338 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11613303338 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201814751 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201814751 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1384521 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384521 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384521 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384521 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27189046254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27189046254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11757002855 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11757002855 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200761751 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200761751 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38195531340 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 38195531340 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38195531340 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 38195531340 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424015000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424015000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997805998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997805998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421820998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421820998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120289 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120289 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048875 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048875 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083858 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083858 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38946049109 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 38946049109 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38946049109 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 38946049109 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424137500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424137500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997802998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997802998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421940498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421940498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120227 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120227 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048873 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048873 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083906 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091324 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091324 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091324 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24528.709012 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24528.709012 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38650.458741 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38650.458741 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11521.737326 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11521.737326 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091300 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091300 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091300 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091300 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25080.734621 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25080.734621 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39130.010168 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39130.010168 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11449.854625 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11449.854625 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27594.158991 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27594.158991 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27594.158991 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27594.158991 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28129.619637 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28129.619637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28129.619637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28129.619637 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1318,28 +1366,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 6437 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182247 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182248 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818706968000 97.77% 97.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64176500 0.00% 97.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 554827000 0.03% 97.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 40873882000 2.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860199853500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818037303500 97.73% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64303500 0.00% 97.74% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 561270000 0.03% 97.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41533903500 2.23% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860196780500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694268 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815393 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694294 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1378,8 +1426,8 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175130 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175131 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed @@ -1388,19 +1436,19 @@ system.cpu.kern.callpal::rti 5105 2.66% 99.64% # nu system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.callpal::total 191976 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326158 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326384 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29671097000 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2774842500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827753906000 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29638597000 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2732860000 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827825315500 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index f5971916a..739cb26e4 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,143 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842705 # Number of seconds simulated -sim_ticks 1842705252000 # Number of ticks simulated -final_tick 1842705252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842698 # Number of seconds simulated +sim_ticks 1842698476000 # Number of ticks simulated +final_tick 1842698476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260475 # Simulator instruction rate (inst/s) -host_op_rate 260475 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6607474809 # Simulator tick rate (ticks/s) -host_mem_usage 309028 # Number of bytes of host memory used -host_seconds 278.88 # Real time elapsed on the host -sim_insts 72641883 # Number of instructions simulated -sim_ops 72641883 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20049216 # Number of bytes read from this memory +host_inst_rate 222585 # Simulator instruction rate (inst/s) +host_op_rate 222585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5605413242 # Simulator tick rate (ticks/s) +host_mem_usage 334468 # Number of bytes of host memory used +host_seconds 328.74 # Real time elapsed on the host +sim_insts 73171582 # Number of instructions simulated +sim_ops 73171582 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 489344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20103680 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2290432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 282112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2525760 # Number of bytes read from this memory -system.physmem.bytes_read::total 28435648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 488448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 282112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 917888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7459584 # Number of bytes written to this memory -system.physmem.bytes_written::total 7459584 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7632 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 313269 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 144384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2235712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 284736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2526400 # Number of bytes read from this memory +system.physmem.bytes_read::total 28436608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 489344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 144384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 284736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 918464 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7460736 # Number of bytes written to this memory +system.physmem.bytes_written::total 7460736 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7646 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 314120 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2302 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 35788 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4408 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39465 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444307 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116556 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116556 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 265071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10880316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1439379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79952 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1242973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 153097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1370680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15431468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 265071 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79952 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 153097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498120 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4048170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4048170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4048170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 265071 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10880316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1439379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1242973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 153097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1370680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19479638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 99238 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 44800 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 99238 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 44800 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 6351232 # Total number of bytes read from memory -system.physmem.bytesWritten 2867200 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 6351232 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2867200 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 44 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6043 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6348 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 5767 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6398 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6152 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6059 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 6519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6372 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 6626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6008 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 5967 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6231 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6045 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2861 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2670 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2847 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2964 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 3000 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2942 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2703 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3213 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2742 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3001 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2449 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2468 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2705 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2852 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2761 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1841692926500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 99238 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 44800 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 67489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 84 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.num_reads::cpu1.inst 2256 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 34933 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39475 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444322 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116574 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116574 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 265558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10909913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1439385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 78355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1213282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 154521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1371033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15432046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 265558 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 78355 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 154521 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498434 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4048810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4048810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4048810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 265558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10909913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1439385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 78355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1213282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 154521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1371033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19480856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 98004 # Number of read requests accepted +system.physmem.writeReqs 44399 # Number of write requests accepted +system.physmem.readBursts 98004 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 44399 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6271808 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 2840768 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6272256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2841536 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 40 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6232 # Per bank write bursts +system.physmem.perBankRdBursts::1 6028 # Per bank write bursts +system.physmem.perBankRdBursts::2 6221 # Per bank write bursts +system.physmem.perBankRdBursts::3 6513 # Per bank write bursts +system.physmem.perBankRdBursts::4 5794 # Per bank write bursts +system.physmem.perBankRdBursts::5 6242 # Per bank write bursts +system.physmem.perBankRdBursts::6 5925 # Per bank write bursts +system.physmem.perBankRdBursts::7 6039 # Per bank write bursts +system.physmem.perBankRdBursts::8 6348 # Per bank write bursts +system.physmem.perBankRdBursts::9 6026 # Per bank write bursts +system.physmem.perBankRdBursts::10 6373 # Per bank write bursts +system.physmem.perBankRdBursts::11 5867 # Per bank write bursts +system.physmem.perBankRdBursts::12 5876 # Per bank write bursts +system.physmem.perBankRdBursts::13 6234 # Per bank write bursts +system.physmem.perBankRdBursts::14 6235 # Per bank write bursts +system.physmem.perBankRdBursts::15 6044 # Per bank write bursts +system.physmem.perBankWrBursts::0 2859 # Per bank write bursts +system.physmem.perBankWrBursts::1 2656 # Per bank write bursts +system.physmem.perBankWrBursts::2 2839 # Per bank write bursts +system.physmem.perBankWrBursts::3 3122 # Per bank write bursts +system.physmem.perBankWrBursts::4 2688 # Per bank write bursts +system.physmem.perBankWrBursts::5 2969 # Per bank write bursts +system.physmem.perBankWrBursts::6 2850 # Per bank write bursts +system.physmem.perBankWrBursts::7 2699 # Per bank write bursts +system.physmem.perBankWrBursts::8 3075 # Per bank write bursts +system.physmem.perBankWrBursts::9 2558 # Per bank write bursts +system.physmem.perBankWrBursts::10 2888 # Per bank write bursts +system.physmem.perBankWrBursts::11 2432 # Per bank write bursts +system.physmem.perBankWrBursts::12 2458 # Per bank write bursts +system.physmem.perBankWrBursts::13 2707 # Per bank write bursts +system.physmem.perBankWrBursts::14 2844 # Per bank write bursts +system.physmem.perBankWrBursts::15 2743 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 1841686150500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 98004 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 44399 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 66399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 14093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -149,362 +151,413 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 15760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 584.832487 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.909397 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1926.760563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 6603 41.90% 41.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 2572 16.32% 58.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 1454 9.23% 67.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 899 5.70% 73.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 642 4.07% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 535 3.39% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 370 2.35% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 312 1.98% 84.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 250 1.59% 86.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 195 1.24% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 235 1.49% 89.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 190 1.21% 90.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 101 0.64% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 71 0.45% 91.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 63 0.40% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 80 0.51% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 51 0.32% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 28 0.18% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 32 0.20% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 74 0.47% 93.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 51 0.32% 93.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 34 0.22% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 173 1.10% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 86 0.55% 95.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 27 0.17% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 14 0.09% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 12 0.08% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 22 0.14% 96.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 10 0.06% 96.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 4 0.03% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 2 0.01% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 6 0.04% 96.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 7 0.04% 96.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 1 0.01% 96.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 3 0.02% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 1 0.01% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 2 0.01% 96.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 1 0.01% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 2 0.01% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 1 0.01% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 1 0.01% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 2 0.01% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 3 0.02% 96.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 3 0.02% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 1 0.01% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 1 0.01% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 1 0.01% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 2 0.01% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.01% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.01% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.01% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.01% 96.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.01% 96.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.01% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 2 0.01% 96.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.01% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 1 0.01% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.01% 96.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.01% 96.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 383 2.43% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 1 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 1 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 2 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 6 0.04% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 1 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 111 0.70% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 1 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 2 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 3 0.02% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 1 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 15760 # Bytes accessed per row activation -system.physmem.totQLat 1910826000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 3572864750 # Sum of mem lat for all requests -system.physmem.totBusLat 496135000 # Total cycles spent in databus access -system.physmem.totBankLat 1165903750 # Total cycles spent in bank access -system.physmem.avgQLat 19257.12 # Average queueing delay per request -system.physmem.avgBankLat 11749.86 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 36006.98 # Average memory access latency -system.physmem.avgRdBW 3.45 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.45 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 1797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 2173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 2221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 2213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 17930 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 508.141439 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.008973 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1572.275953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 7528 41.99% 41.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 2973 16.58% 58.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 1838 10.25% 68.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 1006 5.61% 74.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 670 3.74% 78.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 572 3.19% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 359 2.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 327 1.82% 85.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 240 1.34% 86.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 222 1.24% 87.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 225 1.25% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 213 1.19% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 93 0.52% 90.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 79 0.44% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 78 0.44% 91.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 102 0.57% 92.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 45 0.25% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 56 0.31% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 39 0.22% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 53 0.30% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 30 0.17% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 119 0.66% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 70 0.39% 94.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 89 0.50% 94.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 16 0.09% 95.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 17 0.09% 95.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 5 0.03% 95.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 36 0.20% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 6 0.03% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 15 0.08% 95.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 5 0.03% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 15 0.08% 95.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 11 0.06% 95.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 11 0.06% 95.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 2 0.01% 95.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 23 0.13% 95.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 1 0.01% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 12 0.07% 95.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 2 0.01% 95.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 9 0.05% 96.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 15 0.08% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 1 0.01% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 22 0.12% 96.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 1 0.01% 96.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 14 0.08% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 4 0.02% 96.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 10 0.06% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 3 0.02% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 12 0.07% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 96.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 20 0.11% 96.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 13 0.07% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.01% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 7 0.04% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 13 0.07% 96.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 21 0.12% 96.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 13 0.07% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 2 0.01% 96.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 8 0.04% 97.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 2 0.01% 97.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 14 0.08% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 23 0.13% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 1 0.01% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 14 0.08% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 2 0.01% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 76 0.42% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 3 0.02% 97.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 19 0.11% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.01% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 4 0.02% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 1 0.01% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 9 0.05% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 5 0.03% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.01% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 21 0.12% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 8 0.04% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 8 0.04% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 3 0.02% 98.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 4 0.02% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 21 0.12% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 3 0.02% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 5 0.03% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 5 0.03% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 19 0.11% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 6 0.03% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.01% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 6 0.03% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 25 0.14% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 15 0.08% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 1 0.01% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 20 0.11% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 2 0.01% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 2 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 2 0.01% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 52 0.29% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 2 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 1 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9411 1 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 1 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10691 1 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 4 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 1 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 1 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 2 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 1 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 2 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 1 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 14 0.08% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 76 0.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 17930 # Bytes accessed per row activation +system.physmem.totQLat 2684942500 # Total ticks spent queuing +system.physmem.totMemAccLat 4336678750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 489985000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1161751250 # Total ticks spent accessing banks +system.physmem.avgQLat 27398.21 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11854.97 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 44253.18 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.40 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.17 # Average write queue length over time -system.physmem.readRowHits 92920 # Number of row buffer hits during reads -system.physmem.writeRowHits 35346 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.90 # Row buffer hit rate for writes -system.physmem.avgGap 12786160.09 # Average gap between requests -system.membus.throughput 19523578 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 45592 # Transaction distribution -system.membus.trans_dist::ReadResp 45560 # Transaction distribution -system.membus.trans_dist::WriteReq 3756 # Transaction distribution -system.membus.trans_dist::WriteResp 3756 # Transaction distribution -system.membus.trans_dist::Writeback 44800 # Transaction distribution -system.membus.trans_dist::UpgradeReq 46 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47 # Transaction distribution -system.membus.trans_dist::ReadExReq 56741 # Transaction distribution -system.membus.trans_dist::ReadExResp 56741 # Transaction distribution -system.membus.trans_dist::BadAddressError 32 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13322 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 191660 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 64 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 205046 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51865 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 51865 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 256911 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15754 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7009472 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 7025226 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2208960 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2208960 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 9234186 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35966088 # Total data (bytes) -system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12465000 # Layer occupancy (ticks) +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.18 # Average write queue length when enqueuing +system.physmem.readRowHits 89612 # Number of row buffer hits during reads +system.physmem.writeRowHits 34842 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.47 # Row buffer hit rate for writes +system.physmem.avgGap 12932916.80 # Average gap between requests +system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 19524796 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 44746 # Transaction distribution +system.membus.trans_dist::ReadResp 44539 # Transaction distribution +system.membus.trans_dist::WriteReq 3750 # Transaction distribution +system.membus.trans_dist::WriteResp 3750 # Transaction distribution +system.membus.trans_dist::Writeback 44399 # Transaction distribution +system.membus.trans_dist::UpgradeReq 43 # Transaction distribution +system.membus.trans_dist::UpgradeResp 43 # Transaction distribution +system.membus.trans_dist::ReadExReq 56527 # Transaction distribution +system.membus.trans_dist::ReadExResp 56527 # Transaction distribution +system.membus.trans_dist::BadAddressError 207 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 414 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 203660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 254372 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15690 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6953984 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 6969674 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 9129482 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35968328 # Total data (bytes) +system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 12460500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 516080000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 511769750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 39000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 256500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 771793954 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 762797456 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 156435750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 153003500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 337384 # number of replacements -system.l2c.tags.tagsinuse 65423.390976 # Cycle average of tags in use -system.l2c.tags.total_refs 2471195 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402547 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.138898 # Average number of references to valid blocks. +system.l2c.tags.replacements 337399 # number of replacements +system.l2c.tags.tagsinuse 65421.710089 # Cycle average of tags in use +system.l2c.tags.total_refs 2471820 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402562 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.140222 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54840.022307 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2455.785986 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2733.317890 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 573.564095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 593.217562 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2104.783507 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2122.699630 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.836792 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.037472 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041707 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008752 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009052 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032116 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.032390 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998282 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 518817 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 493229 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 124693 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 83730 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 293247 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 239325 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1753041 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835257 # number of Writeback hits -system.l2c.Writeback_hits::total 835257 # number of Writeback hits +system.l2c.tags.occ_blocks::writebacks 54901.425298 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2456.924718 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2698.289857 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 528.309889 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 619.621947 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2142.597203 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2074.541175 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.837729 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.037490 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041173 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009455 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.032693 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.031655 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998256 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 520374 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 492975 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 124091 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 84248 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 292559 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 239147 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1753394 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835552 # number of Writeback hits +system.l2c.Writeback_hits::total 835552 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 92556 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 26552 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67733 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186841 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 518817 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 585785 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 124693 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 110282 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 293247 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 307058 # number of demand (read+write) hits -system.l2c.demand_hits::total 1939882 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 518817 # number of overall hits -system.l2c.overall_hits::cpu0.data 585785 # number of overall hits -system.l2c.overall_hits::cpu1.inst 124693 # number of overall hits -system.l2c.overall_hits::cpu1.data 110282 # number of overall hits -system.l2c.overall_hits::cpu2.inst 293247 # number of overall hits -system.l2c.overall_hits::cpu2.data 307058 # number of overall hits -system.l2c.overall_hits::total 1939882 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 7632 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 237318 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2302 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 17365 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4408 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 18542 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287567 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu0.data 92855 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 26292 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 67775 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 186922 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 520374 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 585830 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 124091 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 110540 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 292559 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 306922 # number of demand (read+write) hits +system.l2c.demand_hits::total 1940316 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 520374 # number of overall hits +system.l2c.overall_hits::cpu0.data 585830 # number of overall hits +system.l2c.overall_hits::cpu1.inst 124091 # number of overall hits +system.l2c.overall_hits::cpu1.data 110540 # number of overall hits +system.l2c.overall_hits::cpu2.inst 292559 # number of overall hits +system.l2c.overall_hits::cpu2.data 306922 # number of overall hits +system.l2c.overall_hits::total 1940316 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 7646 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 238323 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2256 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 16912 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 4449 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 18154 # number of ReadReq misses +system.l2c.ReadReq_misses::total 287740 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 11 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 19 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 76225 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 18470 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 21026 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115721 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 7632 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 313543 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2302 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 35835 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 4408 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 39568 # number of demand (read+write) misses -system.l2c.demand_misses::total 403288 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 7632 # number of overall misses -system.l2c.overall_misses::cpu0.data 313543 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2302 # number of overall misses -system.l2c.overall_misses::cpu1.data 35835 # number of overall misses -system.l2c.overall_misses::cpu2.inst 4408 # number of overall misses -system.l2c.overall_misses::cpu2.data 39568 # number of overall misses -system.l2c.overall_misses::total 403288 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 186892499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 1138263250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 380152250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1198688249 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2903996248 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 263498 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 263498 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1209958491 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1715474224 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2925432715 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 186892499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2348221741 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 380152250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 2914162473 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 5829428963 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 186892499 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2348221741 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 380152250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 2914162473 # number of overall miss cycles -system.l2c.overall_miss_latency::total 5829428963 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 526449 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 730547 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 126995 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 101095 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 297655 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 257867 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2040608 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835257 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835257 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_misses::cpu2.data 10 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 18 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 76073 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 18069 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 21595 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115737 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 7646 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 314396 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2256 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 34981 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 4449 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 39749 # number of demand (read+write) misses +system.l2c.demand_misses::total 403477 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 7646 # number of overall misses +system.l2c.overall_misses::cpu0.data 314396 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2256 # number of overall misses +system.l2c.overall_misses::cpu1.data 34981 # number of overall misses +system.l2c.overall_misses::cpu2.inst 4449 # number of overall misses +system.l2c.overall_misses::cpu2.data 39749 # number of overall misses +system.l2c.overall_misses::total 403477 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 174436247 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 1133429750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 361724750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1201174749 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2870765496 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 294997 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 294997 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1255826741 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1783349726 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 3039176467 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 174436247 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2389256491 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 361724750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 2984524475 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 5909941963 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 174436247 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2389256491 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 361724750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 2984524475 # number of overall miss cycles +system.l2c.overall_miss_latency::total 5909941963 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 528020 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 731298 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 126347 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 101160 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 297008 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 257301 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2041134 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 835552 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835552 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 14 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 26 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 168781 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 45022 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 88759 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 302562 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 526449 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 899328 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 126995 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 146117 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 297655 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 346626 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2343170 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 526449 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 899328 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 126995 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 146117 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 297655 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 346626 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2343170 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014497 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.324850 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.018127 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.171769 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.014809 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.071905 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.140922 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_accesses::cpu2.data 13 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 25 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 168928 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 44361 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 89370 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 302659 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 528020 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 900226 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 126347 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 145521 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 297008 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 346671 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2343793 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 528020 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 900226 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 126347 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 145521 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 297008 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 346671 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2343793 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014481 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.325890 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.017856 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.167181 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.014979 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.070555 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.140971 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.785714 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.730769 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.500000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.451621 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.410244 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.236889 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.382470 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014497 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.348641 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.018127 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.245249 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.014809 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.114152 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.172112 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014497 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.348641 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.018127 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.245249 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.014809 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.114152 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.172112 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81187.010860 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 65549.280161 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 86241.436025 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 64647.192806 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 10098.503124 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 23954.363636 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 13868.315789 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 65509.393124 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81588.234757 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 25280.050423 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 81187.010860 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 65528.721669 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 86241.436025 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 73649.476168 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 14454.754327 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 81187.010860 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 65528.721669 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 86241.436025 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 73649.476168 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 14454.754327 # average overall miss latency +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.769231 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.720000 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.450328 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.407317 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.241636 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.382401 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014481 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.349241 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.017856 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.240385 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.014979 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.114659 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.172147 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014481 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.349241 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.017856 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.240385 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.014979 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.114659 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.172147 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77321.031472 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 67019.261471 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 81304.731400 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 66165.844938 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 9976.942712 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 29499.700000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 16388.722222 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69501.728983 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82581.603427 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 26259.333377 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 77321.031472 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 68301.549155 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 81304.731400 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 75084.265642 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 14647.531242 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 77321.031472 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 68301.549155 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 81304.731400 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 75084.265642 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 14647.531242 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,105 +566,97 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 75044 # number of writebacks -system.l2c.writebacks::total 75044 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu1.inst 2302 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 17365 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 4408 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 18542 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 42617 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 11 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 18470 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 21026 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 39496 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2302 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 35835 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 4408 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 39568 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 82113 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2302 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 35835 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 4408 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 39568 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 82113 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 157803001 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 920718250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 324243750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 970102251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2372867252 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 261008 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 261008 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 978413509 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1456000776 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2434414285 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 157803001 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1899131759 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 324243750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2426103027 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 4807281537 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 157803001 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1899131759 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 324243750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2426103027 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 4807281537 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 275693000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 292819000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 568512000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 341668500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 404628500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 746297000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 617361500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 697447500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1314809000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018127 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.171769 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014809 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.071905 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.020884 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.785714 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.423077 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.410244 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.236889 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.130539 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018127 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.245249 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014809 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.114152 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.035044 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018127 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.245249 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014809 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.114152 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.035044 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68550.391399 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 53021.494385 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73558.019510 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 52319.180833 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 55678.889927 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 23728 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23728 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 52973.119058 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69247.635118 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61636.983112 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 68550.391399 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52996.560876 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73558.019510 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61314.775248 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58544.707135 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 68550.391399 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52996.560876 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73558.019510 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61314.775248 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58544.707135 # average overall mshr miss latency +system.l2c.writebacks::writebacks 75062 # number of writebacks +system.l2c.writebacks::total 75062 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu1.inst 2256 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 16912 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 4449 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 18154 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 41771 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 10 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 18069 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 21595 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 39664 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2256 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 34981 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 4449 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 39749 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 81435 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2256 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 34981 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 4449 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 39749 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 81435 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 146027753 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 921761250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 305687750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 999134251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2372611004 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 259007 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 259007 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1029550759 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1518288274 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2547839033 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 146027753 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1951312009 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 305687750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2517422525 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 4920450037 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 146027753 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1951312009 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 305687750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2517422525 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 4920450037 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 277798500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 291495500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 569294000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 343775500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 402311000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 746086500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 621574000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 693806500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1315380500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.017856 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.167181 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.070555 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020465 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.769231 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.407317 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.241636 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.131052 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017856 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.240385 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.114659 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034745 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017856 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.240385 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.114659 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034745 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64728.613918 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54503.385170 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 68709.316700 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 55036.589787 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 56800.435805 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 25900.700000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 25900.700000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56978.845481 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70307.398657 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 64235.554483 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64728.613918 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55782.053372 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 68709.316700 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63332.977559 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60421.809259 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64728.613918 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55782.053372 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 68709.316700 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63332.977559 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60421.809259 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -623,14 +668,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254957 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254914 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694872745000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254957 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078435 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078435 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1694870261000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254914 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078432 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078432 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -639,14 +684,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9629212 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9629212 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 4353407559 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4353407559 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4363036771 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4363036771 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4363036771 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4363036771 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9304463 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9304463 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5314395237 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5314395237 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5323699700 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5323699700 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5323699700 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5323699700 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -663,56 +708,56 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55660.184971 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 55660.184971 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104770.108755 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 104770.108755 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 104566.489419 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 104566.489419 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 104566.489419 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 104566.489419 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 114649 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53783.023121 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 53783.023121 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 127897.459497 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 127897.459497 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 127590.166567 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 127590.166567 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 127590.166567 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 127590.166567 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 168405 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11461 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12345 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.003403 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.641555 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 17280 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 17280 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 17350 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 17350 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 17350 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 17350 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5987712 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5987712 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3454277559 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3454277559 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3460265271 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3460265271 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3460265271 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3460265271 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415818 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.415818 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415818 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.415818 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 85538.742857 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 85538.742857 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199900.321701 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199900.321701 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199438.920519 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 199438.920519 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199438.920519 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 199438.920519 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::tsunami.ide 16896 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 16896 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 16965 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 16965 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 16965 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5715463 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5715463 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4435167237 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4435167237 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 4440882700 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4440882700 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 4440882700 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4440882700 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.406623 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.406591 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82832.797101 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82832.797101 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 262498.060902 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 262498.060902 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 261767.326849 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 261767.326849 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 261767.326849 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 261767.326849 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -730,22 +775,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4909978 # DTB read hits -system.cpu0.dtb.read_misses 6100 # DTB read misses +system.cpu0.dtb.read_hits 4920992 # DTB read hits +system.cpu0.dtb.read_misses 6099 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 428319 # DTB read accesses -system.cpu0.dtb.write_hits 3504299 # DTB write hits -system.cpu0.dtb.write_misses 671 # DTB write misses +system.cpu0.dtb.read_accesses 428234 # DTB read accesses +system.cpu0.dtb.write_hits 3511178 # DTB write hits +system.cpu0.dtb.write_misses 670 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 163761 # DTB write accesses -system.cpu0.dtb.data_hits 8414277 # DTB hits -system.cpu0.dtb.data_misses 6771 # DTB misses +system.cpu0.dtb.write_accesses 163777 # DTB write accesses +system.cpu0.dtb.data_hits 8432170 # DTB hits +system.cpu0.dtb.data_misses 6769 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 592080 # DTB accesses -system.cpu0.itb.fetch_hits 2758234 # ITB hits +system.cpu0.dtb.data_accesses 592011 # DTB accesses +system.cpu0.itb.fetch_hits 2763046 # ITB hits system.cpu0.itb.fetch_misses 3034 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2761268 # ITB accesses +system.cpu0.itb.fetch_accesses 2766080 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -758,51 +803,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928316891 # number of cpu cycles simulated +system.cpu0.numCycles 928344318 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33736461 # Number of instructions committed -system.cpu0.committedOps 33736461 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31599588 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 169686 # Number of float alu accesses -system.cpu0.num_func_calls 810809 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4665593 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31599588 # number of integer instructions -system.cpu0.num_fp_insts 169686 # number of float instructions -system.cpu0.num_int_register_reads 44374544 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23060255 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87629 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 89168 # number of times the floating registers were written -system.cpu0.num_mem_refs 8444409 # number of memory refs -system.cpu0.num_load_insts 4931349 # Number of load instructions -system.cpu0.num_store_insts 3513060 # Number of store instructions -system.cpu0.num_idle_cycles 903633014.989213 # Number of idle cycles -system.cpu0.num_busy_cycles 24683876.010787 # Number of busy cycles -system.cpu0.not_idle_fraction 0.026590 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.973410 # Percentage of idle cycles +system.cpu0.committedInsts 33880492 # Number of instructions committed +system.cpu0.committedOps 33880492 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31739536 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 169894 # Number of float alu accesses +system.cpu0.num_func_calls 813170 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4699422 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31739536 # number of integer instructions +system.cpu0.num_fp_insts 169894 # number of float instructions +system.cpu0.num_int_register_reads 44596322 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23159667 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87728 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 89270 # number of times the floating registers were written +system.cpu0.num_mem_refs 8462332 # number of memory refs +system.cpu0.num_load_insts 4942381 # Number of load instructions +system.cpu0.num_store_insts 3519951 # Number of store instructions +system.cpu0.num_idle_cycles 904625586.132235 # Number of idle cycles +system.cpu0.num_busy_cycles 23718731.867765 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025549 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974451 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6419 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211396 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74806 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6416 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211386 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl system.cpu0.kern.ipl_count::31 105698 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182586 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73439 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::total 182585 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73439 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148960 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819515680500 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39349500 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 365678500 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22783774000 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842704482500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1819501633500 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38918500 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 365019000 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22792135500 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842697706500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694800 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815835 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694791 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815828 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -841,7 +886,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175327 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175326 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -850,20 +895,20 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192242 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1908 -system.cpu0.kern.mode_good::user 1738 +system.cpu0.kern.callpal::total 192241 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1909 +system.cpu0.kern.mode_good::user 1739 system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322357 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29786026000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2614250500 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810304201500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391309 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29773270000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2593332500 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810331099500 98.24% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -896,444 +941,427 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110422039 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 786602 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 786555 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3756 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3756 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 371447 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 15 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 151061 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 133781 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 32 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 849315 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370344 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 2219659 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27177600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55325386 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 82502986 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 203464200 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 11072 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2135432500 # Layer occupancy (ticks) +system.toL2Bus.throughput 110448008 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 784800 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 784578 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3750 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3750 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 371852 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 150627 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 133731 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 207 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 846719 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1369630 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 2216349 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27094720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55304714 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 82399434 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 203511688 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 10688 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2136322000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1913139810 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1907046997 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2237602233 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2233138904 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1469136 # Throughput (bytes/s) +system.iobus.throughput 1469141 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 2975 # Transaction distribution system.iobus.trans_dist::ReadResp 2975 # Transaction distribution -system.iobus.trans_dist::WriteReq 21036 # Transaction distribution -system.iobus.trans_dist::WriteResp 21036 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 20646 # Transaction distribution +system.iobus.trans_dist::WriteResp 20646 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2330 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8320 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2420 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8372 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2374 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 13322 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 34700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 48022 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 13312 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 47242 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1574 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4186 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1548 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15754 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1123130 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15690 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1098482 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 2707184 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 2199000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6200000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6239000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 1827000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 1789000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 157303021 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 153606200 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9566000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9562000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17990250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17411500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 950451 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.192015 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43221003 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 950962 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 45.449769 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10381115250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 246.999230 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 99.674980 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 164.517805 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.482420 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194678 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.321324 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998422 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 33216972 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7763860 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2240171 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43221003 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 33216972 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7763860 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2240171 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43221003 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 33216972 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7763860 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2240171 # number of overall hits -system.cpu0.icache.overall_hits::total 43221003 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 526470 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 126995 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 313704 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 967169 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 526470 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 126995 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 313704 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 967169 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 526470 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 126995 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 313704 # number of overall misses -system.cpu0.icache.overall_misses::total 967169 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1823123501 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4463889198 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6287012699 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1823123501 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4463889198 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6287012699 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1823123501 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4463889198 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6287012699 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 33743442 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7890855 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2553875 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 44188172 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 33743442 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7890855 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2553875 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 44188172 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 33743442 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7890855 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2553875 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 44188172 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015602 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016094 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122835 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.021888 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015602 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016094 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122835 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.021888 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015602 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016094 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122835 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.021888 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14355.868349 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14229.621548 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6500.428259 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14355.868349 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14229.621548 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6500.428259 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14355.868349 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14229.621548 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6500.428259 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4785 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 202 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.688119 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.tags.replacements 950723 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.190316 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43428114 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 951234 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 45.654501 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10399272250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.695807 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 99.603495 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 159.891014 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.491593 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194538 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.312287 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998419 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 33359431 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7828902 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2239781 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 43428114 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 33359431 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7828902 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2239781 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 43428114 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 33359431 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7828902 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2239781 # number of overall hits +system.cpu0.icache.overall_hits::total 43428114 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 528040 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 126347 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 313191 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 967578 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 528040 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 126347 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 313191 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 967578 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 528040 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 126347 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 313191 # number of overall misses +system.cpu0.icache.overall_misses::total 967578 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1802440753 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4440627379 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6243068132 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1802440753 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4440627379 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6243068132 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1802440753 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4440627379 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6243068132 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 33887471 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7955249 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2552972 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 44395692 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 33887471 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7955249 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2552972 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 44395692 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 33887471 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7955249 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2552972 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 44395692 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015582 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015882 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122677 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.021794 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015582 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015882 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122677 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.021794 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015582 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015882 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122677 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.021794 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14265.797787 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14178.655769 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6452.263416 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14265.797787 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14178.655769 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6452.263416 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14265.797787 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14178.655769 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6452.263416 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4969 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 740 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 199 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.969849 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 740 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16034 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16034 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16034 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16034 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16034 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16034 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 126995 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 297670 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 424665 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 126995 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 297670 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 424665 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 126995 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 297670 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 424665 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1568013499 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3675865433 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5243878932 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1568013499 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3675865433 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5243878932 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1568013499 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3675865433 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5243878932 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016094 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116556 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009610 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016094 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116556 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009610 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016094 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116556 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009610 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12347.049089 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12348.793741 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12348.272007 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12347.049089 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12348.793741 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12348.272007 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12347.049089 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12348.793741 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12348.272007 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16174 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16174 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16174 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16174 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16174 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16174 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 126347 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 297017 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 423364 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 126347 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 297017 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 423364 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 126347 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 297017 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 423364 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1548840247 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3650495745 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5199335992 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1548840247 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3650495745 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5199335992 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1548840247 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3650495745 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5199335992 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015882 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116342 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009536 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015882 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116342 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009536 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015882 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116342 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009536 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.623054 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12290.527966 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12281.006396 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.623054 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12290.527966 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12281.006396 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.623054 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12290.527966 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12281.006396 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1391525 # number of replacements +system.cpu0.dcache.tags.replacements 1391697 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13285085 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1392037 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.543629 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13286622 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1392209 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.543554 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 250.196143 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 130.348399 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 131.453270 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.488664 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.254587 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.256745 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 248.161883 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 130.279675 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 133.556253 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.484691 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.254452 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.260852 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4073389 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1086662 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2399601 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7559652 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3208453 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 837545 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1295843 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5341841 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116948 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19346 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47955 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184249 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126113 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21379 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51797 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199289 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7281842 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1924207 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3695444 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12901493 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7281842 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1924207 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3695444 # number of overall hits -system.cpu0.dcache.overall_hits::total 12901493 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 720818 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 98930 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 533963 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1353711 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 168792 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 45023 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 591984 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 805799 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9729 # number of LoadLockedReq misses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4083341 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1084976 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2395652 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7563969 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3214796 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 832699 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1291573 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5339068 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117279 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19300 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47662 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184241 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126504 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21337 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51447 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199288 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7298137 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1917675 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3687225 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12903037 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7298137 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1917675 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3687225 # number of overall hits +system.cpu0.dcache.overall_hits::total 12903037 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 721507 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 98995 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 533015 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1353517 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 168939 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 44362 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 596400 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 809701 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9791 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2165 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6797 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18691 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 889610 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 143953 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1125947 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2159510 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 889610 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 143953 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1125947 # number of overall misses -system.cpu0.dcache.overall_misses::total 2159510 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2262060250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9361678086 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11623738336 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1620272009 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 17690504226 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19310776235 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28582500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 102574499 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 131156999 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 38001 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 38001 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3882332259 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 27052182312 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 30934514571 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3882332259 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 27052182312 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 30934514571 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4794207 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1185592 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 2933564 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8913363 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3377245 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 882568 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1887827 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6147640 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126677 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21511 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54752 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 202940 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126113 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21379 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51799 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199291 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8171452 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2068160 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 4821391 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15061003 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8171452 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2068160 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 4821391 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15061003 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150352 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083444 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.182019 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.151874 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049979 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051014 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.313580 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.131075 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076802 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100646 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.124142 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092101 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000039 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108868 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069604 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233532 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.143384 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108868 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069604 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233532 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.143384 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22865.260790 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17532.447166 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8586.573010 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35987.650956 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 29883.416150 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23964.755770 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13202.078522 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15091.143004 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7017.120486 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 19000.500000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 19000.500000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26969.443214 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24026.159590 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14324.784127 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26969.443214 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24026.159590 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14324.784127 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 557875 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 852 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 17918 # number of cycles access was blocked +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6803 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18759 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 890446 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 143357 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1129415 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2163218 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 890446 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 143357 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1129415 # number of overall misses +system.cpu0.dcache.overall_misses::total 2163218 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2262107000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9348260996 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11610367996 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1660998759 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18147263609 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 19808262368 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28538250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 102812500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 131350750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 3923105759 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 27495524605 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 31418630364 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 3923105759 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 27495524605 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 31418630364 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4804848 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1183971 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 2928667 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8917486 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3383735 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 877061 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 1887973 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6148769 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 127070 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21465 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54465 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203000 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126504 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21337 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51447 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 199288 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8188583 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 2061032 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 4816640 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15066255 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8188583 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 2061032 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 4816640 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15066255 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150162 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083613 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181999 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.151782 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049927 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050580 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315894 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.131685 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077052 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100862 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.124906 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092409 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108742 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069556 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.234482 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.143580 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108742 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069556 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.234482 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.143580 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22850.719733 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17538.457634 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8577.925505 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37441.926852 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30428.007393 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 24463.675317 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13181.639723 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15112.817874 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7002.012367 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27365.986725 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24344.926006 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14524.024099 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27365.986725 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24344.926006 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14524.024099 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 591087 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 822 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 17697 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 31.134892 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 121.714286 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 33.400407 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 117.428571 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835257 # number of writebacks -system.cpu0.dcache.writebacks::total 835257 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 281255 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 281255 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 503456 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 503456 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1394 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1394 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 784711 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 784711 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 784711 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 784711 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 98930 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 252708 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 351638 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 45023 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 88528 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 133551 # number of WriteReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 835552 # number of writebacks +system.cpu0.dcache.writebacks::total 835552 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 280898 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 280898 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 507265 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 507265 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1373 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1373 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 788163 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 788163 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 788163 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 788163 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 98995 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 252117 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 351112 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 44362 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 89135 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 133497 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2165 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5403 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7568 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 143953 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 341236 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 485189 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 143953 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 341236 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 485189 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2055649750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4240939408 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6296589158 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1521155991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2563125747 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4084281738 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24249500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66698251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90947751 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33999 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33999 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3576805741 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6804065155 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10380870896 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3576805741 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6804065155 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10380870896 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 294283500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 312003000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 606286500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 361937500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 429433000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 791370500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 656221000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 741436000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1397657000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083444 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086144 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039451 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051014 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046894 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021724 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100646 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098681 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037292 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000039 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000010 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069604 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070775 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032215 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069604 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070775 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032215 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20778.830992 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16781.975276 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17906.452539 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33786.197965 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 28952.712667 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30582.187614 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11200.692841 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12344.669813 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12017.408959 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 16999.500000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16999.500000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24847.038554 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19939.470498 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21395.519882 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24847.038554 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19939.470498 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21395.519882 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5430 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7595 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 143357 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 341252 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 484609 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 143357 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 341252 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 484609 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2056105000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4263367239 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6319472239 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1563762241 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2632845749 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4196607990 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24206750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66163500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90370250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3619867241 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6896212988 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10516080229 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3619867241 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6896212988 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10516080229 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296519000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 310561500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 607080500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 364164500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 426924000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 791088500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 660683500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 737485500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1398169000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083613 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086086 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039373 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050580 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047212 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021711 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100862 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099697 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037414 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069556 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070849 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032165 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069556 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070849 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032165 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20769.786353 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16910.272766 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17998.451318 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35250.039245 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29537.732081 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31435.972269 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11180.946882 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12184.806630 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11898.650428 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25250.718423 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20208.564310 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21700.133982 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25250.718423 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20208.564310 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21700.133982 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1348,22 +1376,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1205047 # DTB read hits -system.cpu1.dtb.read_misses 1367 # DTB read misses +system.cpu1.dtb.read_hits 1203387 # DTB read hits +system.cpu1.dtb.read_misses 1366 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 142944 # DTB read accesses -system.cpu1.dtb.write_hits 904403 # DTB write hits -system.cpu1.dtb.write_misses 185 # DTB write misses -system.cpu1.dtb.write_acv 23 # DTB write access violations -system.cpu1.dtb.write_accesses 58533 # DTB write accesses -system.cpu1.dtb.data_hits 2109450 # DTB hits -system.cpu1.dtb.data_misses 1552 # DTB misses -system.cpu1.dtb.data_acv 57 # DTB access violations -system.cpu1.dtb.data_accesses 201477 # DTB accesses -system.cpu1.itb.fetch_hits 861634 # ITB hits -system.cpu1.itb.fetch_misses 693 # ITB misses +system.cpu1.dtb.read_accesses 142939 # DTB read accesses +system.cpu1.dtb.write_hits 898859 # DTB write hits +system.cpu1.dtb.write_misses 183 # DTB write misses +system.cpu1.dtb.write_acv 22 # DTB write access violations +system.cpu1.dtb.write_accesses 58529 # DTB write accesses +system.cpu1.dtb.data_hits 2102246 # DTB hits +system.cpu1.dtb.data_misses 1549 # DTB misses +system.cpu1.dtb.data_acv 56 # DTB access violations +system.cpu1.dtb.data_accesses 201468 # DTB accesses +system.cpu1.itb.fetch_hits 859133 # ITB hits +system.cpu1.itb.fetch_misses 692 # ITB misses system.cpu1.itb.fetch_acv 30 # ITB acv -system.cpu1.itb.fetch_accesses 862327 # ITB accesses +system.cpu1.itb.fetch_accesses 859825 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1376,28 +1404,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953630418 # number of cpu cycles simulated +system.cpu1.numCycles 953620014 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7889245 # Number of instructions committed -system.cpu1.committedOps 7889245 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7344952 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 44937 # Number of float alu accesses -system.cpu1.num_func_calls 213049 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 993802 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7344952 # number of integer instructions -system.cpu1.num_fp_insts 44937 # number of float instructions -system.cpu1.num_int_register_reads 10269748 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5343251 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24271 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24577 # number of times the floating registers were written -system.cpu1.num_mem_refs 2116682 # number of memory refs -system.cpu1.num_load_insts 1209934 # Number of load instructions -system.cpu1.num_store_insts 906748 # Number of store instructions -system.cpu1.num_idle_cycles 923700977.463911 # Number of idle cycles -system.cpu1.num_busy_cycles 29929440.536089 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031385 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968615 # Percentage of idle cycles +system.cpu1.committedInsts 7953643 # Number of instructions committed +system.cpu1.committedOps 7953643 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7410219 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45003 # Number of float alu accesses +system.cpu1.num_func_calls 212713 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1020267 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7410219 # number of integer instructions +system.cpu1.num_fp_insts 45003 # number of float instructions +system.cpu1.num_int_register_reads 10384111 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5386902 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24304 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24611 # number of times the floating registers were written +system.cpu1.num_mem_refs 2109479 # number of memory refs +system.cpu1.num_load_insts 1208276 # Number of load instructions +system.cpu1.num_store_insts 901203 # Number of store instructions +system.cpu1.num_idle_cycles 922135498.680812 # Number of idle cycles +system.cpu1.num_busy_cycles 31484515.319188 # Number of busy cycles +system.cpu1.not_idle_fraction 0.033016 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.966984 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1415,35 +1443,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9022316 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8342315 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 122648 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7529449 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6410701 # Number of BTB hits +system.cpu2.branchPred.lookups 9128355 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8449925 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 124319 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7461780 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6520544 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 85.141702 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 283187 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 12478 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 87.385905 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 281902 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 13317 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3192037 # DTB read hits -system.cpu2.dtb.read_misses 11608 # DTB read misses +system.cpu2.dtb.read_hits 3185589 # DTB read hits +system.cpu2.dtb.read_misses 11798 # DTB read misses system.cpu2.dtb.read_acv 121 # DTB read access violations -system.cpu2.dtb.read_accesses 216573 # DTB read accesses -system.cpu2.dtb.write_hits 2009173 # DTB write hits -system.cpu2.dtb.write_misses 2522 # DTB write misses +system.cpu2.dtb.read_accesses 217406 # DTB read accesses +system.cpu2.dtb.write_hits 2009886 # DTB write hits +system.cpu2.dtb.write_misses 2608 # DTB write misses system.cpu2.dtb.write_acv 106 # DTB write access violations -system.cpu2.dtb.write_accesses 81978 # DTB write accesses -system.cpu2.dtb.data_hits 5201210 # DTB hits -system.cpu2.dtb.data_misses 14130 # DTB misses +system.cpu2.dtb.write_accesses 82301 # DTB write accesses +system.cpu2.dtb.data_hits 5195475 # DTB hits +system.cpu2.dtb.data_misses 14406 # DTB misses system.cpu2.dtb.data_acv 227 # DTB access violations -system.cpu2.dtb.data_accesses 298551 # DTB accesses -system.cpu2.itb.fetch_hits 369667 # ITB hits -system.cpu2.itb.fetch_misses 5681 # ITB misses -system.cpu2.itb.fetch_acv 262 # ITB acv -system.cpu2.itb.fetch_accesses 375348 # ITB accesses +system.cpu2.dtb.data_accesses 299707 # DTB accesses +system.cpu2.itb.fetch_hits 369992 # ITB hits +system.cpu2.itb.fetch_misses 5727 # ITB misses +system.cpu2.itb.fetch_acv 273 # ITB acv +system.cpu2.itb.fetch_accesses 375719 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1456,270 +1484,270 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31245078 # number of cpu cycles simulated +system.cpu2.numCycles 31308710 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8348883 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 36663716 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9022316 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6693888 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8736568 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 602984 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9694630 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 11222 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1957 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 63711 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 86195 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 437 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2553880 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 85053 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27335965 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.341226 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.294449 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8320877 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 36988805 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9128355 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6802446 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8846835 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 603748 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9639992 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 11047 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1973 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 63718 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 87241 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 497 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2552980 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 86276 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27364450 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.351710 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.294118 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18599397 68.04% 68.04% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 269863 0.99% 69.03% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 429102 1.57% 70.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4885317 17.87% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 756803 2.77% 91.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 166340 0.61% 91.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 191609 0.70% 92.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 429140 1.57% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1608394 5.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18517615 67.67% 67.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 268760 0.98% 68.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 429758 1.57% 70.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4997201 18.26% 88.48% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 759565 2.78% 91.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 164512 0.60% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 190396 0.70% 92.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 427414 1.56% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1609229 5.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27335965 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.288760 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.173424 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8495766 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9778515 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8128034 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 307242 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 380496 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 165135 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12538 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36269918 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 39153 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 380496 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8853799 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2797423 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5789351 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7998658 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1270334 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35131949 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2438 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 231189 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 444117 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 23541427 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 43931372 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 43874902 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 52705 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 21760313 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1781114 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 501831 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 59191 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3719256 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3350609 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2097879 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 369762 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 260934 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32641753 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 622044 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32196803 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 34835 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2138258 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1073109 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 438824 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27335965 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.177818 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.573987 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27364450 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.291560 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.181422 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8471005 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9721532 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8236973 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 308822 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 380199 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 165870 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12770 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36596033 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40157 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 380199 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8829996 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2781091 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5750095 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8109315 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1267845 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35455371 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2432 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 230458 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 443882 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 23756988 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44373855 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 44317462 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 52634 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21971271 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1785717 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 500561 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 59005 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3706520 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3341982 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2099682 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 368903 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 258103 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32963824 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 619272 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32519364 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 32677 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2138512 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1074729 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 437003 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27364450 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.188380 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.575952 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15167963 55.49% 55.49% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3067850 11.22% 66.71% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1557003 5.70% 72.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5712284 20.90% 93.30% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 903378 3.30% 96.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 480833 1.76% 98.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 285081 1.04% 99.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 142652 0.52% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18921 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15094542 55.16% 55.16% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3058510 11.18% 66.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1555503 5.68% 72.02% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5825063 21.29% 93.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 904805 3.31% 96.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 480018 1.75% 98.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 285628 1.04% 99.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 141467 0.52% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18914 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27335965 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27364450 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 33684 13.60% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 113022 45.64% 59.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 100957 40.76% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 33388 13.55% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 112327 45.58% 59.13% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 100703 40.87% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26526068 82.39% 82.39% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20082 0.06% 82.46% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8432 0.03% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3318552 10.31% 92.79% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2030927 6.31% 99.10% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 289082 0.90% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26855600 82.58% 82.59% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20032 0.06% 82.65% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.65% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8424 0.03% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3311528 10.18% 92.87% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2031960 6.25% 99.11% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 288160 0.89% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32196803 # Type of FU issued -system.cpu2.iq.rate 1.030460 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 247663 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007692 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 91777621 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 35291242 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 31803164 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 234448 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114643 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110912 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32319915 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 122111 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 186470 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32519364 # Type of FU issued +system.cpu2.iq.rate 1.038668 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 246418 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007578 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 92448223 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 35610975 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 32122316 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 234050 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114559 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110669 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32641435 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 121907 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 186593 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 409308 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1087 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3940 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 154806 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 407978 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1104 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4025 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 156833 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4179 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 28515 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4157 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 26970 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 380496 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2018433 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 205280 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 34533473 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 223572 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3350609 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2097879 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 552418 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 143005 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2030 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3940 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 62474 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 127218 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 189692 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 32041792 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3211958 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 155011 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 380199 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2010765 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 204147 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34852291 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 222063 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3341982 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2099682 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 549953 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 141753 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1988 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4025 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63582 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 127875 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 191457 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32361861 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3205658 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 157503 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1269676 # number of nop insts executed -system.cpu2.iew.exec_refs 5228104 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7451179 # Number of branches executed -system.cpu2.iew.exec_stores 2016146 # Number of stores executed -system.cpu2.iew.exec_rate 1.025499 # Inst execution rate -system.cpu2.iew.wb_sent 31946323 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 31914076 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18560539 # num instructions producing a value -system.cpu2.iew.wb_consumers 21756623 # num instructions consuming a value +system.cpu2.iew.exec_nop 1269195 # number of nop insts executed +system.cpu2.iew.exec_refs 5222587 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7560841 # Number of branches executed +system.cpu2.iew.exec_stores 2016929 # Number of stores executed +system.cpu2.iew.exec_rate 1.033638 # Inst execution rate +system.cpu2.iew.wb_sent 32266608 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 32232985 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18776213 # num instructions producing a value +system.cpu2.iew.wb_consumers 21965918 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.021411 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.853098 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.029521 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.854788 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2307107 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 183220 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 175579 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26955469 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.193861 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.846623 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2305690 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 182269 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 176747 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26984251 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.204438 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.848007 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16175286 60.01% 60.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2330504 8.65% 68.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1226068 4.55% 73.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5456953 20.24% 93.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 503178 1.87% 95.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 186113 0.69% 96.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 177622 0.66% 96.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 179384 0.67% 97.33% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 720361 2.67% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16102351 59.67% 59.67% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2321930 8.60% 68.28% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1225737 4.54% 72.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5569081 20.64% 93.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 502606 1.86% 95.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 185666 0.69% 96.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 176683 0.65% 96.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 180209 0.67% 97.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 719988 2.67% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26955469 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32181084 # Number of instructions committed -system.cpu2.commit.committedOps 32181084 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26984251 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32500866 # Number of instructions committed +system.cpu2.commit.committedOps 32500866 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4884374 # Number of memory references committed -system.cpu2.commit.loads 2941301 # Number of loads committed -system.cpu2.commit.membars 64148 # Number of memory barriers committed -system.cpu2.commit.branches 7305681 # Number of branches committed -system.cpu2.commit.fp_insts 109768 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 30735120 # Number of committed integer instructions. -system.cpu2.commit.function_calls 229363 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 720361 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4876853 # Number of memory references committed +system.cpu2.commit.loads 2934004 # Number of loads committed +system.cpu2.commit.membars 63840 # Number of memory barriers committed +system.cpu2.commit.branches 7415854 # Number of branches committed +system.cpu2.commit.fp_insts 109494 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 31057555 # Number of committed integer instructions. +system.cpu2.commit.function_calls 228510 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 719988 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 60649307 # The number of ROB reads -system.cpu2.rob.rob_writes 69356385 # The number of ROB writes -system.cpu2.timesIdled 245741 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3909113 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1746532644 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31016177 # Number of Instructions Simulated -system.cpu2.committedOps 31016177 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 31016177 # Number of Instructions Simulated -system.cpu2.cpi 1.007380 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.007380 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.992674 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.992674 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42141472 # number of integer regfile reads -system.cpu2.int_regfile_writes 22438304 # number of integer regfile writes -system.cpu2.fp_regfile_reads 67749 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68082 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5235386 # number of misc regfile reads -system.cpu2.misc_regfile_writes 258296 # number of misc regfile writes +system.cpu2.rob.rob_reads 60996891 # The number of ROB reads +system.cpu2.rob.rob_writes 69992925 # The number of ROB writes +system.cpu2.timesIdled 244953 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3944260 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746464525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31337447 # Number of Instructions Simulated +system.cpu2.committedOps 31337447 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 31337447 # Number of Instructions Simulated +system.cpu2.cpi 0.999083 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.999083 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.000918 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.000918 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42570866 # number of integer regfile reads +system.cpu2.int_regfile_writes 22648106 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67644 # number of floating regfile reads +system.cpu2.fp_regfile_writes 67951 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5345306 # number of misc regfile reads +system.cpu2.misc_regfile_writes 257045 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 5c2619e22..8cfdfc3f7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,132 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.524310 # Number of seconds simulated -sim_ticks 2524309551500 # Number of ticks simulated -final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525141 # Number of seconds simulated +sim_ticks 2525141046500 # Number of ticks simulated +final_tick 2525141046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55803 # Simulator instruction rate (inst/s) -host_op_rate 71803 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2335855340 # Simulator tick rate (ticks/s) -host_mem_usage 401408 # Number of bytes of host memory used -host_seconds 1080.68 # Real time elapsed on the host -sim_insts 60305560 # Number of instructions simulated -sim_ops 77596391 # Number of ops (including micro ops) simulated +host_inst_rate 50522 # Simulator instruction rate (inst/s) +host_op_rate 65007 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2115457252 # Simulator tick rate (ticks/s) +host_mem_usage 427804 # Number of bytes of host memory used +host_seconds 1193.66 # Real time elapsed on the host +sim_insts 60305756 # Number of instructions simulated +sim_ops 77596741 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory -system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094416 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784000 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800072 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142134 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59125 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 966197440 # Total number of bytes read from memory -system.physmem.bytesWritten 52040704 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943576 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943285 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 942562 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943112 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943114 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 941930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943211 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 941608 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943681 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943781 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 942622 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6701 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6473 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6647 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6560 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6809 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6802 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6725 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6889 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6554 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6197 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6775 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7049 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2524308440000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14942208 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154591 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754018 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59118 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1057147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 988434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 981496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3682842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2771885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2756532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2709889 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 16218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47339005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3601548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51257392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498530 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2692947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47339005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4795965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53950339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096843 # Number of read requests accepted +system.physmem.writeReqs 813143 # Number of write requests accepted +system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813143 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue +system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6800072 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943582 # Per bank write bursts +system.physmem.perBankRdBursts::1 943145 # Per bank write bursts +system.physmem.perBankRdBursts::2 939291 # Per bank write bursts +system.physmem.perBankRdBursts::3 939307 # Per bank write bursts +system.physmem.perBankRdBursts::4 943115 # Per bank write bursts +system.physmem.perBankRdBursts::5 943141 # Per bank write bursts +system.physmem.perBankRdBursts::6 939138 # Per bank write bursts +system.physmem.perBankRdBursts::7 938546 # Per bank write bursts +system.physmem.perBankRdBursts::8 943996 # Per bank write bursts +system.physmem.perBankRdBursts::9 943390 # Per bank write bursts +system.physmem.perBankRdBursts::10 938426 # Per bank write bursts +system.physmem.perBankRdBursts::11 937974 # Per bank write bursts +system.physmem.perBankRdBursts::12 943928 # Per bank write bursts +system.physmem.perBankRdBursts::13 943533 # Per bank write bursts +system.physmem.perBankRdBursts::14 939234 # Per bank write bursts +system.physmem.perBankRdBursts::15 938672 # Per bank write bursts +system.physmem.perBankWrBursts::0 6704 # Per bank write bursts +system.physmem.perBankWrBursts::1 6457 # Per bank write bursts +system.physmem.perBankWrBursts::2 6598 # Per bank write bursts +system.physmem.perBankWrBursts::3 6635 # Per bank write bursts +system.physmem.perBankWrBursts::4 6561 # Per bank write bursts +system.physmem.perBankWrBursts::5 6794 # Per bank write bursts +system.physmem.perBankWrBursts::6 6789 # Per bank write bursts +system.physmem.perBankWrBursts::7 6723 # Per bank write bursts +system.physmem.perBankWrBursts::8 7136 # Per bank write bursts +system.physmem.perBankWrBursts::9 6877 # Per bank write bursts +system.physmem.perBankWrBursts::10 6538 # Per bank write bursts +system.physmem.perBankWrBursts::11 6183 # Per bank write bursts +system.physmem.perBankWrBursts::12 7149 # Per bank write bursts +system.physmem.perBankWrBursts::13 6765 # Per bank write bursts +system.physmem.perBankWrBursts::14 7038 # Per bank write bursts +system.physmem.perBankWrBursts::15 6899 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2525139929000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 36 # Read request sizes (log2) +system.physmem.readPktSize::3 14942208 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 154599 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 59125 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1163754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1108384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1064134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3627605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2618920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2606295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2613037 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 58180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -140,294 +142,604 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-143 3432 8.79% 25.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-207 2242 5.74% 31.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-271 1810 4.64% 36.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-399 1032 2.64% 42.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-463 839 2.15% 44.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-591 572 1.47% 47.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-655 506 1.30% 49.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-719 409 1.05% 50.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-783 444 1.14% 51.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-847 300 0.77% 52.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-911 247 0.63% 52.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-975 176 0.45% 53.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1039 206 0.53% 53.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1103 143 0.37% 54.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1167 146 0.37% 54.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1231 98 0.25% 54.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1295 114 0.29% 54.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1359 72 0.18% 55.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1423 399 1.02% 56.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1487 280 0.72% 56.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1551 475 1.22% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1615 79 0.20% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1679 157 0.40% 58.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1743 41 0.11% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1807 100 0.26% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1871 28 0.07% 59.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1935 78 0.20% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1999 27 0.07% 59.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2063 49 0.13% 59.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2127 25 0.06% 59.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2191 51 0.13% 59.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2255 21 0.05% 59.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2319 30 0.08% 59.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2447 27 0.07% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2511 11 0.03% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2575 21 0.05% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2639 5 0.01% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2703 18 0.05% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2767 7 0.02% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2831 11 0.03% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2895 7 0.02% 60.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2959 14 0.04% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3023 6 0.02% 60.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3087 22 0.06% 60.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3215 7 0.02% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3279 4 0.01% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3343 12 0.03% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3599 9 0.02% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3727 6 0.02% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3791 3 0.01% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3855 8 0.02% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3919 3 0.01% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3983 10 0.03% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4047 5 0.01% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4111 44 0.11% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4175 3 0.01% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4239 1 0.00% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4303 5 0.01% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4367 9 0.02% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4495 1 0.00% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4559 3 0.01% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4623 9 0.02% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4687 1 0.00% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4815 1 0.00% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4879 2 0.01% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5007 4 0.01% 60.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5135 7 0.02% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5263 3 0.01% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5391 4 0.01% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5455 1 0.00% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5519 3 0.01% 60.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5775 3 0.01% 60.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5903 3 0.01% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5967 1 0.00% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6031 1 0.00% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6223 1 0.00% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6287 3 0.01% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6479 4 0.01% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6607 2 0.01% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6735 2 0.01% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6799 18 0.05% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6863 4 0.01% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7183 4 0.01% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7311 4 0.01% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7375 1 0.00% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7439 12 0.03% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7503 1 0.00% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7567 2 0.01% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7695 9 0.02% 61.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7823 3 0.01% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7887 2 0.01% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7951 5 0.01% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8015 1 0.00% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8079 7 0.02% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8143 2 0.01% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8207 325 0.83% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8463 41 0.11% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8527 123 0.32% 62.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8591 7 0.02% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8719 1 0.00% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8783 1 0.00% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9231 8 0.02% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9487 2 0.01% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9743 1 0.00% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9999 1 0.00% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10255 2 0.01% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12303 3 0.01% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12559 2 0.01% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13071 1 0.00% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13327 3 0.01% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13583 2 0.01% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13839 1 0.00% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14095 1 0.00% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14351 4 0.01% 62.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14607 2 0.01% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14991 1 0.00% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15119 1 0.00% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15375 1 0.00% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16399 1 0.00% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17167 3 0.01% 62.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17423 3 0.01% 62.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17679 2 0.01% 62.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17935 1 0.00% 62.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18191 2 0.01% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18447 2 0.01% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18703 1 0.00% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19215 2 0.01% 62.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19471 3 0.01% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19727 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21519 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21775 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22208-22223 1 0.00% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22287 2 0.01% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22543 4 0.01% 62.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22799 3 0.01% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23311 1 0.00% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23567 3 0.01% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23616-23631 1 0.00% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24335 1 0.00% 62.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24591 2 0.01% 62.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25359 2 0.01% 62.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25615 3 0.01% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26127 2 0.01% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26383 1 0.00% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26639 1 0.00% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27151 1 0.00% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27663 2 0.01% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27919 4 0.01% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28687 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28943 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29199 2 0.01% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29455 1 0.00% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30479 1 0.00% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30735 4 0.01% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30991 1 0.00% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31375 1 0.00% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31759 3 0.01% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32783 2 0.01% 62.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33551 12 0.03% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33615 1 0.00% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33743 1 0.00% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33807 45 0.12% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34831 1 0.00% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36367 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37647 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39439 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40271 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41231 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41743 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42767 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44303 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45199 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46095 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47247 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47375 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47631 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48399 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49728-49743 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50255 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50304-50319 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50560-50575 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50752-50767 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51392-51407 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51712-51727 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51968-51983 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52239 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53263 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53824-53839 1 0.00% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56335 2 0.01% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58383 1 0.00% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59407 2 0.01% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60431 2 0.01% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61120-61135 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61184-61199 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61455 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63936-63951 1 0.00% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64527 1 0.00% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65039 192 0.49% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65295 6 0.02% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65551 14116 36.16% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::66048-66063 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::69760-69775 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73536-73551 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73856-73871 2 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73920-73935 24 0.06% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-73999 78 0.20% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74048-74063 68 0.17% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation -system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests -system.physmem.totBusLat 75453215000 # Total cycles spent in databus access -system.physmem.totBankLat 15307050000 # Total cycles spent in bank access -system.physmem.avgQLat 19314.15 # Average queueing delay per request -system.physmem.avgBankLat 1014.34 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25328.49 # Average memory access latency -system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 14.41 # Average write queue length over time -system.physmem.readRowHits 15065383 # Number of row buffer hits during reads -system.physmem.writeRowHits 94229 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes -system.physmem.avgGap 158662.04 # Average gap between requests +system.physmem.bytesPerActivate::samples 86114 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11271.566528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1003.490719 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16771.547354 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23576 27.38% 27.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14050 16.32% 43.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2599 3.02% 46.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2090 2.43% 49.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1311 1.52% 50.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1239 1.44% 52.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 869 1.01% 53.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1005 1.17% 54.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 571 0.66% 54.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 602 0.70% 55.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 523 0.61% 56.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 509 0.59% 56.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 284 0.33% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 276 0.32% 57.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 154 0.18% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 642 0.75% 58.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 97 0.11% 58.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 141 0.16% 58.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 78 0.09% 58.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 123 0.14% 58.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 49 0.06% 58.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 518 0.60% 59.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 316 0.37% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 18 0.02% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 102 0.12% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 211 0.25% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 55 0.06% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 327 0.38% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 31 0.04% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 124 0.14% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 3 0.00% 61.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 9 0.01% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 99 0.11% 61.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 90 0.10% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 23 0.03% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 2 0.00% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 292 0.34% 61.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 98 0.11% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 9 0.01% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 18 0.02% 61.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 8 0.01% 61.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 97 0.11% 62.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 158 0.18% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 373 0.43% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 16 0.02% 62.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 116 0.13% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 99 0.11% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 19 0.02% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 13 0.02% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 426 0.49% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 8 0.01% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 6 0.01% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 28 0.03% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 19 0.02% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 89 0.10% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 2 0.00% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 15 0.02% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 413 0.48% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 87 0.10% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 12 0.01% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 145 0.17% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 24 0.03% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 363 0.42% 65.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 9 0.01% 65.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 10 0.01% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 98 0.11% 65.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 3 0.00% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 82 0.10% 65.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 13 0.02% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 508 0.59% 66.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 76 0.09% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 89 0.10% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 74 0.09% 66.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 350 0.41% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 17 0.02% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 3 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9671 1 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 138 0.16% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 6 0.01% 67.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 402 0.47% 67.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 84 0.10% 67.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 76 0.09% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 15 0.02% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 1 0.00% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 416 0.48% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 13 0.02% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 84 0.10% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 98 0.11% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 5 0.01% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 335 0.39% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 3 0.00% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 141 0.16% 69.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 79 0.09% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 86 0.10% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 4 0.00% 69.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 286 0.33% 69.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 76 0.09% 69.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 74 0.09% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 91 0.11% 70.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 284 0.33% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 2 0.00% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 139 0.16% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 146 0.17% 70.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15303 2 0.00% 70.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 17 0.02% 71.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 80 0.09% 71.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 74 0.09% 71.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 11 0.01% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 645 0.75% 72.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 72 0.08% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16711 2 0.00% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16839 1 0.00% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 78 0.09% 72.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 28 0.03% 72.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 5 0.01% 72.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 407 0.47% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 2 0.00% 72.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 18 0.02% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17735 2 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 3 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 147 0.17% 73.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-17991 1 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18112-18119 2 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 144 0.17% 73.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 4 0.00% 73.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 279 0.32% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 89 0.10% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18880-18887 2 0.00% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 73 0.08% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19143 1 0.00% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 77 0.09% 73.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 5 0.01% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 263 0.31% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 82 0.10% 74.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 79 0.09% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 140 0.16% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20288-20295 1 0.00% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 343 0.40% 74.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20672-20679 1 0.00% 74.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 96 0.11% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20864-20871 2 0.00% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 82 0.10% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21120-21127 1 0.00% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 14 0.02% 75.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 401 0.47% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 17 0.02% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 2 0.00% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 77 0.09% 75.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 1 0.00% 75.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 84 0.10% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 3 0.00% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 1 0.00% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 400 0.46% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 80 0.09% 76.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22976-22983 2 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 136 0.16% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 21 0.02% 76.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23360-23367 3 0.00% 76.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 2 0.00% 76.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 351 0.41% 76.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23687 2 0.00% 76.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 73 0.08% 77.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 83 0.10% 77.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 83 0.10% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 387 0.45% 77.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 78 0.09% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24960-24967 1 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25024-25031 1 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 89 0.10% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25287 1 0.00% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 72 0.08% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 4 0.00% 77.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 349 0.41% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 19 0.02% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 3 0.00% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 133 0.15% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 2 0.00% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 78 0.09% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 401 0.47% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26752-26759 2 0.00% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 82 0.10% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 77 0.09% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 1 0.00% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 15 0.02% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 403 0.47% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 11 0.01% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 2 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 83 0.10% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 97 0.11% 80.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 2 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 341 0.40% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28743 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 2 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 143 0.17% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29056-29063 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 77 0.09% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29248-29255 2 0.00% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 85 0.10% 80.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 3 0.00% 80.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 2 0.00% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 268 0.31% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 76 0.09% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 74 0.09% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 2 0.00% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 92 0.11% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 271 0.31% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 2 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 145 0.17% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 2 0.00% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 148 0.17% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31296-31303 1 0.00% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 19 0.02% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31687 4 0.00% 82.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 398 0.46% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31936-31943 1 0.00% 82.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 18 0.02% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 78 0.09% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 83 0.10% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 642 0.75% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32832-32839 2 0.00% 83.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 73 0.08% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 2 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 78 0.09% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 27 0.03% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 2 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 406 0.47% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 16 0.02% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 144 0.17% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 147 0.17% 84.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 269 0.31% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 87 0.10% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 72 0.08% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 2 0.00% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 77 0.09% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 268 0.31% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 81 0.09% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 77 0.09% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 1 0.00% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 144 0.17% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 2 0.00% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 338 0.39% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36992-36999 1 0.00% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 91 0.11% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 83 0.10% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37568-37575 1 0.00% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 11 0.01% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 404 0.47% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 15 0.02% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 1 0.00% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 77 0.09% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 1 0.00% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 84 0.10% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 401 0.47% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 2 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 130 0.15% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 15 0.02% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 348 0.40% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 3 0.00% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 71 0.08% 88.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 86 0.10% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 78 0.09% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 387 0.45% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 2 0.00% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 78 0.09% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41351 2 0.00% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 83 0.10% 89.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 347 0.40% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 18 0.02% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 133 0.15% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 3 0.00% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 79 0.09% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 399 0.46% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 82 0.10% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 76 0.09% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 20 0.02% 90.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 403 0.47% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 10 0.01% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 81 0.09% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 96 0.11% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 341 0.40% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 143 0.17% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 82 0.10% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 5 0.01% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 84 0.10% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 1 0.00% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 261 0.30% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 73 0.08% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 68 0.08% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 91 0.11% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 272 0.32% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 142 0.16% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 144 0.17% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 25 0.03% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 395 0.46% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 16 0.02% 93.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 76 0.09% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 71 0.08% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5013 5.82% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50368-50375 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51264-51271 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86114 # Bytes accessed per row activation +system.physmem.totQLat 365610387500 # Total ticks spent queuing +system.physmem.totMemAccLat 458189280000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17286802500 # Total ticks spent accessing banks +system.physmem.avgQLat 24279.47 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1147.98 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30427.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.00 # Data bus utilization in percentage +system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 12.84 # Average write queue length when enqueuing +system.physmem.readRowHits 14986740 # Number of row buffer hits during reads +system.physmem.writeRowHits 93410 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 86.60 # Row buffer hit rate for writes +system.physmem.avgGap 158714.15 # Average gap between requests +system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.73 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -440,50 +752,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54917647 # Throughput (bytes/s) +system.membus.throughput 54899945 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 16149440 # Transaction distribution system.membus.trans_dist::ReadResp 16149440 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59118 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution -system.membus.trans_dist::ReadExReq 131433 # Transaction distribution -system.membus.trans_dist::ReadExResp 131433 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 59125 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution +system.membus.trans_dist::ReadExReq 131442 # Transaction distribution +system.membus.trans_dist::ReadExResp 131442 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885779 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272485 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34156901 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694552 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092441 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138629141 # Total data (bytes) +system.membus.tot_pkt_size::total 138630105 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138630105 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486773500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3686000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17363455000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4733701508 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33738367951 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -491,13 +803,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48301509 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution -system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution +system.iobus.throughput 48285606 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution +system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution system.iobus.trans_dist::WriteResp 8157 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -519,12 +831,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32267358 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -546,14 +858,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390301 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121927961 # Total data (bytes) +system.iobus.tot_pkt_size::total 121927965 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121927965 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -599,41 +911,41 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921194049 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14390442 # Number of BP lookups -system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits +system.cpu.branchPred.lookups 14384905 # Number of BP lookups +system.cpu.branchPred.condPredicted 11471084 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 703956 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9467627 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7657685 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.882834 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1397242 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72494 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14986742 # DTB read hits -system.cpu.checker.dtb.read_misses 7308 # DTB read misses -system.cpu.checker.dtb.write_hits 11227334 # DTB write hits -system.cpu.checker.dtb.write_misses 2189 # DTB write misses +system.cpu.checker.dtb.read_hits 14986852 # DTB read hits +system.cpu.checker.dtb.read_misses 7306 # DTB read misses +system.cpu.checker.dtb.write_hits 11227410 # DTB write hits +system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 6418 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 179 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994050 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229523 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994158 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229601 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26214076 # DTB hits +system.cpu.checker.dtb.hits 26214262 # DTB hits system.cpu.checker.dtb.misses 9497 # DTB misses -system.cpu.checker.dtb.accesses 26223573 # DTB accesses -system.cpu.checker.itb.inst_hits 61479547 # ITB inst hits +system.cpu.checker.dtb.accesses 26223759 # DTB accesses +system.cpu.checker.itb.inst_hits 61479743 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -650,36 +962,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61484018 # ITB inst accesses -system.cpu.checker.itb.hits 61479547 # DTB hits +system.cpu.checker.itb.inst_accesses 61484214 # ITB inst accesses +system.cpu.checker.itb.hits 61479743 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61484018 # DTB accesses -system.cpu.checker.numCycles 77882185 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61484214 # DTB accesses +system.cpu.checker.numCycles 77882535 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51188083 # DTB read hits -system.cpu.dtb.read_misses 64353 # DTB read misses -system.cpu.dtb.write_hits 11697459 # DTB write hits -system.cpu.dtb.write_misses 15788 # DTB write misses +system.cpu.dtb.read_hits 51179212 # DTB read hits +system.cpu.dtb.read_misses 64531 # DTB read misses +system.cpu.dtb.write_hits 11698539 # DTB write hits +system.cpu.dtb.write_misses 15837 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6547 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6568 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2411 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51252436 # DTB read accesses -system.cpu.dtb.write_accesses 11713247 # DTB write accesses +system.cpu.dtb.perms_faults 1396 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51243743 # DTB read accesses +system.cpu.dtb.write_accesses 11714376 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62885542 # DTB hits -system.cpu.dtb.misses 80141 # DTB misses -system.cpu.dtb.accesses 62965683 # DTB accesses -system.cpu.itb.inst_hits 11520428 # ITB inst hits -system.cpu.itb.inst_misses 11439 # ITB inst misses +system.cpu.dtb.hits 62877751 # DTB hits +system.cpu.dtb.misses 80368 # DTB misses +system.cpu.dtb.accesses 62958119 # DTB accesses +system.cpu.itb.inst_hits 11513998 # ITB inst hits +system.cpu.itb.inst_misses 11344 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -688,114 +1000,114 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4968 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4962 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2968 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11531867 # ITB inst accesses -system.cpu.itb.hits 11520428 # DTB hits -system.cpu.itb.misses 11439 # DTB misses -system.cpu.itb.accesses 11531867 # DTB accesses -system.cpu.numCycles 473080437 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11525342 # ITB inst accesses +system.cpu.itb.hits 11513998 # DTB hits +system.cpu.itb.misses 11344 # DTB misses +system.cpu.itb.accesses 11525342 # DTB accesses +system.cpu.numCycles 474882944 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29745457 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90266235 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14384905 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9054927 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20140969 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4652912 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 123687 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96003967 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87891 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2685420 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11510536 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 707949 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5425 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.740543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.094686 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131871277 86.76% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1302073 0.86% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1710886 1.13% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295409 1.51% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2102442 1.38% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107607 0.73% 92.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555872 1.68% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 743971 0.49% 94.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307413 5.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432104229 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10389 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.532969 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.190081 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31502209 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98125273 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18366247 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 966197 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3037024 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1956644 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171990 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107262918 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568386 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3037024 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33252800 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39466554 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52672825 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17523888 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6043859 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102275198 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20557 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4063584 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106014240 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466907038 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432047963 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10635 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387438 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27626801 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830029 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736499 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12184256 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19715159 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13304037 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1977063 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2478152 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95106473 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1982467 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122897190 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166901 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18919534 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47250176 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500160 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151996950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.808550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.527901 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2809227 1.87% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127944 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108284402 71.24% 71.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13439431 8.84% 80.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6944257 4.57% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5857722 3.85% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12372410 8.14% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2808060 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1695891 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467423 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127354 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151996950 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62444 0.71% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available @@ -823,13 +1135,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8371933 94.63% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412257 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57615534 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93100 0.08% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued @@ -842,397 +1154,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 33 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 25 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2115 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 25 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52504661 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12318028 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued -system.cpu.iq.rate 0.259812 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122897190 # Type of FU issued +system.cpu.iq.rate 0.258795 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8846641 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071984 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406861293 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116024937 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85463742 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23592 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12620 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10347 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131367569 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12596 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623590 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4061151 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6344 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30249 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1572309 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107765 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 681284 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3037024 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30702730 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434457 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97310809 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203906 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19715159 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13304037 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1409970 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113496 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3538 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30249 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349429 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269322 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 618751 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120821579 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51866256 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2075611 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221034 # number of nop insts executed -system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed -system.cpu.iew.exec_branches 11474602 # Number of branches executed -system.cpu.iew.exec_stores 12209197 # Number of stores executed -system.cpu.iew.exec_rate 0.255417 # Inst execution rate -system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47030253 # num instructions producing a value -system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value +system.cpu.iew.exec_nop 221869 # number of nop insts executed +system.cpu.iew.exec_refs 64076774 # number of memory reference insts executed +system.cpu.iew.exec_branches 11475076 # Number of branches executed +system.cpu.iew.exec_stores 12210518 # Number of stores executed +system.cpu.iew.exec_rate 0.254424 # Inst execution rate +system.cpu.iew.wb_sent 119883669 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85474089 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47026181 # num instructions producing a value +system.cpu.iew.wb_consumers 87876552 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179990 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535139 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18658160 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534513 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148959926 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.510472 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121529130 81.59% 81.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13302723 8.93% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3899356 2.62% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2115942 1.42% 94.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1939571 1.30% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 978607 0.66% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1596110 1.07% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718014 0.48% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2880473 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60455941 # Number of instructions committed -system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148959926 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456137 # Number of instructions committed +system.cpu.commit.committedOps 77747122 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385481 # Number of memory references committed -system.cpu.commit.loads 15653838 # Number of loads committed -system.cpu.commit.membars 403568 # Number of memory barriers committed -system.cpu.commit.branches 9961054 # Number of branches committed +system.cpu.commit.refs 27385736 # Number of memory references committed +system.cpu.commit.loads 15654008 # Number of loads committed +system.cpu.commit.membars 403573 # Number of memory barriers committed +system.cpu.commit.branches 9961077 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852229 # Number of committed integer instructions. -system.cpu.commit.function_calls 991205 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852562 # Number of committed integer instructions. +system.cpu.commit.function_calls 991208 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2880473 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 239241509 # The number of ROB reads -system.cpu.rob.rob_writes 195965670 # The number of ROB writes -system.cpu.timesIdled 1778644 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322490663 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575455632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305560 # Number of Instructions Simulated -system.cpu.committedOps 77596391 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305560 # Number of Instructions Simulated -system.cpu.cpi 7.844723 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.844723 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127474 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127474 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547265504 # number of integer regfile reads -system.cpu.int_regfile_writes 87536110 # number of integer regfile writes -system.cpu.fp_regfile_reads 8349 # number of floating regfile reads -system.cpu.fp_regfile_writes 2916 # number of floating regfile writes -system.cpu.misc_regfile_reads 30123194 # number of misc regfile reads -system.cpu.misc_regfile_writes 831835 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58892076 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2657368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2657367 # Transaction distribution +system.cpu.rob.rob_reads 240636318 # The number of ROB reads +system.cpu.rob.rob_writes 195934369 # The number of ROB writes +system.cpu.timesIdled 1776906 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322885994 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575316115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305756 # Number of Instructions Simulated +system.cpu.committedOps 77596741 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305756 # Number of Instructions Simulated +system.cpu.cpi 7.874587 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.874587 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126991 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126991 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547208472 # number of integer regfile reads +system.cpu.int_regfile_writes 87526189 # number of integer regfile writes +system.cpu.fp_regfile_reads 8624 # number of floating regfile reads +system.cpu.fp_regfile_writes 3008 # number of floating regfile writes +system.cpu.misc_regfile_reads 30165107 # number of misc regfile reads +system.cpu.misc_regfile_writes 831837 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58889875 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658094 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658093 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607699 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246095 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246095 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959479 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796858 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30970 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7914210 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62665920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85541397 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42108 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148459049 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148459049 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 202780 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128672900 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246142 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246142 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961671 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796233 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31091 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128199 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7917194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62737088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85515993 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148510785 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148510785 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 194456 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128799181 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1473318251 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474440753 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2559248308 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550199081 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20450735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20321978 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74607301 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74655295 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 979660 # number of replacements -system.cpu.icache.tags.tagsinuse 511.583533 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10456897 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 980172 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.668431 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6854161250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.583533 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999187 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999187 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10456897 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10456897 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10456897 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10456897 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10456897 # number of overall hits -system.cpu.icache.overall_hits::total 10456897 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059959 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059959 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059959 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059959 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059959 # number of overall misses -system.cpu.icache.overall_misses::total 1059959 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14263664434 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14263664434 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14263664434 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14263664434 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14263664434 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14263664434 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11516856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11516856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11516856 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11516856 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11516856 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11516856 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092035 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092035 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092035 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092035 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092035 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092035 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13456.807701 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13456.807701 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13456.807701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13456.807701 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7134 # number of cycles access was blocked +system.cpu.icache.tags.replacements 980741 # number of replacements +system.cpu.icache.tags.tagsinuse 511.579116 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10449649 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981253 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.649291 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.579116 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10449649 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10449649 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10449649 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10449649 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10449649 # number of overall hits +system.cpu.icache.overall_hits::total 10449649 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060761 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060761 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060761 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060761 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060761 # number of overall misses +system.cpu.icache.overall_misses::total 1060761 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273214680 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14273214680 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14273214680 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14273214680 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14273214680 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14273214680 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11510410 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11510410 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11510410 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11510410 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11510410 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11510410 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092157 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092157 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092157 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092157 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092157 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092157 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13455.636736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13455.636736 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6677 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 370 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 323 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.281081 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.671827 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79754 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79754 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79754 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79754 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79754 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79754 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980205 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980205 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980205 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980205 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980205 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980205 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11579661493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11579661493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11579661493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11579661493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11579661493 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11579661493 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8708000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8708000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8708000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8708000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085110 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085110 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085110 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11813.509922 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11813.509922 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79476 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79476 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79476 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79476 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79476 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79476 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981285 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981285 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981285 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981285 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981285 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981285 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587356987 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11587356987 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587356987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11587356987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587356987 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11587356987 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8658250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8658250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8658250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8658250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085252 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085252 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085252 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.350262 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.350262 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64363 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51374.109919 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1885226 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129755 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.529120 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2489241302000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36927.111680 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 38.632288 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000370 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.183198 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.182382 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563463 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000589 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 64371 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51366.694603 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1888244 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129769 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.550810 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2490009951000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36925.668640 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 27.934134 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.003945 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.587712 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6237.500172 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563441 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124713 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.095141 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.783907 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52355 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10525 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 966696 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387308 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1416884 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607864 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607864 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.095177 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.783794 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53605 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10777 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 967799 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387031 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1419212 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607699 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607699 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112905 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112905 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52355 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10525 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 966696 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 500213 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1529789 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52355 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10525 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 966696 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 500213 # number of overall hits -system.cpu.l2cache.overall_hits::total 1529789 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 51 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12341 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10723 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23117 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2916 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2916 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133190 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133190 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 51 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12341 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143913 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156307 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 51 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12341 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143913 # number of overall misses -system.cpu.l2cache.overall_misses::total 156307 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4640000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 130250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 910966750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 788627999 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1704364999 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395483 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 395483 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9130512743 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9130512743 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4640000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 130250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 910966750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9919140742 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10834877742 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4640000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 130250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 910966750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9919140742 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10834877742 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52406 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10527 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979037 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 398031 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1440001 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607864 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607864 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 112944 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112944 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 53605 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10777 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 967799 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 499975 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1532156 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 53605 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10777 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 967799 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 499975 # number of overall hits +system.cpu.l2cache.overall_hits::total 1532156 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12350 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10721 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23115 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2915 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2915 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133198 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133198 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12350 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143919 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156313 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 12350 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143919 # number of overall misses +system.cpu.l2cache.overall_misses::total 156313 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3352500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 233000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 906466500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 812441248 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1722493248 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 465980 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 465980 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10117185994 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10117185994 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3352500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 233000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 906466500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10929627242 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11839679242 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3352500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 233000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 906466500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10929627242 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11839679242 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53646 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10780 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 980149 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397752 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1442327 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607699 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607699 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2955 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2955 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 11 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246095 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246095 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52406 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10527 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 979037 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 644126 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1686096 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52406 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10527 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979037 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 644126 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1686096 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000973 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012605 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026940 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016053 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986802 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986802 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.181818 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.181818 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541214 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541214 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000973 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012605 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223424 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092703 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000973 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012605 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223424 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092703 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 90980.392157 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65125 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73816.283121 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73545.462930 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73727.776052 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 135.625171 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 135.625171 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68552.539553 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68552.539553 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69317.930368 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69317.930368 # average overall miss latency +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246142 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246142 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53646 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10780 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 980149 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643894 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1688469 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53646 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10780 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 980149 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643894 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1688469 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000764 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000278 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012600 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026954 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016026 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986464 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986464 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541143 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541143 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000764 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000278 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012600 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223513 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092577 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000764 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000278 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012600 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223513 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092577 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81768.292683 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77666.666667 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73398.097166 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75780.360787 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74518.418689 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.855918 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.855918 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75955.990285 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75955.990285 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75743.407407 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75743.407407 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1241,109 +1553,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59118 # number of writebacks -system.cpu.l2cache.writebacks::total 59118 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 59125 # number of writebacks +system.cpu.l2cache.writebacks::total 59125 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 51 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12329 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10658 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23040 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2916 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2916 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133190 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133190 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 51 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12329 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143848 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156230 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 51 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12329 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143848 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156230 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3990500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 105750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 754066500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 649417249 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1407579999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29164415 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29164415 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7443119257 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7443119257 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3990500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 105750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 754066500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8092536506 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8850699256 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3990500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 105750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 754066500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8092536506 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8850699256 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6234999 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166923461500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166929696499 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17446167056 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17446167056 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6234999 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184369628556 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184375863555 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026777 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016000 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986802 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986802 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.181818 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541214 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541214 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092658 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092658 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52875 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61162.016384 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60932.374648 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61092.881901 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.514060 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.514060 # average UpgradeReq mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12339 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23039 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2915 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2915 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133198 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133198 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12339 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143854 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156237 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12339 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143854 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156237 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2846500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 196000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 750549750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 675500748 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1429092998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29153914 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29153914 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8456317006 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8456317006 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2846500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 196000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 750549750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9131817754 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9885410004 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2846500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 196000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 750549750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9131817754 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9885410004 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6187249 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166934965500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941152749 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17442637817 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17442637817 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6187249 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377603317 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383790566 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026791 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015973 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986464 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986464 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541143 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541143 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092532 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092532 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.437394 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63391.586712 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62029.298060 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55883.469157 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55883.469157 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63486.816664 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63486.816664 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1353,161 +1665,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643614 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993425 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21512206 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 644126 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.397512 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 41599250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993425 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 643382 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21503755 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643894 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.396421 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13760275 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13760275 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258497 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258497 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242759 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242759 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247596 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247596 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21018772 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21018772 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21018772 # number of overall hits -system.cpu.dcache.overall_hits::total 21018772 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737490 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737490 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963456 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963456 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700946 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700946 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700946 # number of overall misses -system.cpu.dcache.overall_misses::total 3700946 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9976636292 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9976636292 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 134760113834 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 134760113834 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184874750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 184874750 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 168002 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 168002 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144736750126 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144736750126 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144736750126 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144736750126 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14497765 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14497765 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10221953 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10221953 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256268 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 13751955 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13751955 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258296 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258296 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242828 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242828 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21010251 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21010251 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21010251 # number of overall hits +system.cpu.dcache.overall_hits::total 21010251 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737736 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737736 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963735 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963735 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13555 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13555 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3701471 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3701471 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3701471 # number of overall misses +system.cpu.dcache.overall_misses::total 3701471 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10012711310 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10012711310 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 141368125836 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 141368125836 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185715250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185715250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 151380837146 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 151380837146 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 151380837146 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 151380837146 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14489691 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14489691 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222031 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222031 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256383 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256383 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24719718 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24719718 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24719718 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24719718 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050869 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050869 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289911 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289911 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052714 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052714 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149716 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149716 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149716 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149716 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13527.825858 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13527.825858 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45473.971550 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45473.971550 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.302391 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.302391 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15272.909091 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15272.909091 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39108.041600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39108.041600 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 31555 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 26598 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2653 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.894082 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 95.333333 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 24711722 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24711722 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24711722 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24711722 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050915 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050915 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289936 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289936 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052870 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052870 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149786 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149786 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149786 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149786 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13572.214600 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40897.480257 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40897.480257 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33174 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2643 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.551646 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 96.491228 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607864 # number of writebacks -system.cpu.dcache.writebacks::total 607864 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351528 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351528 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714505 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714505 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3066033 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3066033 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3066033 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3066033 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385962 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385962 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248951 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248951 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12168 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12168 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634913 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634913 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634913 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634913 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4950861635 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4950861635 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10610319031 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10610319031 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144937500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144937500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 145998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 145998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15561180666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15561180666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15561180666 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15561180666 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182316666500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182316666500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26837116532 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26837116532 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209153783032 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209153783032 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026622 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047482 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047482 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025684 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025684 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12827.329206 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12827.329206 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42620.110106 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42620.110106 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11911.365878 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.365878 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607699 # number of writebacks +system.cpu.dcache.writebacks::total 607699 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 352116 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 352116 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714717 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714717 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3066833 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3066833 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3066833 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3066833 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385620 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385620 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249018 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249018 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4970319128 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4970319128 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11601864538 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11601864538 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572183666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16572183666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572183666 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16572183666 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328180000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328180000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841518267 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841518267 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169698267 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169698267 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024361 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024361 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047628 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047628 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1529,10 +1841,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499087755049 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 99b249a14..22f0dd0ff 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,154 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.104038 # Number of seconds simulated -sim_ticks 1104038330000 # Number of ticks simulated -final_tick 1104038330000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.104766 # Number of seconds simulated +sim_ticks 1104765949000 # Number of ticks simulated +final_tick 1104765949000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65967 # Simulator instruction rate (inst/s) -host_op_rate 84921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1182267512 # Simulator tick rate (ticks/s) -host_mem_usage 404512 # Number of bytes of host memory used -host_seconds 933.83 # Real time elapsed on the host -sim_insts 61602211 # Number of instructions simulated -sim_ops 79302243 # Number of ops (including micro ops) simulated +host_inst_rate 62642 # Simulator instruction rate (inst/s) +host_op_rate 80640 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1123477436 # Simulator tick rate (ticks/s) +host_mem_usage 430892 # Number of bytes of host memory used +host_seconds 983.35 # Real time elapsed on the host +sim_insts 61598253 # Number of instructions simulated +sim_ops 79296895 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 410368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4366772 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 405824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5250416 # Number of bytes read from this memory -system.physmem.bytes_read::total 59194084 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 410368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 405824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 816192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267200 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 408192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4366132 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 406848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5251248 # Number of bytes read from this memory +system.physmem.bytes_read::total 59192932 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 408192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 406848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4268480 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7294544 # Number of bytes written to this memory +system.physmem.bytes_written::total 7295824 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6412 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82064 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257998 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66675 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6378 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68293 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6357 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82077 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257980 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66695 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823511 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44164032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 696 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823531 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44134945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 371697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3955272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 367581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4755646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53615968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 371697 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 367581 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 739279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3865083 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 15398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2726666 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6607147 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3865083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44164032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 369483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3952088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 368266 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4753267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53579613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 369483 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 368266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 737749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3863696 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 15388 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2724870 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6603954 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3863696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44134945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 371697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3970670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 367581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7482313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60223116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257998 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 823511 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 6257998 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 823511 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 400511872 # Total number of bytes read from memory -system.physmem.bytesWritten 52704704 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59194084 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7294544 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 4191 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 12574 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391107 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391051 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 391031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 390511 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391821 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 391470 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 391242 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 390250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391441 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 391418 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390570 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 389084 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 390982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 391146 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 389937 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7175 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7210 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7320 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7294 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7815 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7419 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7389 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7204 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7511 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7529 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6626 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6832 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7294 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7205 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1104037196000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 105 # Categorize read packet sizes -system.physmem.readPktSize::3 6094848 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163045 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 756836 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66675 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 510579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 438231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 410611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1497375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1129368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1114937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1085131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 10318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7846 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 12945 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 12334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.bw_total::cpu0.inst 369483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3967476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 368266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7478138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60183567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257980 # Number of read requests accepted +system.physmem.writeReqs 823531 # Number of write requests accepted +system.physmem.readBursts 6257980 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 823531 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 398200448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2310272 # Total number of bytes read from write queue +system.physmem.bytesWritten 7402624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 59192932 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7295824 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 36098 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707850 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12605 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 391110 # Per bank write bursts +system.physmem.perBankRdBursts::1 390863 # Per bank write bursts +system.physmem.perBankRdBursts::2 386866 # Per bank write bursts +system.physmem.perBankRdBursts::3 386878 # Per bank write bursts +system.physmem.perBankRdBursts::4 391778 # Per bank write bursts +system.physmem.perBankRdBursts::5 391417 # Per bank write bursts +system.physmem.perBankRdBursts::6 386925 # Per bank write bursts +system.physmem.perBankRdBursts::7 386783 # Per bank write bursts +system.physmem.perBankRdBursts::8 391442 # Per bank write bursts +system.physmem.perBankRdBursts::9 391216 # Per bank write bursts +system.physmem.perBankRdBursts::10 386574 # Per bank write bursts +system.physmem.perBankRdBursts::11 385570 # Per bank write bursts +system.physmem.perBankRdBursts::12 390981 # Per bank write bursts +system.physmem.perBankRdBursts::13 390596 # Per bank write bursts +system.physmem.perBankRdBursts::14 386700 # Per bank write bursts +system.physmem.perBankRdBursts::15 386183 # Per bank write bursts +system.physmem.perBankWrBursts::0 7188 # Per bank write bursts +system.physmem.perBankWrBursts::1 7193 # Per bank write bursts +system.physmem.perBankWrBursts::2 7297 # Per bank write bursts +system.physmem.perBankWrBursts::3 7231 # Per bank write bursts +system.physmem.perBankWrBursts::4 7835 # Per bank write bursts +system.physmem.perBankWrBursts::5 7450 # Per bank write bursts +system.physmem.perBankWrBursts::6 7370 # Per bank write bursts +system.physmem.perBankWrBursts::7 7176 # Per bank write bursts +system.physmem.perBankWrBursts::8 7508 # Per bank write bursts +system.physmem.perBankWrBursts::9 7517 # Per bank write bursts +system.physmem.perBankWrBursts::10 6849 # Per bank write bursts +system.physmem.perBankWrBursts::11 6596 # Per bank write bursts +system.physmem.perBankWrBursts::12 7160 # Per bank write bursts +system.physmem.perBankWrBursts::13 6824 # Per bank write bursts +system.physmem.perBankWrBursts::14 7287 # Per bank write bursts +system.physmem.perBankWrBursts::15 7185 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1104764856500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 105 # Read request sizes (log2) +system.physmem.readPktSize::3 6094848 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 163027 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 756836 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66695 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 548369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 494073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 445478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1468713 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1058783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1047686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1043195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 25416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9815 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,312 +159,563 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 35262 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11560.822642 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 608.575977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 24356.197009 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-79 8749 24.81% 24.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-143 4356 12.35% 37.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-207 2652 7.52% 44.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-271 2010 5.70% 50.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-335 1437 4.08% 54.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-399 1214 3.44% 57.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-463 927 2.63% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-527 1120 3.18% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-591 659 1.87% 65.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-655 617 1.75% 67.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-719 450 1.28% 68.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-783 454 1.29% 69.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-847 302 0.86% 70.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-911 302 0.86% 71.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-975 179 0.51% 72.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1039 219 0.62% 72.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1103 133 0.38% 73.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1167 156 0.44% 73.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1231 97 0.28% 73.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1295 134 0.38% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1359 73 0.21% 74.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1423 395 1.12% 75.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1487 262 0.74% 76.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1551 538 1.53% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1615 109 0.31% 78.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1679 178 0.50% 78.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1743 51 0.14% 78.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1807 128 0.36% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1871 49 0.14% 79.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1935 68 0.19% 79.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1999 39 0.11% 79.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2063 74 0.21% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2127 17 0.05% 79.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2191 56 0.16% 79.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2255 22 0.06% 80.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2319 30 0.09% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2383 13 0.04% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2447 29 0.08% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2511 10 0.03% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2575 19 0.05% 80.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2639 9 0.03% 80.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2703 17 0.05% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2767 7 0.02% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2831 14 0.04% 80.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2895 6 0.02% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2959 10 0.03% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3023 4 0.01% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3087 17 0.05% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3151 3 0.01% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3215 15 0.04% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3279 4 0.01% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3343 7 0.02% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3407 9 0.03% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3471 11 0.03% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3535 3 0.01% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3599 7 0.02% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3663 3 0.01% 80.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3727 11 0.03% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3791 3 0.01% 80.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3855 4 0.01% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3919 5 0.01% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3983 13 0.04% 80.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4047 3 0.01% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4111 28 0.08% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4175 4 0.01% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4239 7 0.02% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4303 4 0.01% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4367 3 0.01% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4431 1 0.00% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4495 6 0.02% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4559 4 0.01% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4623 2 0.01% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4687 1 0.00% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4751 1 0.00% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4815 6 0.02% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4879 4 0.01% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4943 5 0.01% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5007 3 0.01% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5135 4 0.01% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5199 4 0.01% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5263 2 0.01% 81.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5327 1 0.00% 81.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5391 5 0.01% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5455 1 0.00% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5519 1 0.00% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5583 4 0.01% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5647 3 0.01% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5711 1 0.00% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5775 4 0.01% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5839 1 0.00% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5903 2 0.01% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6031 2 0.01% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6095 1 0.00% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6159 2 0.01% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6223 3 0.01% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6287 2 0.01% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6351 3 0.01% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6415 1 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6479 3 0.01% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6543 1 0.00% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6671 2 0.01% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6735 2 0.01% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6799 16 0.05% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6863 3 0.01% 81.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6927 5 0.01% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6991 3 0.01% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7055 1 0.00% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7183 8 0.02% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7247 1 0.00% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7311 1 0.00% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7439 3 0.01% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7567 5 0.01% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7631 2 0.01% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7695 3 0.01% 81.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7759 2 0.01% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7823 1 0.00% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7887 4 0.01% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7951 6 0.02% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8015 1 0.00% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8079 7 0.02% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8143 5 0.01% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8207 318 0.90% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8399 1 0.00% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8463 41 0.12% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8527 122 0.35% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8591 8 0.02% 82.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8719 1 0.00% 82.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8783 3 0.01% 82.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9231 3 0.01% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9487 1 0.00% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9743 2 0.01% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9999 1 0.00% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10255 2 0.01% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10767 2 0.01% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11023 1 0.00% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11279 2 0.01% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11535 2 0.01% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12047 2 0.01% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12303 1 0.00% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12751 1 0.00% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13071 1 0.00% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13583 1 0.00% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13839 1 0.00% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14351 1 0.00% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14607 1 0.00% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15375 2 0.01% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15631 1 0.00% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16399 2 0.01% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16527 1 0.00% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17423 3 0.01% 82.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17679 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17935 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18447 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18880-18895 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19136-19151 1 0.00% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19215 1 0.00% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19727 1 0.00% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19904-19919 1 0.00% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20239 1 0.00% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20495 2 0.01% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20928-20943 1 0.00% 82.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21007 2 0.01% 82.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21327 1 0.00% 83.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21519 2 0.01% 83.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22031 1 0.00% 83.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22543 3 0.01% 83.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23567 1 0.00% 83.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23823 1 0.00% 83.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24128-24143 1 0.00% 83.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24591 4 0.01% 83.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24847 1 0.00% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25024-25039 1 0.00% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25103 1 0.00% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25359 1 0.00% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26319 1 0.00% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26383 1 0.00% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26639 1 0.00% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26688-26703 1 0.00% 83.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27200-27215 1 0.00% 83.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27407 1 0.00% 83.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27663 2 0.01% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-27983 1 0.00% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28096-28111 1 0.00% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28687 3 0.01% 83.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29455 1 0.00% 83.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29711 1 0.00% 83.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29967 3 0.01% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30400-30415 1 0.00% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30479 1 0.00% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30735 1 0.00% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31247 2 0.01% 83.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31759 3 0.01% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32015 1 0.00% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32271 1 0.00% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32527 1 0.00% 83.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32640-32655 1 0.00% 83.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32783 2 0.01% 83.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32911 1 0.00% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33039 1 0.00% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33295 1 0.00% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33551 9 0.03% 83.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33615 9 0.03% 83.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33679 3 0.01% 83.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33743 3 0.01% 83.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33807 23 0.07% 83.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36879 1 0.00% 83.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37568-37583 1 0.00% 83.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37903 2 0.01% 83.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39247 1 0.00% 83.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39695 1 0.00% 83.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42767 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43535 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44239 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44559 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45583 1 0.00% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46400-46415 1 0.00% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46863 1 0.00% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47119 1 0.00% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47247 1 0.00% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47311 1 0.00% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47424-47439 1 0.00% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47887 1 0.00% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48143 2 0.01% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48320-48335 2 0.01% 83.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49039 1 0.00% 83.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49600-49615 1 0.00% 83.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49935 1 0.00% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52864-52879 1 0.00% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53504-53519 1 0.00% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54287 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54464-54479 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54784-54799 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58383 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60160-60175 1 0.00% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60672-60687 1 0.00% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60928-60943 1 0.00% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64527 1 0.00% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65039 10 0.03% 83.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65408-65423 6 0.02% 83.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65551 5666 16.07% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::68672-68687 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::69120-69135 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::72128-72143 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73088-73103 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73920-73935 20 0.06% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-73999 91 0.26% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74048-74063 61 0.17% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74112-74127 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 35262 # Bytes accessed per row activation -system.physmem.totQLat 121597245250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 160506894000 # Sum of mem lat for all requests -system.physmem.totBusLat 31269035000 # Total cycles spent in databus access -system.physmem.totBankLat 7640613750 # Total cycles spent in bank access -system.physmem.avgQLat 19443.72 # Average queueing delay per request -system.physmem.avgBankLat 1221.75 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25665.47 # Average memory access latency -system.physmem.avgRdBW 362.77 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 47.74 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.62 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.21 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 12.74 # Average write queue length over time -system.physmem.readRowHits 6235456 # Number of row buffer hits during reads -system.physmem.writeRowHits 98940 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 12.01 # Row buffer hit rate for writes -system.physmem.avgGap 155904.23 # Average gap between requests +system.physmem.bytesPerActivate::samples 71125 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5702.673097 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 368.783347 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 12967.835637 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 25909 36.43% 36.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14850 20.88% 57.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3162 4.45% 61.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2234 3.14% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1545 2.17% 67.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1302 1.83% 68.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 996 1.40% 70.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1191 1.67% 71.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 629 0.88% 72.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 663 0.93% 73.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 567 0.80% 74.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 536 0.75% 75.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 288 0.40% 75.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 263 0.37% 76.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 175 0.25% 76.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 373 0.52% 76.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 125 0.18% 77.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 132 0.19% 77.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 91 0.13% 77.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 197 0.28% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 57 0.08% 77.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 541 0.76% 78.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 41 0.06% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 225 0.32% 78.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 27 0.04% 78.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 110 0.15% 79.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 22 0.03% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 111 0.16% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 16 0.02% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 61 0.09% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 13 0.02% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 267 0.38% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 16 0.02% 79.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 40 0.06% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 17 0.02% 79.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 50 0.07% 79.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 11 0.02% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 22 0.03% 79.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 7 0.01% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 43 0.06% 80.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 4 0.01% 80.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 15 0.02% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 8 0.01% 80.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 32 0.04% 80.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 7 0.01% 80.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 30 0.04% 80.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 5 0.01% 80.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 157 0.22% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 6 0.01% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 17 0.02% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 2 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 36 0.05% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 9 0.01% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 17 0.02% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 7 0.01% 80.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 88 0.12% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 7 0.01% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 27 0.04% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 8 0.01% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 39 0.05% 80.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 6 0.01% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 18 0.03% 80.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 181 0.25% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 9 0.01% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 12 0.02% 81.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 12 0.02% 81.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 102 0.14% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 17 0.02% 81.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 25 0.04% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 7 0.01% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 11 0.02% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 5 0.01% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 10 0.01% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 19 0.03% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 2 0.00% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 6 0.01% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 5 0.01% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 161 0.23% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 13 0.02% 81.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 9 0.01% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 14 0.02% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 3 0.00% 81.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 16 0.02% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.00% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 18 0.03% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 5 0.01% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 8 0.01% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 5 0.01% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 150 0.21% 81.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 2 0.00% 81.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 12 0.02% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 13 0.02% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 95 0.13% 82.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 7 0.01% 82.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 6 0.01% 82.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 23 0.03% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 4 0.01% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 11 0.02% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 3 0.00% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 112 0.16% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 9 0.01% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 20 0.03% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 8 0.01% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 28 0.04% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 5 0.01% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 4 0.01% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 2 0.00% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 94 0.13% 82.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 6 0.01% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 10 0.01% 82.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 92 0.13% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 3 0.00% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 10 0.01% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 3 0.00% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 20 0.03% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 2 0.00% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 2 0.00% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 4 0.01% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 30 0.04% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 6 0.01% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 8 0.01% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8135 1 0.00% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 249 0.35% 83.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 83.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 31 0.04% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8647 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 16 0.02% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 3 0.00% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8903 1 0.00% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 75 0.11% 83.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 1 0.00% 83.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 93 0.13% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9415 1 0.00% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 20 0.03% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 1 0.00% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 102 0.14% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 14 0.02% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 3 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 94 0.13% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 94 0.13% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 15 0.02% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10823 1 0.00% 84.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10887 1 0.00% 84.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 6 0.01% 84.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11079 2 0.00% 84.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 1 0.00% 84.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 147 0.21% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11335 3 0.00% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 15 0.02% 84.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 1 0.00% 84.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 1 0.00% 84.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11847 1 0.00% 84.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 79 0.11% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12103 1 0.00% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 162 0.23% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 20 0.03% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12743 1 0.00% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 68 0.10% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12935 1 0.00% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 20 0.03% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 148 0.21% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13447 1 0.00% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13511 1 0.00% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 19 0.03% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13703 1 0.00% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 18 0.03% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 11 0.02% 85.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 228 0.32% 85.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 27 0.04% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 14 0.02% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 1 0.00% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 1 0.00% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 73 0.10% 85.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15175 2 0.00% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 1 0.00% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 145 0.20% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 10 0.01% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15687 1 0.00% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15751 1 0.00% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 20 0.03% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 17 0.02% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 1 0.00% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16327 1 0.00% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 273 0.38% 86.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16455 1 0.00% 86.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16519 1 0.00% 86.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 20 0.03% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16711 1 0.00% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 21 0.03% 86.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 13 0.02% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 1 0.00% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17351 1 0.00% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 156 0.22% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 2 0.00% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 1 0.00% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 80 0.11% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 1 0.00% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17863 1 0.00% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 14 0.02% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 31 0.04% 86.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 2 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 1 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18375 1 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 219 0.31% 87.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 87.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 6 0.01% 87.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18752-18759 1 0.00% 87.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 15 0.02% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19008-19015 1 0.00% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 4 0.01% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 13 0.02% 87.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19264-19271 1 0.00% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 140 0.20% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19591 1 0.00% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19648-19655 1 0.00% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 17 0.02% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19840-19847 2 0.00% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 68 0.10% 87.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20032-20039 1 0.00% 87.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20103 1 0.00% 87.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 17 0.02% 87.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 2 0.00% 87.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 157 0.22% 87.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 82 0.12% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 4 0.01% 87.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 14 0.02% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 2 0.00% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21440-21447 2 0.00% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 145 0.20% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 1 0.00% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21696-21703 1 0.00% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 4 0.01% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21824-21831 1 0.00% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 14 0.02% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 2 0.00% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 92 0.13% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 1 0.00% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 2 0.00% 88.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 85 0.12% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 14 0.02% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 102 0.14% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23104-23111 2 0.00% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23232-23239 1 0.00% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 21 0.03% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23488-23495 1 0.00% 88.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 91 0.13% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23616-23623 1 0.00% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23744-23751 4 0.01% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 75 0.11% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23872-23879 2 0.00% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 1 0.00% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 21 0.03% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 31 0.04% 88.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24512-24519 1 0.00% 88.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 139 0.20% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24704-24711 1 0.00% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24775 1 0.00% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 29 0.04% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24896-24903 2 0.00% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 18 0.03% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25287 1 0.00% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 77 0.11% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 2 0.00% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 90 0.13% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 19 0.03% 89.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 104 0.15% 89.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 14 0.02% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 87 0.12% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26816-26823 2 0.00% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 94 0.13% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 1 0.00% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27264-27271 2 0.00% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27328-27335 1 0.00% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 5 0.01% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 1 0.00% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 143 0.20% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27776-27783 1 0.00% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 16 0.02% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 2 0.00% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 5 0.01% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28224-28231 2 0.00% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 82 0.12% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 1 0.00% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 1 0.00% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 157 0.22% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28743 2 0.00% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 1 0.00% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 1 0.00% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 22 0.03% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 2 0.00% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 67 0.09% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29376-29383 1 0.00% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 16 0.02% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 1 0.00% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 3 0.00% 90.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 139 0.20% 90.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 3 0.00% 90.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 13 0.02% 90.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30016-30023 1 0.00% 90.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30080-30087 2 0.00% 90.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 17 0.02% 90.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30279 4 0.01% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 11 0.02% 90.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30528-30535 2 0.00% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 213 0.30% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 2 0.00% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 2 0.00% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 26 0.04% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31040-31047 1 0.00% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31168-31175 1 0.00% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 17 0.02% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 1 0.00% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 70 0.10% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 147 0.21% 91.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31808-31815 1 0.00% 91.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 14 0.02% 91.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32064-32071 1 0.00% 91.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 91.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 20 0.03% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 2 0.00% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 14 0.02% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32647 1 0.00% 91.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32704-32711 1 0.00% 91.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 271 0.38% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 14 0.02% 91.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 20 0.03% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 1 0.00% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 20 0.03% 92.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 1 0.00% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 4 0.01% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33735 1 0.00% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 153 0.22% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33856-33863 1 0.00% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 71 0.10% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34112-34119 1 0.00% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34176-34183 1 0.00% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 15 0.02% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34368-34375 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 2 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 26 0.04% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34624-34631 2 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 211 0.30% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 7 0.01% 92.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 15 0.02% 92.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 1 0.00% 92.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 13 0.02% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 136 0.19% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 19 0.03% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36288-36295 1 0.00% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 67 0.09% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 1 0.00% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 18 0.03% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 1 0.00% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 155 0.22% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 79 0.11% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37312-37319 1 0.00% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 3 0.00% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37440-37447 1 0.00% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37568-37575 1 0.00% 93.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 12 0.02% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37696-37703 1 0.00% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 140 0.20% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 1 0.00% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 3 0.00% 93.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 13 0.02% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 93 0.13% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 85 0.12% 93.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 15 0.02% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39360-39367 2 0.00% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 104 0.15% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39616-39623 1 0.00% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 19 0.03% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 90 0.13% 94.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 75 0.11% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 16 0.02% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 2 0.00% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 30 0.04% 94.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40832-40839 1 0.00% 94.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 138 0.19% 94.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 29 0.04% 94.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41280-41287 1 0.00% 94.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 18 0.03% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41536-41543 1 0.00% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 1 0.00% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41664-41671 1 0.00% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 74 0.10% 94.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41792-41799 2 0.00% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41920-41927 2 0.00% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 90 0.13% 94.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42176-42183 1 0.00% 94.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 19 0.03% 94.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 98 0.14% 95.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 95.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 15 0.02% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42880-42887 2 0.00% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 82 0.12% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 95.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 90 0.13% 95.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43392-43399 1 0.00% 95.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43712-43719 1 0.00% 95.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 4 0.01% 95.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 144 0.20% 95.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 2 0.00% 95.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 12 0.02% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 2 0.00% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44480-44487 1 0.00% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 5 0.01% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 85 0.12% 95.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 155 0.22% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45120-45127 1 0.00% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 16 0.02% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 96.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45504-45511 2 0.00% 96.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 71 0.10% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45639 2 0.00% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45760-45767 1 0.00% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 19 0.03% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 1 0.00% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 138 0.19% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 14 0.02% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 15 0.02% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 10 0.01% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47040-47047 1 0.00% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 214 0.30% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 31 0.04% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 15 0.02% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47680-47687 1 0.00% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 70 0.10% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 146 0.21% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 10 0.01% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 20 0.03% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 13 0.02% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48832-48839 2 0.00% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 13 0.02% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 2 0.00% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 1979 2.78% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49792-49799 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50183 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50368-50375 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50759 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50880-50887 4 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50944-50951 3 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51328-51335 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51648-51655 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51719 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52352-52359 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52672-52679 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 71125 # Bytes accessed per row activation +system.physmem.totQLat 151840872500 # Total ticks spent queuing +system.physmem.totMemAccLat 191562815000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 31109410000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8612532500 # Total ticks spent accessing banks +system.physmem.avgQLat 24404.33 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1384.23 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30788.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 360.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.70 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 53.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.60 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.87 # Data bus utilization in percentage +system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.06 # Average write queue length when enqueuing +system.physmem.readRowHits 6168484 # Number of row buffer hits during reads +system.physmem.writeRowHits 97939 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.66 # Row buffer hit rate for writes +system.physmem.avgGap 156006.94 # Average gap between requests +system.physmem.pageHitRate 98.88 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 3.92 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -485,300 +734,286 @@ system.realview.nvmem.bw_inst_read::total 406 # I system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 62410733 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7306749 # Transaction distribution -system.membus.trans_dist::ReadResp 7306749 # Transaction distribution +system.membus.throughput 62369736 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7306752 # Transaction distribution +system.membus.trans_dist::ReadResp 7306752 # Transaction distribution system.membus.trans_dist::WriteReq 767894 # Transaction distribution system.membus.trans_dist::WriteResp 767894 # Transaction distribution -system.membus.trans_dist::Writeback 66675 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33869 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17715 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12574 # Transaction distribution -system.membus.trans_dist::ReadExReq 138085 # Transaction distribution -system.membus.trans_dist::ReadExResp 137703 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382522 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 66695 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33888 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17695 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12605 # Transaction distribution +system.membus.trans_dist::ReadExReq 138070 # Transaction distribution +system.membus.trans_dist::ReadExResp 137680 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382518 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11642 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971187 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4366211 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4366229 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16555907 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389789 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 16555925 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389781 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23284 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1684 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729844 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20145057 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729972 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20145177 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 68903841 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 68903841 # Total data (bytes) +system.membus.tot_pkt_size::total 68903961 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 68903961 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475612500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487006499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9865000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9880000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 750000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 749500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 8618805999 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 8612723499 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4854602214 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4837509170 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 13760099489 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 13760375954 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.tags.replacements 72758 # number of replacements -system.l2c.tags.tagsinuse 53808.125296 # Cycle average of tags in use -system.l2c.tags.total_refs 1836602 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 137939 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.314596 # Average number of references to valid blocks. +system.l2c.tags.replacements 72740 # number of replacements +system.l2c.tags.tagsinuse 53853.567584 # Cycle average of tags in use +system.l2c.tags.total_refs 1839137 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 137924 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.334423 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39514.415699 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.446892 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.257540 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4002.916228 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2827.365052 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 9.413975 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.918976 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3679.171285 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3769.219649 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.602942 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000068 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 39512.680536 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.162068 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.257969 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4009.847433 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2829.767621 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.955070 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3709.355619 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3778.541270 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.602916 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000079 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061080 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043142 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000144 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056140 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.057514 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.821047 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 21860 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4237 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386435 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166509 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30879 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4932 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 588366 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198248 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1401466 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581263 # number of Writeback hits -system.l2c.Writeback_hits::total 581263 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1335 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 743 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2078 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 202 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 141 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 343 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48314 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58639 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106953 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 21860 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4237 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386435 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214823 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30879 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4932 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 588366 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 256887 # number of demand (read+write) hits -system.l2c.demand_hits::total 1508419 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 21860 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4237 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386435 # number of overall hits -system.l2c.overall_hits::cpu0.data 214823 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30879 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4932 # number of overall hits -system.l2c.overall_hits::cpu1.inst 588366 # number of overall hits -system.l2c.overall_hits::cpu1.data 256887 # number of overall hits -system.l2c.overall_hits::total 1508419 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.061185 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043179 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000121 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.056600 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.057656 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.821740 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 22065 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4358 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 386342 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166614 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30647 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5089 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 590258 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 198399 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1403772 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581386 # number of Writeback hits +system.l2c.Writeback_hits::total 581386 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1334 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 750 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2084 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 137 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48317 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58643 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106960 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 22065 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4358 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 386342 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 214931 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30647 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5089 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 590258 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 257042 # number of demand (read+write) hits +system.l2c.demand_hits::total 1510732 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 22065 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4358 # number of overall hits +system.l2c.overall_hits::cpu0.inst 386342 # number of overall hits +system.l2c.overall_hits::cpu0.data 214931 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30647 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5089 # number of overall hits +system.l2c.overall_hits::cpu1.inst 590258 # number of overall hits +system.l2c.overall_hits::cpu1.data 257042 # number of overall hits +system.l2c.overall_hits::total 1510732 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6295 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6381 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6308 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6244 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25258 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5140 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3782 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8922 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 633 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 424 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1057 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63292 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 77006 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140298 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 6260 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6384 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6325 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6267 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25263 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5164 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3801 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8965 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 637 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 413 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1050 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63263 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 77007 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140270 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 13 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6295 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69673 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6308 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83250 # number of demand (read+write) misses -system.l2c.demand_misses::total 165556 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses +system.l2c.demand_misses::cpu0.inst 6260 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69647 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6325 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 83274 # number of demand (read+write) misses +system.l2c.demand_misses::total 165533 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 13 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6295 # number of overall misses -system.l2c.overall_misses::cpu0.data 69673 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6308 # number of overall misses -system.l2c.overall_misses::cpu1.data 83250 # number of overall misses -system.l2c.overall_misses::total 165556 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 956500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 219500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 459403500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 469850249 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1252250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 89250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 486933250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 475323500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1894027999 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 8999593 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12092485 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 21092078 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 513478 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3097867 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3611345 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4257399342 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5547277314 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9804676656 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 956500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 219500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 459403500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4727249591 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1252250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 89250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 486933250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6022600814 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11698704655 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 956500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 219500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 459403500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4727249591 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1252250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 89250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 486933250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6022600814 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11698704655 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 21872 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 4240 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 392730 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 172890 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30893 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 4933 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 594674 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 204492 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1426724 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 581263 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 581263 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6475 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4525 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 11000 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 835 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 565 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1400 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111606 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 135645 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247251 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 21872 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 4240 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 392730 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 284496 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30893 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 4933 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 594674 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 340137 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1673975 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 21872 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 4240 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 392730 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 284496 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30893 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 4933 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 594674 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 340137 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1673975 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000549 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000708 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.016029 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036908 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000453 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000203 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010607 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030534 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017703 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.793822 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.835801 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.811091 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.758084 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.750442 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.755000 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.567102 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.567702 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.567431 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000549 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000708 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.016029 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.244900 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000453 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000203 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010607 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.244754 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.098900 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000549 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000708 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.016029 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.244900 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000453 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000203 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010607 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.244754 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.098900 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79708.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 73166.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72979.110405 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 73632.698480 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89446.428571 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77192.969245 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 76124.839846 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 74987.251524 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1750.893580 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3197.378371 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2364.052679 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 811.181675 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7306.290094 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3416.598865 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67265.994786 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72036.949251 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 69884.650216 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79708.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 73166.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 72979.110405 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 67849.089188 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89446.428571 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 77192.969245 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 72343.553321 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 70663.127008 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79708.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 73166.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 72979.110405 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 67849.089188 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89446.428571 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 77192.969245 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 72343.553321 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 70663.127008 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 6260 # number of overall misses +system.l2c.overall_misses::cpu0.data 69647 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6325 # number of overall misses +system.l2c.overall_misses::cpu1.data 83274 # number of overall misses +system.l2c.overall_misses::total 165533 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1016250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 477500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 449841750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 482248247 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 862750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 476239250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 488675250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1899360997 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 8963096 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12325976 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 21289072 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 488979 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2955872 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3444851 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4446470608 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 6273738055 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10720208663 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 1016250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 477500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 449841750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4928718855 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 862750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 476239250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 6762413305 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 12619569660 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 1016250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 477500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 449841750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4928718855 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 862750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 476239250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 6762413305 # number of overall miss cycles +system.l2c.overall_miss_latency::total 12619569660 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 22078 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 4361 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 392602 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 172998 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30658 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5089 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 596583 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 204666 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1429035 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 581386 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 581386 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6498 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4551 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 11049 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 828 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 550 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1378 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111580 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 135650 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247230 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 22078 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 4361 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 392602 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 284578 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30658 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5089 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 596583 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 340316 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1676265 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 22078 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 4361 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 392602 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 284578 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30658 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5089 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 596583 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 340316 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1676265 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000589 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000688 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015945 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036902 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000359 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010602 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030621 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017678 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.794706 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.835201 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.811386 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.769324 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.750909 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.761974 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.566974 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.567689 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.567366 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000589 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000688 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015945 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.244738 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000359 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010602 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.244696 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.098751 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000589 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000688 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015945 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.244738 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000359 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010602 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.244696 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.098751 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78173.076923 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 159166.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71859.704473 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 75540.138941 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78431.818182 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75294.743083 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 77975.945428 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 75183.509362 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1735.688613 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3242.824520 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2374.687340 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 767.627943 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7157.075061 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3280.810476 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70285.484533 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81469.711260 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 76425.526934 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78173.076923 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 159166.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 71859.704473 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 70767.137924 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78431.818182 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75294.743083 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 81206.778887 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 76235.975062 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78173.076923 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 159166.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 71859.704473 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 70767.137924 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78431.818182 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75294.743083 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 81206.778887 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 76235.975062 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -787,180 +1022,168 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66675 # number of writebacks -system.l2c.writebacks::total 66675 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 66695 # number of writebacks +system.l2c.writebacks::total 66695 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 27 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 27 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 27 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 77 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 12 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 13 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6291 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6342 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 14 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6301 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6217 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25181 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5140 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3782 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8922 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 633 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 424 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1057 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63292 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 77006 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140298 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 12 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6257 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6345 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6317 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6240 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25186 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5164 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3801 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8965 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 637 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 413 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1050 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63263 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 77007 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140270 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 13 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6291 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 69634 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 14 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6301 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 83223 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165479 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 12 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6257 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69608 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6317 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 83247 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165456 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 13 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6291 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 69634 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 14 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6301 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 83223 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165479 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 805500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 182000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 379474750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 387080999 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1074250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 406686000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 393745000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1569124749 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51534074 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 37985753 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 89519827 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6330633 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4257919 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10588552 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3457418648 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4568436180 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8025854828 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 805500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 182000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 379474750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3844499647 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1074250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 406686000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 4962181180 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9594979577 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 805500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 182000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 379474750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3844499647 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1074250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 406686000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 4962181180 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9594979577 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6406999 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12399719988 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2451249 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154593049986 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167001628222 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1006386499 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16503554515 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17509941014 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6406999 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13406106487 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2451249 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171096604501 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184511569236 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036682 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000453 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000203 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010596 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030402 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017650 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.793822 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835801 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.811091 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.758084 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750442 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567102 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567702 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.567431 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.244763 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000453 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000203 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010596 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.244675 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.098854 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.244763 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000453 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000203 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010596 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.244675 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.098854 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61034.531536 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63333.601415 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 62313.837775 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10026.084436 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10043.826811 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10033.605358 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10042.261792 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10017.551561 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54626.471718 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59325.717217 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 57205.767923 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55210.093446 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59625.117816 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57983.064782 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55210.093446 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59625.117816 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57983.064782 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu0.inst 6257 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69608 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6317 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 83247 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165456 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 853750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 440500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 370880500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 400730997 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 728750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 396408250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 408765250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1578807997 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51771606 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38348722 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 90120328 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6378635 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4156405 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10535040 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3652529888 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5315357439 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8967887327 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 853750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 440500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 370880500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4053260885 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 728750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 396408250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5724122689 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10546695324 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 853750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 440500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 370880500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4053260885 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 728750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 396408250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5724122689 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10546695324 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6382249 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12399939239 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2397749 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154603749244 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167012468481 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1006407999 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16511968075 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17518376074 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6382249 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13406347238 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2397749 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171115717319 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184530844555 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000589 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000688 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015937 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036677 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000359 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010589 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030489 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017624 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.794706 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835201 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.811386 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.769324 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750909 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.761974 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566974 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567689 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567366 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000589 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000688 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015937 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244601 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000359 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010589 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244617 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098705 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000589 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000688 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015937 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244601 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000359 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010589 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244617 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098705 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63156.973522 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65507.251603 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62685.936512 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.485283 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10089.113917 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.462688 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.555730 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10063.934625 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10033.371429 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57735.641497 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69024.341151 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63933.038618 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58229.813886 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68760.708362 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63743.202567 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58229.813886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68760.708362 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63743.202567 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -981,62 +1204,62 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 136659470 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2706207 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2706206 # Transaction distribution +system.toL2Bus.throughput 136691596 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2708551 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2708550 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 767894 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 767894 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 581263 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 33352 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18058 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51410 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 258939 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 258939 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 786305 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073575 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13268 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55413 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1190023 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4801593 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14394 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 72130 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8006701 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25142464 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34843867 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16960 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38062080 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47776006 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 19732 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 123572 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 146072169 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 146072169 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4805124 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4892877936 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 581386 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 33382 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18023 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 51405 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 258959 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 258959 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 785985 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073715 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13547 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55934 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1193885 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4802054 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14684 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 71694 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8011498 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25134272 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34847315 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17444 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38184256 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47797126 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20356 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 122632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 146211713 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 146211713 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4800508 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4894625900 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1772488367 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1771371395 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1516304011 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1514575770 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9043467 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9208452 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 33687702 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 34011429 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2681029210 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 2689519761 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 3243394678 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 3237226447 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 9483701 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 9617950 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 41522672 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 41300207 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 46328621 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7278159 # Transaction distribution -system.iobus.trans_dist::ReadResp 7278159 # Transaction distribution +system.iobus.throughput 46298101 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7278157 # Transaction distribution +system.iobus.trans_dist::ReadResp 7278157 # Transaction distribution system.iobus.trans_dist::WriteReq 7950 # Transaction distribution system.iobus.trans_dist::WriteResp 7950 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8022 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 724 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1058,12 +1281,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382518 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 14572218 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 14572214 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1448 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1085,14 +1308,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389789 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389781 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 51148573 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 51148573 # Total data (bytes) +system.iobus.tot_pkt_size::total 51148565 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 51148565 # Total data (bytes) system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4019000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4017000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1138,42 +1361,42 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374572000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374568000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16699589511 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16664438046 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6002321 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4576737 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 295742 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3785758 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2914394 # Number of BTB hits +system.cpu0.branchPred.lookups 6002691 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4577903 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 294712 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3771820 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2913648 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 76.983104 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 673290 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28745 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.247801 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 672509 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28479 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8907919 # DTB read hits -system.cpu0.dtb.read_misses 28331 # DTB read misses -system.cpu0.dtb.write_hits 5140728 # DTB write hits -system.cpu0.dtb.write_misses 5464 # DTB write misses +system.cpu0.dtb.read_hits 8905508 # DTB read hits +system.cpu0.dtb.read_misses 28991 # DTB read misses +system.cpu0.dtb.write_hits 5140500 # DTB write hits +system.cpu0.dtb.write_misses 5723 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1828 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 958 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 306 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1824 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 969 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 309 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 551 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8936250 # DTB read accesses -system.cpu0.dtb.write_accesses 5146192 # DTB write accesses +system.cpu0.dtb.perms_faults 556 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8934499 # DTB read accesses +system.cpu0.dtb.write_accesses 5146223 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14048647 # DTB hits -system.cpu0.dtb.misses 33795 # DTB misses -system.cpu0.dtb.accesses 14082442 # DTB accesses -system.cpu0.itb.inst_hits 4222709 # ITB inst hits -system.cpu0.itb.inst_misses 5005 # ITB inst misses +system.cpu0.dtb.hits 14046008 # DTB hits +system.cpu0.dtb.misses 34714 # DTB misses +system.cpu0.dtb.accesses 14080722 # DTB accesses +system.cpu0.itb.inst_hits 4219281 # ITB inst hits +system.cpu0.itb.inst_misses 5089 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1182,114 +1405,114 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1348 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1343 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1494 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1465 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4227714 # ITB inst accesses -system.cpu0.itb.hits 4222709 # DTB hits -system.cpu0.itb.misses 5005 # DTB misses -system.cpu0.itb.accesses 4227714 # DTB accesses -system.cpu0.numCycles 69175889 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4224370 # ITB inst accesses +system.cpu0.itb.hits 4219281 # DTB hits +system.cpu0.itb.misses 5089 # DTB misses +system.cpu0.itb.accesses 4224370 # DTB accesses +system.cpu0.numCycles 69432037 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11717201 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32026454 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6002321 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3587684 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7519324 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1452827 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 60860 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 19607589 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5035 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47006 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1325879 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 324 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4221110 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157905 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2000 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41325646 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.001484 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.381957 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11713503 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32019404 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6002691 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3586157 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7516730 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1449804 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 61386 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 19631994 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46872 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1335943 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4217707 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157539 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2075 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41351812 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.000563 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.381156 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33813760 81.82% 81.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 565868 1.37% 83.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 817164 1.98% 85.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676151 1.64% 86.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 772838 1.87% 88.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 560246 1.36% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 669817 1.62% 91.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351583 0.85% 92.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3098219 7.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33842541 81.84% 81.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 565579 1.37% 83.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 816874 1.98% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 676358 1.64% 86.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 772843 1.87% 88.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 558608 1.35% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 669211 1.62% 91.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 351371 0.85% 92.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3098427 7.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41325646 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.086769 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.462971 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12221128 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20791110 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6824454 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 510238 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 978716 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935346 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64732 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40027040 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212951 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 978716 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12790081 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5972534 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12789547 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6714080 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2080688 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38920228 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 41351812 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.086454 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.461162 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12216999 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20826551 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6820783 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 510850 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 976629 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 935170 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64759 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40012064 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213022 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 976629 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12786291 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5985032 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12800887 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6711570 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2091403 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38907337 # Number of instructions processed by rename system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 436221 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1152507 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 84 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39264921 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175790758 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 161860177 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 4025 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30938700 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8326220 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411215 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370279 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5370420 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7651291 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5689186 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1120456 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1254854 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36835170 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895288 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37251130 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 81272 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6287660 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13163035 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256365 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41325646 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.901405 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.514906 # Number of insts issued each cycle +system.cpu0.rename.IQFullEvents 435425 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1163203 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 107 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39252215 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175728295 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 161804372 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 3955 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30935092 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8317122 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411284 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370379 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5367119 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7645996 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5688511 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1121166 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1220161 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36823164 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895382 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37236653 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80347 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6279547 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13158300 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256522 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41351812 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.900484 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.514831 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26248472 63.52% 63.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5690851 13.77% 77.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3114453 7.54% 84.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2470786 5.98% 90.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2128163 5.15% 95.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 926108 2.24% 98.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 506651 1.23% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 185379 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54783 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26282952 63.56% 63.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5688374 13.76% 77.32% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3116432 7.54% 84.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2466494 5.96% 90.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2112034 5.11% 95.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 939185 2.27% 98.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 506930 1.23% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 184996 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54415 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41325646 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41351812 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27685 2.59% 2.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 452 0.04% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27736 2.59% 2.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 453 0.04% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available @@ -1317,395 +1540,395 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 842164 78.64% 81.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 200566 18.73% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 842113 78.49% 81.12% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 202594 18.88% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22335497 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46969 0.13% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 704 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22326150 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46947 0.13% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9366005 25.14% 85.37% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5449722 14.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9362954 25.14% 85.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5447671 14.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37251130 # Type of FU issued -system.cpu0.iq.rate 0.538499 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1070867 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028747 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 117005145 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44025943 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34344840 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8484 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3874 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38265319 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4464 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307168 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37236653 # Type of FU issued +system.cpu0.iq.rate 0.536304 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1072896 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028813 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 117004426 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44005967 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34332716 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8422 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4624 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3857 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38252914 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4421 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307648 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1372814 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2493 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13018 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 537400 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1368398 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2491 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13086 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 537466 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192818 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5781 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192854 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5939 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 978716 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4319425 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 103424 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37848942 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 83231 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7651291 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5689186 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571145 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39872 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 13404 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13018 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150227 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117595 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267822 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36871306 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9223534 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 379824 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 976629 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4337522 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 100010 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37836354 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 83498 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7645996 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5688511 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571219 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39755 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6621 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13086 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 149491 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117486 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 266977 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36859042 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9220953 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 377611 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118484 # number of nop insts executed -system.cpu0.iew.exec_refs 14624342 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4855002 # Number of branches executed -system.cpu0.iew.exec_stores 5400808 # Number of stores executed -system.cpu0.iew.exec_rate 0.533008 # Inst execution rate -system.cpu0.iew.wb_sent 36677174 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34348714 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18316479 # num instructions producing a value -system.cpu0.iew.wb_consumers 35213732 # num instructions consuming a value +system.cpu0.iew.exec_nop 117808 # number of nop insts executed +system.cpu0.iew.exec_refs 14621413 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4853789 # Number of branches executed +system.cpu0.iew.exec_stores 5400460 # Number of stores executed +system.cpu0.iew.exec_rate 0.530865 # Inst execution rate +system.cpu0.iew.wb_sent 36664720 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34336573 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18306413 # num instructions producing a value +system.cpu0.iew.wb_consumers 35193198 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.496542 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520152 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.494535 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520169 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6093987 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638923 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232030 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40346930 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775643 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.740681 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6085996 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638860 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 231074 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40375183 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775004 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.739173 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28704762 71.14% 71.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5702920 14.13% 85.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1886389 4.68% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 981050 2.43% 92.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 790069 1.96% 94.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 509429 1.26% 95.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 395100 0.98% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 219754 0.54% 97.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1157457 2.87% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28737053 71.18% 71.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5697190 14.11% 85.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1882101 4.66% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 980199 2.43% 92.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 786708 1.95% 94.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 526531 1.30% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 398386 0.99% 96.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 216969 0.54% 97.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1150046 2.85% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40346930 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23686340 # Number of instructions committed -system.cpu0.commit.committedOps 31294803 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40375183 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23683551 # Number of instructions committed +system.cpu0.commit.committedOps 31290943 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11430263 # Number of memory references committed -system.cpu0.commit.loads 6278477 # Number of loads committed -system.cpu0.commit.membars 229716 # Number of memory barriers committed -system.cpu0.commit.branches 4246456 # Number of branches committed +system.cpu0.commit.refs 11428643 # Number of memory references committed +system.cpu0.commit.loads 6277598 # Number of loads committed +system.cpu0.commit.membars 229694 # Number of memory barriers committed +system.cpu0.commit.branches 4245889 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27650320 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489514 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1157457 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27646853 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489416 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1150046 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75726854 # The number of ROB reads -system.cpu0.rob.rob_writes 75758265 # The number of ROB writes -system.cpu0.timesIdled 367474 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27850243 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138859041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23605598 # Number of Instructions Simulated -system.cpu0.committedOps 31214061 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23605598 # Number of Instructions Simulated -system.cpu0.cpi 2.930487 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.930487 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.341240 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.341240 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171860544 # number of integer regfile reads -system.cpu0.int_regfile_writes 34096305 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads -system.cpu0.fp_regfile_writes 892 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13010065 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451140 # number of misc regfile writes -system.cpu0.icache.tags.replacements 392795 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.002835 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3796668 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 393307 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.653192 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6982777250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.002835 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998052 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998052 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3796668 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3796668 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3796668 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3796668 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3796668 # number of overall hits -system.cpu0.icache.overall_hits::total 3796668 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 424314 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 424314 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 424314 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 424314 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 424314 # number of overall misses -system.cpu0.icache.overall_misses::total 424314 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5901888496 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5901888496 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5901888496 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5901888496 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5901888496 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5901888496 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4220982 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4220982 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4220982 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4220982 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4220982 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4220982 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100525 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100525 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100525 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100525 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100525 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100525 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13909.247623 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13909.247623 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13909.247623 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13909.247623 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13909.247623 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13909.247623 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3930 # number of cycles access was blocked +system.cpu0.rob.rob_reads 75750709 # The number of ROB reads +system.cpu0.rob.rob_writes 75732466 # The number of ROB writes +system.cpu0.timesIdled 364061 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 28080225 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2140058132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23602809 # Number of Instructions Simulated +system.cpu0.committedOps 31210201 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23602809 # Number of Instructions Simulated +system.cpu0.cpi 2.941685 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.941685 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.339941 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.339941 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171807193 # number of integer regfile reads +system.cpu0.int_regfile_writes 34081987 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3237 # number of floating regfile reads +system.cpu0.fp_regfile_writes 886 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13003191 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451099 # number of misc regfile writes +system.cpu0.icache.tags.replacements 392605 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.965142 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3793600 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 393117 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.650053 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7051834000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.965142 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997979 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997979 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3793600 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3793600 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3793600 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3793600 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3793600 # number of overall hits +system.cpu0.icache.overall_hits::total 3793600 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423979 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423979 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423979 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423979 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423979 # number of overall misses +system.cpu0.icache.overall_misses::total 423979 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5892352014 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5892352014 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5892352014 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5892352014 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5892352014 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5892352014 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4217579 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4217579 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4217579 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4217579 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4217579 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4217579 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100527 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100527 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100527 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100527 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100527 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100527 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13897.744969 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13897.744969 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13897.744969 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13897.744969 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13897.744969 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13897.744969 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3802 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 194 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 164 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.257732 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.182927 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30982 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30982 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30982 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30982 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30982 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30982 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393332 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393332 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393332 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393332 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393332 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393332 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4803860873 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4803860873 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4803860873 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4803860873 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4803860873 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4803860873 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8948750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8948750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8948750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8948750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093185 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093185 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093185 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093185 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093185 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093185 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12213.247010 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12213.247010 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12213.247010 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12213.247010 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12213.247010 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12213.247010 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30839 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30839 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30839 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30839 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30839 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30839 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393140 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 393140 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 393140 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 393140 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 393140 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393140 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4794002596 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4794002596 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4794002596 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4794002596 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4794002596 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4794002596 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8923000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8923000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8923000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8923000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093215 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093215 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093215 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12194.135921 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12194.135921 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12194.135921 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 276222 # number of replacements -system.cpu0.dcache.tags.tagsinuse 460.530312 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9262144 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 276734 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.469483 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 42960250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 460.530312 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.899473 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.899473 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5781621 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5781621 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3159389 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3159389 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139147 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139147 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137077 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137077 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8941010 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8941010 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8941010 # number of overall hits -system.cpu0.dcache.overall_hits::total 8941010 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 391790 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 391790 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1584826 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1584826 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8742 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8742 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7480 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7480 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1976616 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1976616 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1976616 # number of overall misses -system.cpu0.dcache.overall_misses::total 1976616 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5523901183 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5523901183 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77315448541 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 77315448541 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88125732 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88125732 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45924629 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 45924629 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 82839349724 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 82839349724 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 82839349724 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 82839349724 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6173411 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6173411 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744215 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4744215 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147889 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 147889 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144557 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144557 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10917626 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10917626 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10917626 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10917626 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063464 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063464 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334054 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.334054 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059112 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059112 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051744 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051744 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181048 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.181048 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181048 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.181048 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14099.137760 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14099.137760 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48784.818359 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 48784.818359 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10080.728895 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10080.728895 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6139.656283 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6139.656283 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41909.682874 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 41909.682874 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41909.682874 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41909.682874 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 11704 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 6407 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 613 # number of cycles access was blocked +system.cpu0.dcache.tags.replacements 276287 # number of replacements +system.cpu0.dcache.tags.tagsinuse 459.684046 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9258198 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 276799 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.447368 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 43491250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 459.684046 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.897820 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.897820 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5778274 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5778274 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3158747 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3158747 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139141 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139141 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137092 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137092 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8937021 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8937021 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8937021 # number of overall hits +system.cpu0.dcache.overall_hits::total 8937021 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392090 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392090 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1584925 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1584925 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8730 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8730 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7451 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7451 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1977015 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1977015 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1977015 # number of overall misses +system.cpu0.dcache.overall_misses::total 1977015 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5539255201 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5539255201 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79907349135 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 79907349135 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 90050735 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 90050735 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45818635 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 45818635 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 85446604336 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 85446604336 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 85446604336 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 85446604336 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6170364 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6170364 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743672 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4743672 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147871 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147871 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144543 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144543 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10914036 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10914036 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10914036 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10914036 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063544 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063544 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334114 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.334114 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059038 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059038 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051549 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051549 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181144 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181144 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181144 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181144 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14127.509503 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14127.509503 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50417.116983 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50417.116983 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10315.089920 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10315.089920 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6149.326936 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6149.326936 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43220.008111 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43220.008111 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43220.008111 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43220.008111 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9481 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 10276 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 609 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 131 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.092985 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 48.908397 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.568144 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 78.442748 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256512 # number of writebacks -system.cpu0.dcache.writebacks::total 256512 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203095 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 203095 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454344 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1454344 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 453 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 453 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657439 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657439 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657439 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657439 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188695 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188695 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130482 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130482 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8289 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8289 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7480 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7480 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319177 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319177 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319177 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319177 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2406687867 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2406687867 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5110325446 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5110325446 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66640768 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66640768 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30961371 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30961371 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7517013313 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7517013313 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7517013313 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7517013313 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504611525 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504611525 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131834379 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131834379 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14636445904 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14636445904 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030566 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030566 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027503 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027503 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056049 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056049 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051744 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051744 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029235 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029235 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029235 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029235 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12754.380704 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12754.380704 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39164.984028 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39164.984028 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.663168 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8039.663168 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4139.220722 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4139.220722 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23551.237442 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23551.237442 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23551.237442 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23551.237442 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256484 # number of writebacks +system.cpu0.dcache.writebacks::total 256484 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203289 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 203289 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454440 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1454440 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 445 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 445 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657729 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657729 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657729 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657729 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188801 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188801 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130485 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130485 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8285 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8285 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7449 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7449 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319286 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319286 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319286 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319286 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2419086873 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2419086873 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5310990170 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5310990170 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68672765 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68672765 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30919365 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30919365 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7730077043 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7730077043 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7730077043 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7730077043 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504888791 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504888791 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131913883 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131913883 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14636802674 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14636802674 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030598 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030598 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027507 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027507 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056029 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056029 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051535 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051535 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029255 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029255 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029255 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029255 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12812.892268 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12812.892268 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40701.921064 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40701.921064 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8288.806880 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8288.806880 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4150.807491 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4150.807491 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24210.510461 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24210.510461 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24210.510461 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24210.510461 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1713,38 +1936,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8782132 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7168426 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 407819 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5819499 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4955017 # Number of BTB hits +system.cpu1.branchPred.lookups 8781819 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7169373 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 406881 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5765537 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4953289 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.145079 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 773793 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42171 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.912015 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 772113 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42948 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42691295 # DTB read hits -system.cpu1.dtb.read_misses 36496 # DTB read misses -system.cpu1.dtb.write_hits 6824033 # DTB write hits -system.cpu1.dtb.write_misses 10597 # DTB write misses +system.cpu1.dtb.read_hits 42694682 # DTB read hits +system.cpu1.dtb.read_misses 36199 # DTB read misses +system.cpu1.dtb.write_hits 6825983 # DTB write hits +system.cpu1.dtb.write_misses 10603 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2020 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2612 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 305 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2017 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2691 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 287 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 657 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42727791 # DTB read accesses -system.cpu1.dtb.write_accesses 6834630 # DTB write accesses +system.cpu1.dtb.perms_faults 664 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42730881 # DTB read accesses +system.cpu1.dtb.write_accesses 6836586 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49515328 # DTB hits -system.cpu1.dtb.misses 47093 # DTB misses -system.cpu1.dtb.accesses 49562421 # DTB accesses -system.cpu1.itb.inst_hits 7577708 # ITB inst hits -system.cpu1.itb.inst_misses 5297 # ITB inst misses +system.cpu1.dtb.hits 49520665 # DTB hits +system.cpu1.dtb.misses 46802 # DTB misses +system.cpu1.dtb.accesses 49567467 # DTB accesses +system.cpu1.itb.inst_hits 7578103 # ITB inst hits +system.cpu1.itb.inst_misses 5415 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1753,114 +1976,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1529 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1532 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1545 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1496 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7583005 # ITB inst accesses -system.cpu1.itb.hits 7577708 # DTB hits -system.cpu1.itb.misses 5297 # DTB misses -system.cpu1.itb.accesses 7583005 # DTB accesses -system.cpu1.numCycles 408491180 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7583518 # ITB inst accesses +system.cpu1.itb.hits 7578103 # DTB hits +system.cpu1.itb.misses 5415 # DTB misses +system.cpu1.itb.accesses 7583518 # DTB accesses +system.cpu1.numCycles 409882606 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 18854224 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 60287918 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8782132 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5728810 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13124144 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3307681 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 62009 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77240238 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4754 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42673 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1437796 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7575877 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 546214 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2648 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 113028448 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.652235 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.978835 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 18878139 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 60299044 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8781819 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5725402 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13123323 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3309042 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 63154 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 78443797 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5020 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42366 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1440662 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7576329 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 547353 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2737 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114261108 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.645293 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.969526 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 99911588 88.40% 88.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796149 0.70% 89.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 938672 0.83% 89.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1688468 1.49% 91.42% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1396344 1.24% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 570472 0.50% 93.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1929580 1.71% 94.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410359 0.36% 95.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5386816 4.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 101145087 88.52% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796077 0.70% 89.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 936773 0.82% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1687391 1.48% 91.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1395150 1.22% 92.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 571856 0.50% 93.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1930284 1.69% 94.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 409373 0.36% 95.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5389117 4.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 113028448 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.021499 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.147587 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20182430 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 78186513 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11968696 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 524734 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2166075 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1104186 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 97997 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69821372 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 325725 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2166075 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 21372370 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33233612 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40763249 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11209012 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4284130 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 65907040 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18855 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 668466 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3042854 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 1130 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 69218982 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 302521919 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 280703259 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6508 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49058929 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20160053 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444772 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387840 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7873214 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12591353 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7935523 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1036537 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1457992 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 60681374 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157953 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 87712578 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93570 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13421216 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 35924412 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277156 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 113028448 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.776022 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519284 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114261108 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.021425 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.147113 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20196476 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 79405562 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11967958 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 523276 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2167836 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1103528 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98181 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69822224 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 326370 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2167836 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 21386304 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 34427825 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40782107 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11206546 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4290490 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 65904089 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18821 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 671145 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3046869 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 355 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 69217965 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 302501585 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 280690851 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6493 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49057579 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20160386 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444741 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387793 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7877859 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12590402 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7938263 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1041211 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1447247 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 60694774 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1157845 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 87723814 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94478 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13427979 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 35976172 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277080 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114261108 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.767749 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.513486 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83202776 73.61% 73.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8275815 7.32% 80.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4119768 3.64% 84.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3698740 3.27% 87.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10372542 9.18% 97.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1968067 1.74% 98.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1039899 0.92% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 275618 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 75223 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 84436887 73.90% 73.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8271726 7.24% 81.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4125209 3.61% 84.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3692140 3.23% 87.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10373138 9.08% 97.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1967895 1.72% 98.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1041724 0.91% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 276233 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 76156 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 113028448 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114261108 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32070 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32226 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 994 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available @@ -1888,395 +2111,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7550021 95.87% 96.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 292311 3.71% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7551636 95.89% 96.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 290793 3.69% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 314062 0.36% 0.36% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36603154 41.73% 42.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59244 0.07% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36606472 41.73% 42.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59249 0.07% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.16% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.16% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43563118 49.67% 91.82% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7171472 8.18% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43568189 49.67% 91.82% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7174305 8.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 87712578 # Type of FU issued -system.cpu1.iq.rate 0.214723 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7875398 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.089786 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 296453915 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 75268930 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53141218 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15550 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8086 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6819 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 95265602 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8312 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 341261 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 87723814 # Type of FU issued +system.cpu1.iq.rate 0.214022 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7875649 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089778 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 297709996 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 75289267 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53144243 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15477 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8000 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 95277128 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8273 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 341654 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2835568 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3737 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17004 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1095143 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2834942 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3919 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17226 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1098203 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31913350 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 674872 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31919752 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 674526 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2166075 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25455774 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 362563 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 61943028 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 112233 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12591353 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7935523 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869270 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64753 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6199 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17004 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 201423 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 154723 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 356146 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 85989556 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43061283 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1723022 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2167836 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 26657812 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 361941 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 61957280 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 112544 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12590402 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7938263 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869014 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64925 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4205 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17226 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 200285 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 154811 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 355096 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 85998990 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43064757 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1724824 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 103701 # number of nop insts executed -system.cpu1.iew.exec_refs 50171461 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6912906 # Number of branches executed -system.cpu1.iew.exec_stores 7110178 # Number of stores executed -system.cpu1.iew.exec_rate 0.210505 # Inst execution rate -system.cpu1.iew.wb_sent 85230378 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53148037 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29710424 # num instructions producing a value -system.cpu1.iew.wb_consumers 52969976 # num instructions consuming a value +system.cpu1.iew.exec_nop 104661 # number of nop insts executed +system.cpu1.iew.exec_refs 50176981 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6911907 # Number of branches executed +system.cpu1.iew.exec_stores 7112224 # Number of stores executed +system.cpu1.iew.exec_rate 0.209814 # Inst execution rate +system.cpu1.iew.wb_sent 85240093 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53151046 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29713379 # num instructions producing a value +system.cpu1.iew.wb_consumers 52980753 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.130108 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560892 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.129674 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560833 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13294883 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880797 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 311444 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 110862373 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.434393 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.404754 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13311701 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880765 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 310263 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 112093272 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.429609 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.397405 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94147475 84.92% 84.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8220753 7.42% 92.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2089215 1.88% 94.22% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1249683 1.13% 95.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1247924 1.13% 96.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 575753 0.52% 96.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 991767 0.89% 97.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 529898 0.48% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1809905 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 95372912 85.08% 85.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8221460 7.33% 92.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2092695 1.87% 94.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1254196 1.12% 95.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1248841 1.11% 96.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 572620 0.51% 97.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 992421 0.89% 97.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 531111 0.47% 98.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1807016 1.61% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 110862373 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38066252 # Number of instructions committed -system.cpu1.commit.committedOps 48157821 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 112093272 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38065083 # Number of instructions committed +system.cpu1.commit.committedOps 48156333 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16596165 # Number of memory references committed -system.cpu1.commit.loads 9755785 # Number of loads committed -system.cpu1.commit.membars 190126 # Number of memory barriers committed -system.cpu1.commit.branches 5967905 # Number of branches committed +system.cpu1.commit.refs 16595520 # Number of memory references committed +system.cpu1.commit.loads 9755460 # Number of loads committed +system.cpu1.commit.membars 190120 # Number of memory barriers committed +system.cpu1.commit.branches 5967695 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42692526 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534650 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1809905 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42691207 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534629 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1807016 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 169461098 # The number of ROB reads -system.cpu1.rob.rob_writes 125154390 # The number of ROB writes -system.cpu1.timesIdled 1414583 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295462732 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1798949280 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37996613 # Number of Instructions Simulated -system.cpu1.committedOps 48088182 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37996613 # Number of Instructions Simulated -system.cpu1.cpi 10.750726 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.750726 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.093017 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.093017 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 384900722 # number of integer regfile reads -system.cpu1.int_regfile_writes 55276259 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5045 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2312 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18451458 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405460 # number of misc regfile writes -system.cpu1.icache.tags.replacements 594712 # number of replacements -system.cpu1.icache.tags.tagsinuse 480.460982 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6935744 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 595224 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.652326 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74833132000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.460982 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938400 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.938400 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 6935744 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6935744 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6935744 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6935744 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6935744 # number of overall hits -system.cpu1.icache.overall_hits::total 6935744 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 640085 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 640085 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 640085 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 640085 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 640085 # number of overall misses -system.cpu1.icache.overall_misses::total 640085 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8700934064 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8700934064 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8700934064 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8700934064 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8700934064 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8700934064 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7575829 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7575829 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7575829 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7575829 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7575829 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7575829 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084490 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084490 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084490 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.084490 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084490 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.084490 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13593.404101 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13593.404101 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13593.404101 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13593.404101 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13593.404101 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13593.404101 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2623 # number of cycles access was blocked +system.cpu1.rob.rob_reads 170710273 # The number of ROB reads +system.cpu1.rob.rob_writes 125186848 # The number of ROB writes +system.cpu1.timesIdled 1415125 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295621498 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1799013115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37995444 # Number of Instructions Simulated +system.cpu1.committedOps 48086694 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37995444 # Number of Instructions Simulated +system.cpu1.cpi 10.787678 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.787678 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092698 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092698 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 384930549 # number of integer regfile reads +system.cpu1.int_regfile_writes 55277579 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5074 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18448778 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405411 # number of misc regfile writes +system.cpu1.icache.tags.replacements 596659 # number of replacements +system.cpu1.icache.tags.tagsinuse 480.521199 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6934084 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 597171 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.611555 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74930526000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.521199 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938518 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.938518 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 6934084 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6934084 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6934084 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6934084 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6934084 # number of overall hits +system.cpu1.icache.overall_hits::total 6934084 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 642197 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 642197 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 642197 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 642197 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 642197 # number of overall misses +system.cpu1.icache.overall_misses::total 642197 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8716898620 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8716898620 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8716898620 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8716898620 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8716898620 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8716898620 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7576281 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7576281 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7576281 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7576281 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7576281 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7576281 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084764 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.084764 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084764 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.084764 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084764 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.084764 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13573.558612 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13573.558612 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13573.558612 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13573.558612 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13573.558612 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13573.558612 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3156 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 183 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 190 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.333333 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.610526 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44828 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44828 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44828 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44828 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44828 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44828 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 595257 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 595257 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 595257 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 595257 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 595257 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 595257 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7103878279 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7103878279 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7103878279 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7103878279 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7103878279 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7103878279 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3410750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3410750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3410750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3410750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078573 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078573 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078573 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.078573 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078573 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.078573 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11934.136481 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11934.136481 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11934.136481 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11934.136481 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11934.136481 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11934.136481 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44987 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44987 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44987 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44987 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44987 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44987 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597210 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 597210 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 597210 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 597210 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 597210 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 597210 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7115046481 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7115046481 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7115046481 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7115046481 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7115046481 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7115046481 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3356250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3356250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3356250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3356250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078826 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.078826 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.078826 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11913.810018 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11913.810018 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11913.810018 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 360690 # number of replacements -system.cpu1.dcache.tags.tagsinuse 473.926621 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 12678192 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 361043 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.115463 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 70882645000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.926621 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925638 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.925638 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8311339 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8311339 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4138952 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4138952 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97545 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97545 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94900 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94900 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12450291 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12450291 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12450291 # number of overall hits -system.cpu1.dcache.overall_hits::total 12450291 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 397118 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 397118 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1557827 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1557827 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13956 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13956 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10582 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10582 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1954945 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1954945 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1954945 # number of overall misses -system.cpu1.dcache.overall_misses::total 1954945 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6022716747 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6022716747 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 76093468282 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 76093468282 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129448993 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 129448993 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53146420 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53146420 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 82116185029 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 82116185029 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 82116185029 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 82116185029 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8708457 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8708457 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696779 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5696779 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111501 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111501 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105482 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105482 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14405236 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14405236 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14405236 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14405236 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045601 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045601 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273458 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273458 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125165 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125165 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100320 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100320 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135711 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135711 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135711 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135711 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15166.063354 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15166.063354 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 48845.904123 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 48845.904123 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9275.508240 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9275.508240 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5022.341712 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5022.341712 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42004.345406 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 42004.345406 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42004.345406 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 42004.345406 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29557 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 18184 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3279 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.014029 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 108.238095 # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 360813 # number of replacements +system.cpu1.dcache.tags.tagsinuse 473.792536 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 12672687 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 361164 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.088456 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70971728000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.792536 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925376 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.925376 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8306232 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8306232 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4138701 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4138701 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97355 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97355 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94895 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 94895 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12444933 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12444933 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12444933 # number of overall hits +system.cpu1.dcache.overall_hits::total 12444933 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 398716 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 398716 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1557859 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1557859 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13937 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13937 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10575 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10575 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1956575 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1956575 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1956575 # number of overall misses +system.cpu1.dcache.overall_misses::total 1956575 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6078170016 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6078170016 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 80199088679 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 80199088679 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 128606244 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 128606244 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52837907 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 52837907 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 86277258695 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 86277258695 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 86277258695 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 86277258695 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8704948 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8704948 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696560 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5696560 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111292 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111292 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105470 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105470 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14401508 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14401508 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14401508 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14401508 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045803 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045803 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273474 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273474 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125229 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125229 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100265 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100265 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135859 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135859 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135859 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135859 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.359434 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.359434 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 51480.325677 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 51480.325677 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9227.684868 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9227.684868 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 4996.492388 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 4996.492388 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 44096.065162 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 44096.065162 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 44096.065162 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 44096.065162 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 31164 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18449 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3306 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.426497 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 111.138554 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324751 # number of writebacks -system.cpu1.dcache.writebacks::total 324751 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168850 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 168850 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396175 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1396175 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1565025 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1565025 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1565025 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1565025 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228268 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228268 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161652 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161652 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12509 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12509 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10578 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10578 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389920 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389920 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389920 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389920 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2830993566 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2830993566 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6516328872 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6516328872 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88639506 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88639506 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31988580 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31988580 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9347322438 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9347322438 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9347322438 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9347322438 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168914513007 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168914513007 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25825904490 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25825904490 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194740417497 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194740417497 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026212 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026212 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028376 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028376 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112187 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112187 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100283 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100283 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027068 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027068 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027068 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027068 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12402.060587 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12402.060587 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40310.845965 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40310.845965 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7086.058518 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7086.058518 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3024.066931 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3024.066931 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23972.410848 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23972.410848 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23972.410848 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23972.410848 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324902 # number of writebacks +system.cpu1.dcache.writebacks::total 324902 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170345 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 170345 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396167 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1396167 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1435 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1435 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566512 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1566512 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566512 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1566512 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228371 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228371 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161692 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161692 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12502 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12502 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10574 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10574 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 390063 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 390063 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 390063 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 390063 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2847018297 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2847018297 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7247965426 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7247965426 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87929505 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87929505 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31688093 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31688093 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 10094983723 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 10094983723 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 10094983723 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 10094983723 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168925175261 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168925175261 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25838951416 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25838951416 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194764126677 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194764126677 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026235 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026235 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028384 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028384 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112335 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112335 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100256 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100256 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027085 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027085 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027085 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027085 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12466.636731 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12466.636731 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44825.751589 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44825.751589 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7033.235082 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7033.235082 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 2996.793361 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2996.793361 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25880.392970 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25880.392970 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25880.392970 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25880.392970 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2298,18 +2521,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 582931892511 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 582931892511 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 582931892511 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 582931892511 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612781961046 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 612781961046 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612781961046 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 612781961046 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41731 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41730 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48858 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48851 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index ab328c798..b60e42a06 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,132 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.524310 # Number of seconds simulated -sim_ticks 2524309551500 # Number of ticks simulated -final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525141 # Number of seconds simulated +sim_ticks 2525141046500 # Number of ticks simulated +final_tick 2525141046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65403 # Simulator instruction rate (inst/s) -host_op_rate 84155 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2737677908 # Simulator tick rate (ticks/s) -host_mem_usage 401408 # Number of bytes of host memory used -host_seconds 922.06 # Real time elapsed on the host -sim_insts 60305560 # Number of instructions simulated -sim_ops 77596391 # Number of ops (including micro ops) simulated +host_inst_rate 61643 # Simulator instruction rate (inst/s) +host_op_rate 79318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2581152882 # Simulator tick rate (ticks/s) +host_mem_usage 426780 # Number of bytes of host memory used +host_seconds 978.30 # Real time elapsed on the host +sim_insts 60305756 # Number of instructions simulated +sim_ops 77596741 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory -system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094416 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784000 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800072 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142134 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59125 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 966197440 # Total number of bytes read from memory -system.physmem.bytesWritten 52040704 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943576 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943285 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 942562 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943112 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943114 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 941930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943211 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 941608 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943681 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943781 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 942622 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6701 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6473 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6647 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6560 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6809 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6802 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6725 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6889 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6554 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6197 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6775 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7049 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2524308440000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14942208 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154591 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754018 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59118 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1057147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 988434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 981496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3682842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2771885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2756532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2709889 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 16218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47339005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3601548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51257392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498530 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2692947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47339005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4795965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53950339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096843 # Number of read requests accepted +system.physmem.writeReqs 813143 # Number of write requests accepted +system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813143 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue +system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6800072 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943582 # Per bank write bursts +system.physmem.perBankRdBursts::1 943145 # Per bank write bursts +system.physmem.perBankRdBursts::2 939291 # Per bank write bursts +system.physmem.perBankRdBursts::3 939307 # Per bank write bursts +system.physmem.perBankRdBursts::4 943115 # Per bank write bursts +system.physmem.perBankRdBursts::5 943141 # Per bank write bursts +system.physmem.perBankRdBursts::6 939138 # Per bank write bursts +system.physmem.perBankRdBursts::7 938546 # Per bank write bursts +system.physmem.perBankRdBursts::8 943996 # Per bank write bursts +system.physmem.perBankRdBursts::9 943390 # Per bank write bursts +system.physmem.perBankRdBursts::10 938426 # Per bank write bursts +system.physmem.perBankRdBursts::11 937974 # Per bank write bursts +system.physmem.perBankRdBursts::12 943928 # Per bank write bursts +system.physmem.perBankRdBursts::13 943533 # Per bank write bursts +system.physmem.perBankRdBursts::14 939234 # Per bank write bursts +system.physmem.perBankRdBursts::15 938672 # Per bank write bursts +system.physmem.perBankWrBursts::0 6704 # Per bank write bursts +system.physmem.perBankWrBursts::1 6457 # Per bank write bursts +system.physmem.perBankWrBursts::2 6598 # Per bank write bursts +system.physmem.perBankWrBursts::3 6635 # Per bank write bursts +system.physmem.perBankWrBursts::4 6561 # Per bank write bursts +system.physmem.perBankWrBursts::5 6794 # Per bank write bursts +system.physmem.perBankWrBursts::6 6789 # Per bank write bursts +system.physmem.perBankWrBursts::7 6723 # Per bank write bursts +system.physmem.perBankWrBursts::8 7136 # Per bank write bursts +system.physmem.perBankWrBursts::9 6877 # Per bank write bursts +system.physmem.perBankWrBursts::10 6538 # Per bank write bursts +system.physmem.perBankWrBursts::11 6183 # Per bank write bursts +system.physmem.perBankWrBursts::12 7149 # Per bank write bursts +system.physmem.perBankWrBursts::13 6765 # Per bank write bursts +system.physmem.perBankWrBursts::14 7038 # Per bank write bursts +system.physmem.perBankWrBursts::15 6899 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2525139929000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 36 # Read request sizes (log2) +system.physmem.readPktSize::3 14942208 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 154599 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 59125 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1163754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1108384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1064134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3627605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2618920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2606295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2613037 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 58180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -140,294 +142,604 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-143 3432 8.79% 25.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-207 2242 5.74% 31.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-271 1810 4.64% 36.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-399 1032 2.64% 42.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-463 839 2.15% 44.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-591 572 1.47% 47.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-655 506 1.30% 49.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-719 409 1.05% 50.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-783 444 1.14% 51.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-847 300 0.77% 52.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-911 247 0.63% 52.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-975 176 0.45% 53.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1039 206 0.53% 53.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1103 143 0.37% 54.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1167 146 0.37% 54.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1231 98 0.25% 54.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1295 114 0.29% 54.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1359 72 0.18% 55.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1423 399 1.02% 56.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1487 280 0.72% 56.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1551 475 1.22% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1615 79 0.20% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1679 157 0.40% 58.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1743 41 0.11% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1807 100 0.26% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1871 28 0.07% 59.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1935 78 0.20% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1999 27 0.07% 59.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2063 49 0.13% 59.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2127 25 0.06% 59.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2191 51 0.13% 59.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2255 21 0.05% 59.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2319 30 0.08% 59.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2447 27 0.07% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2511 11 0.03% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2575 21 0.05% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2639 5 0.01% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2703 18 0.05% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2767 7 0.02% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2831 11 0.03% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2895 7 0.02% 60.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2959 14 0.04% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3023 6 0.02% 60.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3087 22 0.06% 60.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3215 7 0.02% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3279 4 0.01% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3343 12 0.03% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3599 9 0.02% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3727 6 0.02% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3791 3 0.01% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3855 8 0.02% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3919 3 0.01% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3983 10 0.03% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4047 5 0.01% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4111 44 0.11% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4175 3 0.01% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4239 1 0.00% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4303 5 0.01% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4367 9 0.02% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4495 1 0.00% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4559 3 0.01% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4623 9 0.02% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4687 1 0.00% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4815 1 0.00% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4879 2 0.01% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5007 4 0.01% 60.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5135 7 0.02% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5263 3 0.01% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5391 4 0.01% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5455 1 0.00% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5519 3 0.01% 60.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5775 3 0.01% 60.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5903 3 0.01% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5967 1 0.00% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6031 1 0.00% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6223 1 0.00% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6287 3 0.01% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6479 4 0.01% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6607 2 0.01% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6735 2 0.01% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6799 18 0.05% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6863 4 0.01% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7183 4 0.01% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7311 4 0.01% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7375 1 0.00% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7439 12 0.03% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7503 1 0.00% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7567 2 0.01% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7695 9 0.02% 61.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7823 3 0.01% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7887 2 0.01% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7951 5 0.01% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8015 1 0.00% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8079 7 0.02% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8143 2 0.01% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8207 325 0.83% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8463 41 0.11% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8527 123 0.32% 62.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8591 7 0.02% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8719 1 0.00% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8783 1 0.00% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9231 8 0.02% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9487 2 0.01% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9743 1 0.00% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9999 1 0.00% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10255 2 0.01% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12303 3 0.01% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12559 2 0.01% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13071 1 0.00% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13327 3 0.01% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13583 2 0.01% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13839 1 0.00% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14095 1 0.00% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14351 4 0.01% 62.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14607 2 0.01% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14991 1 0.00% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15119 1 0.00% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15375 1 0.00% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16399 1 0.00% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17167 3 0.01% 62.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17423 3 0.01% 62.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17679 2 0.01% 62.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17935 1 0.00% 62.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18191 2 0.01% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18447 2 0.01% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18703 1 0.00% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19215 2 0.01% 62.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19471 3 0.01% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19727 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21519 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21775 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22208-22223 1 0.00% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22287 2 0.01% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22543 4 0.01% 62.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22799 3 0.01% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23311 1 0.00% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23567 3 0.01% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23616-23631 1 0.00% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24335 1 0.00% 62.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24591 2 0.01% 62.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25359 2 0.01% 62.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25615 3 0.01% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26127 2 0.01% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26383 1 0.00% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26639 1 0.00% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27151 1 0.00% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27663 2 0.01% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27919 4 0.01% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28687 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28943 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29199 2 0.01% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29455 1 0.00% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30479 1 0.00% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30735 4 0.01% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30991 1 0.00% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31375 1 0.00% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31759 3 0.01% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32783 2 0.01% 62.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33551 12 0.03% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33615 1 0.00% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33743 1 0.00% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33807 45 0.12% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34831 1 0.00% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36367 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37647 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39439 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40271 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41231 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41743 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42767 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44303 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45199 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46095 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47247 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47375 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47631 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48399 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49728-49743 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50255 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50304-50319 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50560-50575 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50752-50767 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51392-51407 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51712-51727 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51968-51983 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52239 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53263 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53824-53839 1 0.00% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56335 2 0.01% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58383 1 0.00% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59407 2 0.01% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60431 2 0.01% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61120-61135 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61184-61199 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61455 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63936-63951 1 0.00% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64527 1 0.00% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65039 192 0.49% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65295 6 0.02% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65551 14116 36.16% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::66048-66063 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::69760-69775 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73536-73551 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73856-73871 2 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73920-73935 24 0.06% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-73999 78 0.20% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74048-74063 68 0.17% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation -system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests -system.physmem.totBusLat 75453215000 # Total cycles spent in databus access -system.physmem.totBankLat 15307050000 # Total cycles spent in bank access -system.physmem.avgQLat 19314.15 # Average queueing delay per request -system.physmem.avgBankLat 1014.34 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25328.49 # Average memory access latency -system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 14.41 # Average write queue length over time -system.physmem.readRowHits 15065383 # Number of row buffer hits during reads -system.physmem.writeRowHits 94229 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes -system.physmem.avgGap 158662.04 # Average gap between requests +system.physmem.bytesPerActivate::samples 86114 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11271.566528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1003.490719 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16771.547354 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23576 27.38% 27.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14050 16.32% 43.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2599 3.02% 46.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2090 2.43% 49.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1311 1.52% 50.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1239 1.44% 52.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 869 1.01% 53.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1005 1.17% 54.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 571 0.66% 54.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 602 0.70% 55.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 523 0.61% 56.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 509 0.59% 56.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 284 0.33% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 276 0.32% 57.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 154 0.18% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 642 0.75% 58.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 97 0.11% 58.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 141 0.16% 58.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 78 0.09% 58.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 123 0.14% 58.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 49 0.06% 58.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 518 0.60% 59.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 316 0.37% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 18 0.02% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 102 0.12% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 211 0.25% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 55 0.06% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 327 0.38% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 31 0.04% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 124 0.14% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 3 0.00% 61.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 9 0.01% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 99 0.11% 61.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 90 0.10% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 23 0.03% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 2 0.00% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 292 0.34% 61.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 98 0.11% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 9 0.01% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 18 0.02% 61.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 8 0.01% 61.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 97 0.11% 62.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 158 0.18% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 373 0.43% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 16 0.02% 62.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 116 0.13% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 99 0.11% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 19 0.02% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 13 0.02% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 426 0.49% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 8 0.01% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 6 0.01% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 28 0.03% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 19 0.02% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 89 0.10% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 2 0.00% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 15 0.02% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 413 0.48% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 87 0.10% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 12 0.01% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 145 0.17% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 24 0.03% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 363 0.42% 65.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 9 0.01% 65.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 10 0.01% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 98 0.11% 65.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 3 0.00% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 82 0.10% 65.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 13 0.02% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 508 0.59% 66.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 76 0.09% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 89 0.10% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 74 0.09% 66.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 350 0.41% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 17 0.02% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 3 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9671 1 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 138 0.16% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 6 0.01% 67.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 402 0.47% 67.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 84 0.10% 67.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 76 0.09% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 15 0.02% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 1 0.00% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 416 0.48% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 13 0.02% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 84 0.10% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 98 0.11% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 5 0.01% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 335 0.39% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 3 0.00% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 141 0.16% 69.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 79 0.09% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 86 0.10% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 4 0.00% 69.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 286 0.33% 69.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 76 0.09% 69.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 74 0.09% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 91 0.11% 70.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 284 0.33% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 2 0.00% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 139 0.16% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 146 0.17% 70.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15303 2 0.00% 70.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 17 0.02% 71.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 80 0.09% 71.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 74 0.09% 71.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 11 0.01% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 645 0.75% 72.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 72 0.08% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16711 2 0.00% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16839 1 0.00% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 78 0.09% 72.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 28 0.03% 72.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 5 0.01% 72.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 407 0.47% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 2 0.00% 72.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 18 0.02% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17735 2 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 3 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 147 0.17% 73.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-17991 1 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18112-18119 2 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 144 0.17% 73.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 4 0.00% 73.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 279 0.32% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 89 0.10% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18880-18887 2 0.00% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 73 0.08% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19143 1 0.00% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 77 0.09% 73.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 5 0.01% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 263 0.31% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 82 0.10% 74.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 79 0.09% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 140 0.16% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20288-20295 1 0.00% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 343 0.40% 74.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20672-20679 1 0.00% 74.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 96 0.11% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20864-20871 2 0.00% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 82 0.10% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21120-21127 1 0.00% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 14 0.02% 75.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 401 0.47% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 17 0.02% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 2 0.00% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 77 0.09% 75.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 1 0.00% 75.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 84 0.10% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 3 0.00% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 1 0.00% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 400 0.46% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 80 0.09% 76.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22976-22983 2 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 136 0.16% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 21 0.02% 76.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23360-23367 3 0.00% 76.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 2 0.00% 76.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 351 0.41% 76.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23687 2 0.00% 76.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 73 0.08% 77.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 83 0.10% 77.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 83 0.10% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 387 0.45% 77.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 78 0.09% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24960-24967 1 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25024-25031 1 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 89 0.10% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25287 1 0.00% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 72 0.08% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 4 0.00% 77.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 349 0.41% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 19 0.02% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 3 0.00% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 133 0.15% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 2 0.00% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 78 0.09% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 401 0.47% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26752-26759 2 0.00% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 82 0.10% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 77 0.09% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 1 0.00% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 15 0.02% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 403 0.47% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 11 0.01% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 2 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 83 0.10% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 97 0.11% 80.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 2 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 341 0.40% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28743 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 2 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 143 0.17% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29056-29063 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 77 0.09% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29248-29255 2 0.00% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 85 0.10% 80.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 3 0.00% 80.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 2 0.00% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 268 0.31% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 76 0.09% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 74 0.09% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 2 0.00% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 92 0.11% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 271 0.31% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 2 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 145 0.17% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 2 0.00% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 148 0.17% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31296-31303 1 0.00% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 19 0.02% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31687 4 0.00% 82.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 398 0.46% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31936-31943 1 0.00% 82.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 18 0.02% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 78 0.09% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 83 0.10% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 642 0.75% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32832-32839 2 0.00% 83.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 73 0.08% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 2 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 78 0.09% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 27 0.03% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 2 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 406 0.47% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 16 0.02% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 144 0.17% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 147 0.17% 84.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 269 0.31% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 87 0.10% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 72 0.08% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 2 0.00% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 77 0.09% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 268 0.31% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 81 0.09% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 77 0.09% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 1 0.00% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 144 0.17% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 2 0.00% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 338 0.39% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36992-36999 1 0.00% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 91 0.11% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 83 0.10% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37568-37575 1 0.00% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 11 0.01% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 404 0.47% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 15 0.02% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 1 0.00% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 77 0.09% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 1 0.00% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 84 0.10% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 401 0.47% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 2 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 130 0.15% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 15 0.02% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 348 0.40% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 3 0.00% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 71 0.08% 88.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 86 0.10% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 78 0.09% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 387 0.45% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 2 0.00% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 78 0.09% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41351 2 0.00% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 83 0.10% 89.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 347 0.40% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 18 0.02% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 133 0.15% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 3 0.00% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 79 0.09% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 399 0.46% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 82 0.10% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 76 0.09% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 20 0.02% 90.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 403 0.47% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 10 0.01% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 81 0.09% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 96 0.11% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 341 0.40% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 143 0.17% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 82 0.10% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 5 0.01% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 84 0.10% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 1 0.00% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 261 0.30% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 73 0.08% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 68 0.08% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 91 0.11% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 272 0.32% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 142 0.16% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 144 0.17% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 25 0.03% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 395 0.46% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 16 0.02% 93.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 76 0.09% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 71 0.08% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5013 5.82% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50368-50375 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51264-51271 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86114 # Bytes accessed per row activation +system.physmem.totQLat 365610387500 # Total ticks spent queuing +system.physmem.totMemAccLat 458189280000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17286802500 # Total ticks spent accessing banks +system.physmem.avgQLat 24279.47 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1147.98 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30427.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.00 # Data bus utilization in percentage +system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 12.84 # Average write queue length when enqueuing +system.physmem.readRowHits 14986740 # Number of row buffer hits during reads +system.physmem.writeRowHits 93410 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 86.60 # Row buffer hit rate for writes +system.physmem.avgGap 158714.15 # Average gap between requests +system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.73 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -440,50 +752,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54917647 # Throughput (bytes/s) +system.membus.throughput 54899945 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 16149440 # Transaction distribution system.membus.trans_dist::ReadResp 16149440 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59118 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution -system.membus.trans_dist::ReadExReq 131433 # Transaction distribution -system.membus.trans_dist::ReadExResp 131433 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 59125 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution +system.membus.trans_dist::ReadExReq 131442 # Transaction distribution +system.membus.trans_dist::ReadExResp 131442 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885779 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272485 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34156901 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694552 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092441 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138629141 # Total data (bytes) +system.membus.tot_pkt_size::total 138630105 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138630105 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486773500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3686000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17363455000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4733701508 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33738367951 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -491,13 +803,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48301509 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution -system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution +system.iobus.throughput 48285606 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution +system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution system.iobus.trans_dist::WriteResp 8157 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -519,12 +831,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32267358 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -546,14 +858,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390301 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121927961 # Total data (bytes) +system.iobus.tot_pkt_size::total 121927965 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121927965 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -599,42 +911,42 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921194049 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14390442 # Number of BP lookups -system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits +system.cpu.branchPred.lookups 14384905 # Number of BP lookups +system.cpu.branchPred.condPredicted 11471084 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 703956 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9467627 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7657685 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.882834 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1397242 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72494 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51188083 # DTB read hits -system.cpu.dtb.read_misses 64353 # DTB read misses -system.cpu.dtb.write_hits 11697459 # DTB write hits -system.cpu.dtb.write_misses 15788 # DTB write misses +system.cpu.dtb.read_hits 51179212 # DTB read hits +system.cpu.dtb.read_misses 64531 # DTB read misses +system.cpu.dtb.write_hits 11698539 # DTB write hits +system.cpu.dtb.write_misses 15837 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3561 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3571 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2411 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51252436 # DTB read accesses -system.cpu.dtb.write_accesses 11713247 # DTB write accesses +system.cpu.dtb.perms_faults 1396 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51243743 # DTB read accesses +system.cpu.dtb.write_accesses 11714376 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62885542 # DTB hits -system.cpu.dtb.misses 80141 # DTB misses -system.cpu.dtb.accesses 62965683 # DTB accesses -system.cpu.itb.inst_hits 11520428 # ITB inst hits -system.cpu.itb.inst_misses 11439 # ITB inst misses +system.cpu.dtb.hits 62877751 # DTB hits +system.cpu.dtb.misses 80368 # DTB misses +system.cpu.dtb.accesses 62958119 # DTB accesses +system.cpu.itb.inst_hits 11513998 # ITB inst hits +system.cpu.itb.inst_misses 11344 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -643,114 +955,114 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2486 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2483 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2968 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11531867 # ITB inst accesses -system.cpu.itb.hits 11520428 # DTB hits -system.cpu.itb.misses 11439 # DTB misses -system.cpu.itb.accesses 11531867 # DTB accesses -system.cpu.numCycles 473080437 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11525342 # ITB inst accesses +system.cpu.itb.hits 11513998 # DTB hits +system.cpu.itb.misses 11344 # DTB misses +system.cpu.itb.accesses 11525342 # DTB accesses +system.cpu.numCycles 474882944 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29745457 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90266235 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14384905 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9054927 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20140969 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4652912 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 123687 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96003967 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87891 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2685420 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11510536 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 707949 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5425 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.740543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.094686 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131871277 86.76% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1302073 0.86% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1710886 1.13% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295409 1.51% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2102442 1.38% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107607 0.73% 92.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555872 1.68% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 743971 0.49% 94.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307413 5.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432104229 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10389 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.532969 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.190081 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31502209 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98125273 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18366247 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 966197 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3037024 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1956644 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171990 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107262918 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568386 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3037024 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33252800 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39466554 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52672825 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17523888 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6043859 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102275198 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20557 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4063584 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106014240 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466907038 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432047963 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10635 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387438 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27626801 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830029 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736499 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12184256 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19715159 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13304037 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1977063 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2478152 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95106473 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1982467 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122897190 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166901 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18919534 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47250176 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500160 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151996950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.808550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.527901 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2809227 1.87% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127944 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108284402 71.24% 71.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13439431 8.84% 80.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6944257 4.57% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5857722 3.85% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12372410 8.14% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2808060 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1695891 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467423 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127354 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151996950 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62444 0.71% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available @@ -778,13 +1090,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8371933 94.63% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412257 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57615534 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93100 0.08% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued @@ -797,397 +1109,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 33 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 25 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2115 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 25 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52504661 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12318028 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued -system.cpu.iq.rate 0.259812 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122897190 # Type of FU issued +system.cpu.iq.rate 0.258795 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8846641 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071984 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406861293 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116024937 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85463742 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23592 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12620 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10347 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131367569 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12596 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623590 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4061151 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6344 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30249 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1572309 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107765 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 681284 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3037024 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30702730 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434457 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97310809 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203906 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19715159 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13304037 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1409970 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113496 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3538 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30249 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349429 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269322 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 618751 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120821579 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51866256 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2075611 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221034 # number of nop insts executed -system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed -system.cpu.iew.exec_branches 11474602 # Number of branches executed -system.cpu.iew.exec_stores 12209197 # Number of stores executed -system.cpu.iew.exec_rate 0.255417 # Inst execution rate -system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47030253 # num instructions producing a value -system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value +system.cpu.iew.exec_nop 221869 # number of nop insts executed +system.cpu.iew.exec_refs 64076774 # number of memory reference insts executed +system.cpu.iew.exec_branches 11475076 # Number of branches executed +system.cpu.iew.exec_stores 12210518 # Number of stores executed +system.cpu.iew.exec_rate 0.254424 # Inst execution rate +system.cpu.iew.wb_sent 119883669 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85474089 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47026181 # num instructions producing a value +system.cpu.iew.wb_consumers 87876552 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179990 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535139 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18658160 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534513 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148959926 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.510472 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121529130 81.59% 81.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13302723 8.93% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3899356 2.62% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2115942 1.42% 94.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1939571 1.30% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 978607 0.66% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1596110 1.07% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718014 0.48% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2880473 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60455941 # Number of instructions committed -system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148959926 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456137 # Number of instructions committed +system.cpu.commit.committedOps 77747122 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385481 # Number of memory references committed -system.cpu.commit.loads 15653838 # Number of loads committed -system.cpu.commit.membars 403568 # Number of memory barriers committed -system.cpu.commit.branches 9961054 # Number of branches committed +system.cpu.commit.refs 27385736 # Number of memory references committed +system.cpu.commit.loads 15654008 # Number of loads committed +system.cpu.commit.membars 403573 # Number of memory barriers committed +system.cpu.commit.branches 9961077 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852229 # Number of committed integer instructions. -system.cpu.commit.function_calls 991205 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852562 # Number of committed integer instructions. +system.cpu.commit.function_calls 991208 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2880473 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 239241509 # The number of ROB reads -system.cpu.rob.rob_writes 195965670 # The number of ROB writes -system.cpu.timesIdled 1778644 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322490663 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575455632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305560 # Number of Instructions Simulated -system.cpu.committedOps 77596391 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305560 # Number of Instructions Simulated -system.cpu.cpi 7.844723 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.844723 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127474 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127474 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547265501 # number of integer regfile reads -system.cpu.int_regfile_writes 87536109 # number of integer regfile writes -system.cpu.fp_regfile_reads 8349 # number of floating regfile reads -system.cpu.fp_regfile_writes 2916 # number of floating regfile writes -system.cpu.misc_regfile_reads 30123194 # number of misc regfile reads -system.cpu.misc_regfile_writes 831835 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58892076 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2657368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2657367 # Transaction distribution +system.cpu.rob.rob_reads 240636318 # The number of ROB reads +system.cpu.rob.rob_writes 195934369 # The number of ROB writes +system.cpu.timesIdled 1776906 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322885994 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575316115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305756 # Number of Instructions Simulated +system.cpu.committedOps 77596741 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305756 # Number of Instructions Simulated +system.cpu.cpi 7.874587 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.874587 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126991 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126991 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547208469 # number of integer regfile reads +system.cpu.int_regfile_writes 87526188 # number of integer regfile writes +system.cpu.fp_regfile_reads 8624 # number of floating regfile reads +system.cpu.fp_regfile_writes 3008 # number of floating regfile writes +system.cpu.misc_regfile_reads 30165107 # number of misc regfile reads +system.cpu.misc_regfile_writes 831837 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58889875 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658094 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658093 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607699 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246095 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246095 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959479 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796858 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30970 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7914210 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62665920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85541397 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42108 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148459049 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148459049 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 202780 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128672900 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246142 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246142 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961671 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796233 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31091 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128199 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7917194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62737088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85515993 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148510785 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148510785 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 194456 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128799181 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1473318251 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474440753 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2559248308 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550199081 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20450735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20321978 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74607301 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74655295 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 979660 # number of replacements -system.cpu.icache.tags.tagsinuse 511.583533 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10456897 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 980172 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.668431 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6854161250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.583533 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999187 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999187 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10456897 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10456897 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10456897 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10456897 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10456897 # number of overall hits -system.cpu.icache.overall_hits::total 10456897 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059959 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059959 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059959 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059959 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059959 # number of overall misses -system.cpu.icache.overall_misses::total 1059959 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14263664434 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14263664434 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14263664434 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14263664434 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14263664434 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14263664434 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11516856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11516856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11516856 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11516856 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11516856 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11516856 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092035 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092035 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092035 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092035 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092035 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092035 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13456.807701 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13456.807701 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13456.807701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13456.807701 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7134 # number of cycles access was blocked +system.cpu.icache.tags.replacements 980741 # number of replacements +system.cpu.icache.tags.tagsinuse 511.579116 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10449649 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981253 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.649291 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.579116 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10449649 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10449649 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10449649 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10449649 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10449649 # number of overall hits +system.cpu.icache.overall_hits::total 10449649 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060761 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060761 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060761 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060761 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060761 # number of overall misses +system.cpu.icache.overall_misses::total 1060761 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273214680 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14273214680 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14273214680 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14273214680 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14273214680 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14273214680 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11510410 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11510410 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11510410 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11510410 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11510410 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11510410 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092157 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092157 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092157 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092157 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092157 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092157 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13455.636736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13455.636736 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6677 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 370 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 323 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.281081 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.671827 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79754 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79754 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79754 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79754 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79754 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79754 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980205 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980205 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980205 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980205 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980205 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980205 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11579661493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11579661493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11579661493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11579661493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11579661493 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11579661493 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8708000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8708000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8708000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8708000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085110 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085110 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085110 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11813.509922 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11813.509922 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79476 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79476 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79476 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79476 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79476 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79476 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981285 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981285 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981285 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981285 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981285 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981285 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587356987 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11587356987 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587356987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11587356987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587356987 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11587356987 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8658250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8658250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8658250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8658250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085252 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085252 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085252 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.350262 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.350262 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64363 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51374.109919 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1885226 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129755 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.529120 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2489241302000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36927.111680 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 38.632288 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000370 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.183198 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.182382 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563463 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000589 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 64371 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51366.694603 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1888244 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129769 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.550810 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2490009951000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36925.668640 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 27.934134 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.003945 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.587712 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6237.500172 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563441 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124713 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.095141 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.783907 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52355 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10525 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 966696 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387308 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1416884 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607864 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607864 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.095177 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.783794 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53605 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10777 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 967799 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387031 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1419212 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607699 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607699 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112905 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112905 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52355 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10525 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 966696 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 500213 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1529789 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52355 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10525 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 966696 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 500213 # number of overall hits -system.cpu.l2cache.overall_hits::total 1529789 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 51 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12341 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10723 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23117 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2916 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2916 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133190 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133190 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 51 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12341 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143913 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156307 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 51 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12341 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143913 # number of overall misses -system.cpu.l2cache.overall_misses::total 156307 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4640000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 130250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 910966750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 788627999 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1704364999 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395483 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 395483 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9130512743 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9130512743 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4640000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 130250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 910966750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9919140742 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10834877742 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4640000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 130250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 910966750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9919140742 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10834877742 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52406 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10527 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979037 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 398031 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1440001 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607864 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607864 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 112944 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112944 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 53605 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10777 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 967799 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 499975 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1532156 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 53605 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10777 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 967799 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 499975 # number of overall hits +system.cpu.l2cache.overall_hits::total 1532156 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12350 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10721 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23115 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2915 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2915 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133198 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133198 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12350 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143919 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156313 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 12350 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143919 # number of overall misses +system.cpu.l2cache.overall_misses::total 156313 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3352500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 233000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 906466500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 812441248 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1722493248 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 465980 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 465980 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10117185994 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10117185994 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3352500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 233000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 906466500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10929627242 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11839679242 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3352500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 233000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 906466500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10929627242 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11839679242 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53646 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10780 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 980149 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397752 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1442327 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607699 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607699 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2955 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2955 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 11 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246095 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246095 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52406 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10527 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 979037 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 644126 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1686096 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52406 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10527 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979037 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 644126 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1686096 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000973 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012605 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026940 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016053 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986802 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986802 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.181818 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.181818 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541214 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541214 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000973 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012605 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223424 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092703 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000973 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012605 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223424 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092703 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 90980.392157 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65125 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73816.283121 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73545.462930 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73727.776052 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 135.625171 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 135.625171 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68552.539553 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68552.539553 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69317.930368 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69317.930368 # average overall miss latency +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246142 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246142 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53646 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10780 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 980149 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643894 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1688469 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53646 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10780 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 980149 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643894 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1688469 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000764 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000278 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012600 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026954 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016026 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986464 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986464 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541143 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541143 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000764 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000278 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012600 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223513 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092577 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000764 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000278 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012600 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223513 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092577 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81768.292683 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77666.666667 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73398.097166 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75780.360787 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74518.418689 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.855918 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.855918 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75955.990285 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75955.990285 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75743.407407 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75743.407407 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1196,109 +1508,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59118 # number of writebacks -system.cpu.l2cache.writebacks::total 59118 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 59125 # number of writebacks +system.cpu.l2cache.writebacks::total 59125 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 51 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12329 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10658 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23040 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2916 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2916 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133190 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133190 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 51 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12329 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143848 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156230 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 51 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12329 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143848 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156230 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3990500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 105750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 754066500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 649417249 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1407579999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29164415 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29164415 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7443119257 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7443119257 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3990500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 105750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 754066500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8092536506 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8850699256 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3990500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 105750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 754066500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8092536506 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8850699256 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6234999 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166923461500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166929696499 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17446167056 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17446167056 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6234999 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184369628556 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184375863555 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026777 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016000 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986802 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986802 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.181818 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541214 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541214 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092658 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092658 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52875 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61162.016384 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60932.374648 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61092.881901 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.514060 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.514060 # average UpgradeReq mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12339 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23039 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2915 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2915 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133198 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133198 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12339 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143854 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156237 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12339 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143854 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156237 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2846500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 196000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 750549750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 675500748 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1429092998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29153914 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29153914 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8456317006 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8456317006 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2846500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 196000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 750549750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9131817754 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9885410004 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2846500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 196000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 750549750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9131817754 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9885410004 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6187249 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166934965500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941152749 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17442637817 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17442637817 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6187249 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377603317 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383790566 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026791 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015973 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986464 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986464 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541143 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541143 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092532 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092532 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.437394 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63391.586712 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62029.298060 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55883.469157 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55883.469157 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63486.816664 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63486.816664 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1308,161 +1620,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643614 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993425 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21512206 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 644126 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.397512 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 41599250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993425 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 643382 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21503755 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643894 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.396421 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13760275 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13760275 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258497 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258497 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242759 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242759 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247596 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247596 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21018772 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21018772 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21018772 # number of overall hits -system.cpu.dcache.overall_hits::total 21018772 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737490 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737490 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963456 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963456 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700946 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700946 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700946 # number of overall misses -system.cpu.dcache.overall_misses::total 3700946 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9976636292 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9976636292 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 134760113834 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 134760113834 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184874750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 184874750 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 168002 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 168002 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144736750126 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144736750126 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144736750126 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144736750126 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14497765 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14497765 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10221953 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10221953 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256268 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 13751955 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13751955 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258296 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258296 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242828 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242828 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21010251 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21010251 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21010251 # number of overall hits +system.cpu.dcache.overall_hits::total 21010251 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737736 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737736 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963735 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963735 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13555 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13555 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3701471 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3701471 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3701471 # number of overall misses +system.cpu.dcache.overall_misses::total 3701471 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10012711310 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10012711310 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 141368125836 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 141368125836 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185715250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185715250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 151380837146 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 151380837146 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 151380837146 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 151380837146 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14489691 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14489691 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222031 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222031 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256383 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256383 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24719718 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24719718 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24719718 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24719718 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050869 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050869 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289911 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289911 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052714 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052714 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149716 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149716 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149716 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149716 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13527.825858 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13527.825858 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45473.971550 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45473.971550 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.302391 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.302391 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15272.909091 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15272.909091 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39108.041600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39108.041600 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 31555 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 26598 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2653 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.894082 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 95.333333 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 24711722 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24711722 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24711722 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24711722 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050915 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050915 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289936 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289936 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052870 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052870 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149786 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149786 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149786 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149786 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13572.214600 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40897.480257 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40897.480257 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33174 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2643 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.551646 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 96.491228 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607864 # number of writebacks -system.cpu.dcache.writebacks::total 607864 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351528 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351528 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714505 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714505 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3066033 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3066033 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3066033 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3066033 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385962 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385962 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248951 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248951 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12168 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12168 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634913 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634913 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634913 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634913 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4950861635 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4950861635 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10610319031 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10610319031 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144937500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144937500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 145998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 145998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15561180666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15561180666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15561180666 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15561180666 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182316666500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182316666500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26837116532 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26837116532 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209153783032 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209153783032 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026622 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047482 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047482 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025684 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025684 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12827.329206 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12827.329206 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42620.110106 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42620.110106 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11911.365878 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.365878 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607699 # number of writebacks +system.cpu.dcache.writebacks::total 607699 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 352116 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 352116 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714717 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714717 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3066833 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3066833 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3066833 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3066833 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385620 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385620 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249018 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249018 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4970319128 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4970319128 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11601864538 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11601864538 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572183666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16572183666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572183666 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16572183666 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328180000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328180000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841518267 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841518267 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169698267 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169698267 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024361 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024361 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047628 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047628 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1484,10 +1796,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499087755049 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 2afd1181d..506582551 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,182 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403596 # Number of seconds simulated -sim_ticks 2403595690000 # Number of ticks simulated -final_tick 2403595690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403658 # Number of seconds simulated +sim_ticks 2403657545000 # Number of ticks simulated +final_tick 2403657545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196358 # Simulator instruction rate (inst/s) -host_op_rate 252199 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7823307249 # Simulator tick rate (ticks/s) -host_mem_usage 401444 # Number of bytes of host memory used -host_seconds 307.24 # Real time elapsed on the host -sim_insts 60328186 # Number of instructions simulated -sim_ops 77484426 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 183148 # Simulator instruction rate (inst/s) +host_op_rate 235229 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7297160965 # Simulator tick rate (ticks/s) +host_mem_usage 427808 # Number of bytes of host memory used +host_seconds 329.40 # Real time elapsed on the host +sim_insts 60328152 # Number of instructions simulated +sim_ops 77483430 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 511520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7050896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 512416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7048656 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 64832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 677568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 64128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 675392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 704 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 187392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1347680 # Number of bytes read from this memory -system.physmem.bytes_read::total 124659728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 511520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu2.data 1353632 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 512416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 64128 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 187392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743680 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298324 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159300 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759496 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 763936 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3744384 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298192 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159304 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558320 # Number of bytes written to this memory +system.physmem.bytes_written::total 6760200 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14195 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110204 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14209 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110169 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1013 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10587 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1002 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10553 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 11 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 2928 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 21065 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512388 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58495 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324581 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39825 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389548 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812449 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47769711 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.data 21158 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512418 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58506 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324548 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39826 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 389580 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812460 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47768482 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 212814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2933478 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2932471 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 281898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77963 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 560693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51863851 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 212814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26973 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77963 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317751 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557533 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 280985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 77961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 563155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51863315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26679 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 77961 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557786 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540090 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 66276 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2812243 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47769711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648312 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2812464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47768482 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 212814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3473637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3472561 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 348173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1208969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54676094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13479442 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 446461 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 13479442 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 446461 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 862684288 # Total number of bytes read from memory -system.physmem.bytesWritten 28573504 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 109828768 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2811124 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 2349 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 837727 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 837365 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 837535 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 838843 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 839834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 839919 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 839832 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 840753 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 841921 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 844340 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 845026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 846543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 848256 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 848014 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 846904 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 846630 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2743 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2603 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2565 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 3057 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 3449 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 3230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2572 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2333 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 2233 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2428 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 2377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 3826 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 3451 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2698 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2556 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2402560453500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 8 # Categorize read packet sizes -system.physmem.readPktSize::3 13443840 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 35594 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 429373 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17088 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 871692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 848345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 868847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3321058 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2492431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2492072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2465727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 13654 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 13341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 25821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 38140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 25648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 671 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.bw_total::cpu1.inst 26679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 347261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 77961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1211467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54675779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13467317 # Number of read requests accepted +system.physmem.writeReqs 446508 # Number of write requests accepted +system.physmem.readBursts 13467317 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446508 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 861908288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 2866432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109734624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2812152 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 401719 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2372 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 837719 # Per bank write bursts +system.physmem.perBankRdBursts::1 837389 # Per bank write bursts +system.physmem.perBankRdBursts::2 837556 # Per bank write bursts +system.physmem.perBankRdBursts::3 837999 # Per bank write bursts +system.physmem.perBankRdBursts::4 838842 # Per bank write bursts +system.physmem.perBankRdBursts::5 838880 # Per bank write bursts +system.physmem.perBankRdBursts::6 838796 # Per bank write bursts +system.physmem.perBankRdBursts::7 839742 # Per bank write bursts +system.physmem.perBankRdBursts::8 840911 # Per bank write bursts +system.physmem.perBankRdBursts::9 843323 # Per bank write bursts +system.physmem.perBankRdBursts::10 844015 # Per bank write bursts +system.physmem.perBankRdBursts::11 845500 # Per bank write bursts +system.physmem.perBankRdBursts::12 847242 # Per bank write bursts +system.physmem.perBankRdBursts::13 846993 # Per bank write bursts +system.physmem.perBankRdBursts::14 845867 # Per bank write bursts +system.physmem.perBankRdBursts::15 846543 # Per bank write bursts +system.physmem.perBankWrBursts::0 2729 # Per bank write bursts +system.physmem.perBankWrBursts::1 2587 # Per bank write bursts +system.physmem.perBankWrBursts::2 2574 # Per bank write bursts +system.physmem.perBankWrBursts::3 3045 # Per bank write bursts +system.physmem.perBankWrBursts::4 3468 # Per bank write bursts +system.physmem.perBankWrBursts::5 3206 # Per bank write bursts +system.physmem.perBankWrBursts::6 2544 # Per bank write bursts +system.physmem.perBankWrBursts::7 2321 # Per bank write bursts +system.physmem.perBankWrBursts::8 2236 # Per bank write bursts +system.physmem.perBankWrBursts::9 2427 # Per bank write bursts +system.physmem.perBankWrBursts::10 2367 # Per bank write bursts +system.physmem.perBankWrBursts::11 2798 # Per bank write bursts +system.physmem.perBankWrBursts::12 3813 # Per bank write bursts +system.physmem.perBankWrBursts::13 3444 # Per bank write bursts +system.physmem.perBankWrBursts::14 2680 # Per bank write bursts +system.physmem.perBankWrBursts::15 2549 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2402622305000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 8 # Read request sizes (log2) +system.physmem.readPktSize::3 13431664 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 35645 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 429406 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 17102 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 965936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 943404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 937737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3274872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2367219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2366833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2384991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 47923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 55146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 17633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 17612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 17582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -190,30 +176,30 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 28 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -222,473 +208,633 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 22080 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 39201.023188 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 6463.207550 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31878.388388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-79 3036 13.75% 13.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-143 1347 6.10% 19.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-207 793 3.59% 23.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-271 589 2.67% 26.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-335 391 1.77% 27.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-399 355 1.61% 29.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-463 279 1.26% 30.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-527 235 1.06% 31.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-591 172 0.78% 32.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-655 146 0.66% 33.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-719 130 0.59% 33.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-783 164 0.74% 34.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-847 77 0.35% 34.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-911 80 0.36% 35.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-975 63 0.29% 35.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1039 74 0.34% 35.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1103 30 0.14% 36.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1167 39 0.18% 36.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1231 22 0.10% 36.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1295 39 0.18% 36.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1359 28 0.13% 36.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1423 83 0.38% 37.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1487 95 0.43% 37.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1551 108 0.49% 37.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1615 17 0.08% 38.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1679 45 0.20% 38.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1743 23 0.10% 38.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1807 32 0.14% 38.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1871 10 0.05% 38.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1935 20 0.09% 38.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1999 6 0.03% 38.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2063 23 0.10% 38.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2127 8 0.04% 38.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2191 15 0.07% 38.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2255 1 0.00% 38.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2319 6 0.03% 38.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2383 4 0.02% 38.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2447 10 0.05% 38.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2511 3 0.01% 38.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2575 2 0.01% 38.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2639 1 0.00% 38.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2703 3 0.01% 38.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2767 5 0.02% 38.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2831 8 0.04% 39.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2895 3 0.01% 39.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2959 3 0.01% 39.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3023 1 0.00% 39.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3087 6 0.03% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3151 2 0.01% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3215 2 0.01% 39.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3279 5 0.02% 39.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3343 6 0.03% 39.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3407 2 0.01% 39.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3471 3 0.01% 39.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3535 1 0.00% 39.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3599 2 0.01% 39.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3663 2 0.01% 39.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3727 2 0.01% 39.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3791 3 0.01% 39.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3855 1 0.00% 39.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4047 3 0.01% 39.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4111 7 0.03% 39.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4367 3 0.01% 39.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4431 1 0.00% 39.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4687 2 0.01% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4815 2 0.01% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4943 1 0.00% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5007 2 0.01% 39.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5135 1 0.00% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5391 2 0.01% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5455 1 0.00% 39.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6287 1 0.00% 39.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6479 1 0.00% 39.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6543 3 0.01% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6799 15 0.07% 39.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6863 2 0.01% 39.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6991 1 0.00% 39.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7055 3 0.01% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7183 3 0.01% 39.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7375 2 0.01% 39.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7439 1 0.00% 39.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7695 1 0.00% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7759 1 0.00% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7951 2 0.01% 39.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8079 1 0.00% 39.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8207 3 0.01% 39.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8463 45 0.20% 39.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8527 150 0.68% 40.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8591 12 0.05% 40.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8975 1 0.00% 40.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9231 1 0.00% 40.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9487 1 0.00% 40.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12047 2 0.01% 40.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14863 1 0.00% 40.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16335 1 0.00% 40.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17423 1 0.00% 40.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17679 1 0.00% 40.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20239 1 0.00% 40.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22799 1 0.00% 40.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24591 1 0.00% 40.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25871 1 0.00% 40.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27663 1 0.00% 40.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29455 1 0.00% 40.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30735 2 0.01% 40.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31247 1 0.00% 40.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33039 1 0.00% 40.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33295 3 0.01% 40.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33807 1 0.00% 40.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34319 1 0.00% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34831 1 0.00% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35855 1 0.00% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37903 1 0.00% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38927 1 0.00% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40207 1 0.00% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40975 1 0.00% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41999 1 0.00% 40.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42767 1 0.00% 40.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47887 1 0.00% 40.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52239 1 0.00% 40.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53263 1 0.00% 40.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53504-53519 1 0.00% 40.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56064-56079 1 0.00% 40.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59407 1 0.00% 40.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65551 13109 59.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22080 # Bytes accessed per row activation -system.physmem.totQLat 259652718750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 339530350000 # Sum of mem lat for all requests -system.physmem.totBusLat 67397210000 # Total cycles spent in databus access -system.physmem.totBankLat 12480421250 # Total cycles spent in bank access -system.physmem.avgQLat 19262.87 # Average queueing delay per request -system.physmem.avgBankLat 925.89 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25188.75 # Average memory access latency -system.physmem.avgRdBW 358.91 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 11.89 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 45.69 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.17 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.90 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 13462207 # Number of row buffer hits during reads -system.physmem.writeRowHits 40077 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 8.98 # Row buffer hit rate for writes -system.physmem.avgGap 172524.57 # Average gap between requests -system.membus.throughput 55673401 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13817014 # Transaction distribution -system.membus.trans_dist::ReadResp 13817014 # Transaction distribution -system.membus.trans_dist::WriteReq 432240 # Transaction distribution -system.membus.trans_dist::WriteResp 432240 # Transaction distribution -system.membus.trans_dist::Writeback 17088 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2349 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2349 # Transaction distribution -system.membus.trans_dist::ReadExReq 28007 # Transaction distribution -system.membus.trans_dist::ReadExResp 28007 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736658 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 234 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951736 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1688628 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26887680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26887680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28576308 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740538 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 468 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5089172 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5830178 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107550720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107550720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113380898 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133816346 # Total data (bytes) +system.physmem.bytesPerActivate::samples 48451 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 17848.429795 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 3200.071202 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 18346.519598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 8608 17.77% 17.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 4824 9.96% 27.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 1006 2.08% 29.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 654 1.35% 31.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 399 0.82% 31.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 406 0.84% 32.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 283 0.58% 33.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 297 0.61% 34.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 176 0.36% 34.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 170 0.35% 34.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 172 0.35% 35.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 155 0.32% 35.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 77 0.16% 35.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 80 0.17% 35.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 48 0.10% 35.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 416 0.86% 36.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 18 0.04% 36.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 23 0.05% 36.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 23 0.05% 36.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 108 0.22% 37.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 17 0.04% 37.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 165 0.34% 37.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 12 0.02% 37.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 112 0.23% 37.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 15 0.03% 37.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 32 0.07% 37.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 7 0.01% 37.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 140 0.29% 38.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 6 0.01% 38.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 13 0.03% 38.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 8 0.02% 38.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 455 0.94% 39.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 3 0.01% 39.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 12 0.02% 39.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 2 0.00% 39.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 72 0.15% 39.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 6 0.01% 39.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 4 0.01% 39.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 2 0.00% 39.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 5 0.01% 39.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 6 0.01% 39.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 3 0.01% 39.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 5 0.01% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 10 0.02% 39.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 5 0.01% 39.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 8 0.02% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 2 0.00% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 505 1.04% 40.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 5 0.01% 40.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 5 0.01% 40.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 65 0.13% 40.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 6 0.01% 40.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 5 0.01% 40.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 9 0.02% 40.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 15 0.03% 40.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 3 0.01% 40.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 4 0.01% 40.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 6 0.01% 40.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 66 0.14% 40.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 4 0.01% 40.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 6 0.01% 40.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 3 0.01% 40.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 327 0.67% 41.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 5 0.01% 41.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 8 0.02% 41.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 2 0.00% 41.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 130 0.27% 41.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 6 0.01% 41.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 4 0.01% 41.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 3 0.01% 41.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 68 0.14% 41.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 3 0.01% 41.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 2 0.00% 41.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 5 0.01% 41.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 4 0.01% 42.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 4 0.01% 42.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 4 0.01% 42.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 7 0.01% 42.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 258 0.53% 42.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 42.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 4 0.01% 42.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 3 0.01% 42.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 88 0.18% 42.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 3 0.01% 42.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 8 0.02% 42.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.01% 42.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 92 0.19% 42.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 4 0.01% 43.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 7 0.01% 43.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 2 0.00% 43.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 102 0.21% 43.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 2 0.00% 43.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 3 0.01% 43.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 10 0.02% 43.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 481 0.99% 44.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 2 0.00% 44.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 3 0.01% 44.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 1 0.00% 44.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 3 0.01% 44.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 2 0.00% 44.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 67 0.14% 44.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 5 0.01% 44.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 6 0.01% 44.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 131 0.27% 44.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 1 0.00% 44.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 1 0.00% 44.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 3 0.01% 44.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 72 0.15% 44.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 1 0.00% 44.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 2 0.00% 44.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 13 0.03% 44.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 133 0.27% 45.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 66 0.14% 45.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 64 0.13% 45.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 385 0.79% 46.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 65 0.13% 46.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 65 0.13% 46.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 128 0.26% 46.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 73 0.15% 46.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 128 0.26% 47.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 64 0.13% 47.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 1 0.00% 47.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 478 0.99% 48.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 63 0.13% 48.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 1 0.00% 48.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 89 0.18% 48.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 86 0.18% 48.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 257 0.53% 49.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 1 0.00% 49.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 65 0.13% 49.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 128 0.26% 49.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 320 0.66% 50.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 64 0.13% 50.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 14 0.03% 50.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 50.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 64 0.13% 50.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 499 1.03% 51.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 64 0.13% 51.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 442 0.91% 52.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 128 0.26% 53.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 66 0.14% 53.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 72 0.15% 53.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 362 0.75% 54.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 2 0.00% 54.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 6 0.01% 54.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 781 1.61% 55.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 7 0.01% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 1 0.00% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 1 0.00% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 362 0.75% 56.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 72 0.15% 56.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 64 0.13% 56.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 128 0.26% 56.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 57.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 1 0.00% 57.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 442 0.91% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 64 0.13% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 1 0.00% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 499 1.03% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 64 0.13% 59.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 12 0.02% 59.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 66 0.14% 59.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 320 0.66% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 128 0.26% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 64 0.13% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 256 0.53% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 85 0.18% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 87 0.18% 61.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 64 0.13% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 478 0.99% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 67 0.14% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 128 0.26% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 71 0.15% 62.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 129 0.27% 63.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 64 0.13% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 64 0.13% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 384 0.79% 64.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 64 0.13% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 64 0.13% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 129 0.27% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 70 0.14% 64.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 128 0.26% 65.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26048-26055 1 0.00% 65.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 66 0.14% 65.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 480 0.99% 66.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 64 0.13% 66.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 89 0.18% 66.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 86 0.18% 66.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 256 0.53% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 1 0.00% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 65 0.13% 67.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 1 0.00% 67.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 127 0.26% 67.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 320 0.66% 68.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 65 0.13% 68.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 13 0.03% 68.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 64 0.13% 68.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 497 1.03% 69.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 69.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 64 0.13% 69.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 442 0.91% 70.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 1 0.00% 70.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 129 0.27% 71.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 65 0.13% 71.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 72 0.15% 71.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 362 0.75% 72.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 1 0.00% 72.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 72.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 6 0.01% 72.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 778 1.61% 73.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 5 0.01% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 1 0.00% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 2 0.00% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 362 0.75% 74.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 72 0.15% 74.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 66 0.14% 74.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34688-34695 1 0.00% 75.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 443 0.91% 75.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 64 0.13% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 1 0.00% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 499 1.03% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 64 0.13% 77.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 13 0.03% 77.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 65 0.13% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 321 0.66% 78.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 127 0.26% 78.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 78.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 64 0.13% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 1 0.00% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 257 0.53% 79.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 1 0.00% 79.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 86 0.18% 79.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 89 0.18% 79.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 479 0.99% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 65 0.13% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39488-39495 1 0.00% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 128 0.26% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 71 0.15% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 128 0.26% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 64 0.13% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 64 0.13% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 384 0.79% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 64 0.13% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 64 0.13% 82.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 129 0.27% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 71 0.15% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 128 0.26% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 67 0.14% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 477 0.98% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 64 0.13% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 87 0.18% 84.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 84 0.17% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 256 0.53% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 64 0.13% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 128 0.26% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 320 0.66% 86.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 65 0.13% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 12 0.02% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 64 0.13% 86.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 498 1.03% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 1 0.00% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 64 0.13% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 443 0.91% 88.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 128 0.26% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 66 0.14% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 72 0.15% 89.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 362 0.75% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 2 0.00% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 2 0.00% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 1 0.00% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 7 0.01% 90.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 1 0.00% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 4749 9.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48451 # Bytes accessed per row activation +system.physmem.totQLat 326245474250 # Total ticks spent queuing +system.physmem.totMemAccLat 407559786750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67336585000 # Total ticks spent in databus transfers +system.physmem.totBankLat 13977727500 # Total ticks spent accessing banks +system.physmem.avgQLat 24224.98 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1037.90 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30262.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.81 # Data bus utilization in percentage +system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.37 # Average write queue length when enqueuing +system.physmem.readRowHits 13424164 # Number of row buffer hits during reads +system.physmem.writeRowHits 39490 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 88.17 # Row buffer hit rate for writes +system.physmem.avgGap 172678.78 # Average gap between requests +system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.76 # Percentage of time for which DRAM has all the banks in precharge state +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55673060 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13803640 # Transaction distribution +system.membus.trans_dist::ReadResp 13803640 # Transaction distribution +system.membus.trans_dist::WriteReq 432247 # Transaction distribution +system.membus.trans_dist::WriteResp 432247 # Transaction distribution +system.membus.trans_dist::Writeback 17102 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2372 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2372 # Transaction distribution +system.membus.trans_dist::ReadExReq 28053 # Transaction distribution +system.membus.trans_dist::ReadExResp 28053 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 734214 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1686398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26863328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26863328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28549726 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 738102 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5093464 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5832006 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107453312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107453312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113285318 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133818970 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 415555000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 417653000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 219000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 209500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14607219000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14595653500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1602404901 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1597948868 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 30345557250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 30334798000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 63232 # number of replacements -system.l2c.tags.tagsinuse 50385.545216 # Cycle average of tags in use -system.l2c.tags.total_refs 1748703 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128626 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.595253 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375561795000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36863.517049 # Average occupied blocks per requestor +system.l2c.tags.replacements 63262 # number of replacements +system.l2c.tags.tagsinuse 50391.923695 # Cycle average of tags in use +system.l2c.tags.total_refs 1749292 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128659 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.596344 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375568862000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36846.357046 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5225.910742 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3838.689123 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 514.601539 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 693.553663 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.833611 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.974677 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1665.560742 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1574.910611 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562493 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5224.016956 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3834.498559 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 503.830830 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 691.484420 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.832714 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1696.766805 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1584.142905 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562231 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079741 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058574 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079712 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058510 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007852 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010583 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000104 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025414 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024031 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768822 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 8792 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3229 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 468268 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 177348 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2569 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1162 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 128925 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64565 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18612 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4274 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 281840 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 131110 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1290694 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597529 # number of Writeback hits -system.l2c.Writeback_hits::total 597529 # number of Writeback hits +system.l2c.tags.occ_percent::cpu1.inst 0.007688 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010551 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000150 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025891 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024172 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768920 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 8708 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3160 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 467622 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 176862 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2604 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1190 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 130139 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 64269 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18599 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4205 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 281217 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 132179 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1290754 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597747 # number of Writeback hits +system.l2c.Writeback_hits::total 597747 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 11 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 61796 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 18660 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33186 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113642 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8792 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3229 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 468268 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 239144 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2569 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1162 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 128925 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 83225 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18612 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4274 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 281840 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 164296 # number of demand (read+write) hits -system.l2c.demand_hits::total 1404336 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8792 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3229 # number of overall hits -system.l2c.overall_hits::cpu0.inst 468268 # number of overall hits -system.l2c.overall_hits::cpu0.data 239144 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2569 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1162 # number of overall hits -system.l2c.overall_hits::cpu1.inst 128925 # number of overall hits -system.l2c.overall_hits::cpu1.data 83225 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 18612 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4274 # number of overall hits -system.l2c.overall_hits::cpu2.inst 281840 # number of overall hits -system.l2c.overall_hits::cpu2.data 164296 # number of overall hits -system.l2c.overall_hits::total 1404336 # number of overall hits +system.l2c.UpgradeReq_hits::cpu2.data 14 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 32 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 61947 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 18483 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 33173 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113603 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8708 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3160 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 467622 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 238809 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 2604 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1190 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 130139 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 82752 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 18599 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 4205 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 281217 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 165352 # number of demand (read+write) hits +system.l2c.demand_hits::total 1404357 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8708 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3160 # number of overall hits +system.l2c.overall_hits::cpu0.inst 467622 # number of overall hits +system.l2c.overall_hits::cpu0.data 238809 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2604 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1190 # number of overall hits +system.l2c.overall_hits::cpu1.inst 130139 # number of overall hits +system.l2c.overall_hits::cpu1.data 82752 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 18599 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 4205 # number of overall hits +system.l2c.overall_hits::cpu2.inst 281217 # number of overall hits +system.l2c.overall_hits::cpu2.data 165352 # number of overall hits +system.l2c.overall_hits::total 1404357 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7579 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6466 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7593 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6471 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1013 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1126 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1002 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1122 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 11 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.inst 2929 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2523 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21648 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1417 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 474 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 1014 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 104500 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9736 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 19132 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133368 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu2.data 2540 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21672 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1412 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 467 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 1028 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2907 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 104452 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9703 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 19227 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133382 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7579 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 110966 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7593 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 110923 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1013 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10862 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 7 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1002 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10825 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 11 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.inst 2929 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 21655 # number of demand (read+write) misses -system.l2c.demand_misses::total 155016 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 21767 # number of demand (read+write) misses +system.l2c.demand_misses::total 155054 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7579 # number of overall misses -system.l2c.overall_misses::cpu0.data 110966 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7593 # number of overall misses +system.l2c.overall_misses::cpu0.data 110923 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1013 # number of overall misses -system.l2c.overall_misses::cpu1.data 10862 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 7 # number of overall misses -system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1002 # number of overall misses +system.l2c.overall_misses::cpu1.data 10825 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 11 # number of overall misses system.l2c.overall_misses::cpu2.inst 2929 # number of overall misses -system.l2c.overall_misses::cpu2.data 21655 # number of overall misses -system.l2c.overall_misses::total 155016 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 75420750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 83519750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 595250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.itb.walker 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 229132750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 191859499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 580705499 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu2.data 21767 # number of overall misses +system.l2c.overall_misses::total 155054 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 74500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 71455000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 85190000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 823000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 219607750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 196366750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 573517000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 93996 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 163493 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 257489 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 623287225 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1332698664 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1955985889 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 88750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 75420750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 706806975 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 595250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.itb.walker 88750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 229132750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1524558163 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2536691388 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 88750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 75420750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 706806975 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 595250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.itb.walker 88750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 229132750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1524558163 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2536691388 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8793 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3231 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 475847 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 183814 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 2570 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1162 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 129938 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 65691 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 18619 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 4275 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 284769 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 133633 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1312342 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 597529 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 597529 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1431 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 478 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 1025 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2934 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 166296 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 28396 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 52318 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247010 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8793 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3231 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 475847 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 350110 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 2570 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1162 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 129938 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 94087 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 18619 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 4275 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 284769 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 185951 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1559352 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8793 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3231 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 475847 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 350110 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 2570 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1162 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 129938 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 94087 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 18619 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 4275 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 284769 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 185951 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1559352 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000114 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000619 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015927 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.035177 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000389 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.007796 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.017141 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000376 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000234 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.010286 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.018880 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016496 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990217 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991632 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.989268 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.990116 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.628398 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.342865 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.365687 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539930 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000114 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000619 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015927 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.316946 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000389 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007796 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.115446 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000376 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.itb.walker 0.000234 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.010286 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.116455 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.099411 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000114 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000619 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015927 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.316946 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000389 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007796 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.115446 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000376 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.itb.walker 0.000234 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.010286 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.116455 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.099411 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74452.862784 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 74173.845471 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 85035.714286 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 88750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 78229.003073 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 76044.193024 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 26824.902947 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 198.303797 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 161.235700 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 88.636489 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 64018.819330 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 69658.094501 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 14666.080986 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 74452.862784 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 65071.531486 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 85035.714286 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 78229.003073 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 70402.131748 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 16364.061697 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 74452.862784 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 65071.531486 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 85035.714286 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 78229.003073 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 70402.131748 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 16364.061697 # average overall miss latency +system.l2c.UpgradeReq_miss_latency::cpu2.data 92996 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 186992 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 728546978 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1457919895 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2186466873 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 71455000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 813736978 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 823000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 219607750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1654286645 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2759983873 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 74500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 71455000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 813736978 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 823000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 219607750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1654286645 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2759983873 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8709 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3162 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 475215 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 183333 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 2605 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1190 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 131141 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 65391 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 18610 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 4205 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 284146 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 134719 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1312426 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 597747 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 597747 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1426 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 471 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 1042 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2939 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu2.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 166399 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 28186 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 52400 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246985 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8709 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3162 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 475215 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 349732 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 2605 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1190 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 131141 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 93577 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 18610 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 4205 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 284146 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 187119 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1559411 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8709 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3162 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 475215 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 349732 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 2605 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1190 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 131141 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 93577 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 18610 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 4205 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 284146 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 187119 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1559411 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000633 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015978 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.035296 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000384 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.007641 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.017158 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000591 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.010308 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.018854 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016513 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990182 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991507 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.986564 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989112 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.627720 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.344249 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.366927 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.540041 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000633 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015978 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.317166 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000384 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007641 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.115680 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000591 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.010308 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.116327 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.099431 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000633 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015978 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.317166 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000384 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007641 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.115680 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000591 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.010308 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.116327 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.099431 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71312.375250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 75926.916221 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 74818.181818 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 74977.039945 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 77309.744094 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 26463.501292 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 201.276231 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 90.463035 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 64.324733 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75084.713800 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 75826.696573 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 16392.518278 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 71312.375250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 75172.007206 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 74818.181818 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 74977.039945 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 75999.753985 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 17800.146226 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 71312.375250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 75172.007206 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 74818.181818 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 74977.039945 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 75999.753985 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 17800.146226 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -697,8 +843,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 58495 # number of writebacks -system.l2c.writebacks::total 58495 # number of writebacks +system.l2c.writebacks::writebacks 58506 # number of writebacks +system.l2c.writebacks::total 58506 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu2.data 12 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits @@ -709,134 +855,122 @@ system.l2c.overall_mshr_hits::cpu2.inst 1 # nu system.l2c.overall_mshr_hits::cpu2.data 12 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 13 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1013 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1126 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1002 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1122 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 11 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.inst 2928 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 2511 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 7587 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 474 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 1014 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1488 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 9736 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 19132 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 28868 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 2528 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 7592 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 467 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 1028 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1495 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 9703 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 19227 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 28930 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1013 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 10862 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 7 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1002 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10825 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 11 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.inst 2928 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 21643 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 36455 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 21755 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 36522 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1013 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 10862 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 7 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1002 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10825 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 11 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.inst 2928 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 21643 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 36455 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 62622750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 69218750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 506250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 191992000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 159345749 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 483837999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4740474 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10141014 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 14881488 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 500926275 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1090069836 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1590996111 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 62622750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 570145025 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 506250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 191992000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1249415585 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 2074834110 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 62622750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 570145025 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 506250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 191992000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1249415585 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 2074834110 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25122070000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26464740500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 51586810500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 939177000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 8518259500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 9457436500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 26061247000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34983000000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 61044247000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000389 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007796 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017141 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000376 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000234 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010282 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018790 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.005781 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991632 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.989268 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.507157 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.342865 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.365687 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.116870 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000389 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007796 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.115446 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000376 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000234 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010282 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.116391 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.023378 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000389 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007796 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.115446 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000376 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000234 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010282 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.116391 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.023378 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61819.101678 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61473.134991 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 72321.428571 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65571.038251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 63459.079650 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 63771.978252 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51450.932108 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 56976.261551 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 55112.793093 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61819.101678 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52489.875253 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 72321.428571 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65571.038251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 57728.391859 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 56914.939240 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61819.101678 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52489.875253 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 72321.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65571.038251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 57728.391859 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 56914.939240 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu2.data 21755 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 36522 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 58877500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 71259000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 687500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 182826500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 164184000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 477897000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4670967 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10281528 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14952495 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 606681022 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1218059105 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1824740127 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 58877500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 677940022 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 687500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 182826500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1382243105 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2302637127 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 58877500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 677940022 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 687500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 182826500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1382243105 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2302637127 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25057289000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26363515500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 51420804500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 935323010 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 8517824000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 9453147010 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25992612010 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34881339500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60873951510 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007641 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017158 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000591 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010305 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018765 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.005785 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991507 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.986564 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.508676 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.344249 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.366927 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.117133 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007641 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.115680 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000591 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010305 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.116263 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023420 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007641 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.115680 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000591 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010305 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.116263 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023420 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63510.695187 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64946.202532 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62947.444679 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.070664 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001.486381 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.668896 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62525.097599 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 63351.490352 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63074.321708 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62627.253764 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63536.800965 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63047.947183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62627.253764 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63536.800965 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63047.947183 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -853,52 +987,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58805533 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1021031 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1021030 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432240 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432240 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 264941 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1503 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1506 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80714 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80714 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830128 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423683 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15492 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 51832 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3321135 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26541184 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37337186 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21748 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84756 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 63984874 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141242678 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 102048 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2176255494 # Layer occupancy (ticks) +system.toL2Bus.throughput 58815755 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1021426 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1021425 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432247 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432247 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265552 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1513 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1515 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80586 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80586 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831264 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423236 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15497 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52067 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3322064 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26578304 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37416070 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21580 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84860 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64100814 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141271334 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 101600 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2179143758 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1870489205 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1872769954 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1849664390 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1848854181 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10070717 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10116966 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30771737 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30973250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48764104 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13809372 # Transaction distribution -system.iobus.trans_dist::ReadResp 13809372 # Transaction distribution -system.iobus.trans_dist::WriteReq 2797 # Transaction distribution -system.iobus.trans_dist::WriteResp 2797 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11494 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3026 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 22 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 258 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48762849 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13795996 # Transaction distribution +system.iobus.trans_dist::ReadResp 13795996 # Transaction distribution +system.iobus.trans_dist::WriteReq 2775 # Transaction distribution +system.iobus.trans_dist::WriteResp 2775 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11418 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 256 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721570 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 719202 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -914,18 +1048,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 736658 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26887680 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26887680 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27624338 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15458 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6052 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 44 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 516 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 734214 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26863328 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26863328 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27597542 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15382 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 715532 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -941,18 +1075,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 740538 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107550720 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107550720 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108291258 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 738102 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107453312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107453312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108191414 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 117209190 # Total data (bytes) -system.iobus.reqLayer0.occupancy 8031000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 7974000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1513000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1515000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 22000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 129000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 128000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -960,7 +1094,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 361287000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 360101000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -992,444 +1126,444 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13443840000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13431664000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 733861000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 731439000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 36856295750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 36823110000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8004008 # DTB read hits -system.cpu0.dtb.read_misses 6222 # DTB read misses -system.cpu0.dtb.write_hits 6595133 # DTB write hits -system.cpu0.dtb.write_misses 2001 # DTB write misses +system.cpu0.dtb.read_hits 7991455 # DTB read hits +system.cpu0.dtb.read_misses 6184 # DTB read misses +system.cpu0.dtb.write_hits 6591541 # DTB write hits +system.cpu0.dtb.write_misses 1989 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 674 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5693 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 118 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8010230 # DTB read accesses -system.cpu0.dtb.write_accesses 6597134 # DTB write accesses +system.cpu0.dtb.perms_faults 208 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7997639 # DTB read accesses +system.cpu0.dtb.write_accesses 6593530 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14599141 # DTB hits -system.cpu0.dtb.misses 8223 # DTB misses -system.cpu0.dtb.accesses 14607364 # DTB accesses -system.cpu0.itb.inst_hits 32379967 # ITB inst hits -system.cpu0.itb.inst_misses 3492 # ITB inst misses +system.cpu0.dtb.hits 14582996 # DTB hits +system.cpu0.dtb.misses 8173 # DTB misses +system.cpu0.dtb.accesses 14591169 # DTB accesses +system.cpu0.itb.inst_hits 32325256 # ITB inst hits +system.cpu0.itb.inst_misses 3454 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 674 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2598 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2571 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32383459 # ITB inst accesses -system.cpu0.itb.hits 32379967 # DTB hits -system.cpu0.itb.misses 3492 # DTB misses -system.cpu0.itb.accesses 32383459 # DTB accesses -system.cpu0.numCycles 113662532 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32328710 # ITB inst accesses +system.cpu0.itb.hits 32325256 # DTB hits +system.cpu0.itb.misses 3454 # DTB misses +system.cpu0.itb.accesses 32328710 # DTB accesses +system.cpu0.numCycles 113673861 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31896171 # Number of instructions committed -system.cpu0.committedOps 42061376 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37196625 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5021 # Number of float alu accesses -system.cpu0.num_func_calls 1200231 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4252287 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37196625 # number of integer instructions -system.cpu0.num_fp_insts 5021 # number of float instructions -system.cpu0.num_int_register_reads 189594254 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39319391 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3591 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1432 # number of times the floating registers were written -system.cpu0.num_mem_refs 15267333 # number of memory refs -system.cpu0.num_load_insts 8373046 # Number of load instructions -system.cpu0.num_store_insts 6894287 # Number of store instructions -system.cpu0.num_idle_cycles 110849279.389256 # Number of idle cycles -system.cpu0.num_busy_cycles 2813252.610744 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024751 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975249 # Percentage of idle cycles +system.cpu0.committedInsts 31847112 # Number of instructions committed +system.cpu0.committedOps 42008964 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37152656 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5018 # Number of float alu accesses +system.cpu0.num_func_calls 1198427 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4245737 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37152656 # number of integer instructions +system.cpu0.num_fp_insts 5018 # number of float instructions +system.cpu0.num_int_register_reads 189368889 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39264582 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3589 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1430 # number of times the floating registers were written +system.cpu0.num_mem_refs 15250074 # number of memory refs +system.cpu0.num_load_insts 8359762 # Number of load instructions +system.cpu0.num_store_insts 6890312 # Number of store instructions +system.cpu0.num_idle_cycles 110868175.114613 # Number of idle cycles +system.cpu0.num_busy_cycles 2805685.885387 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024682 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975318 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891479 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.603901 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43691974 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 891991 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.982528 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8175687500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 493.614782 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.336202 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.652916 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.964091 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014329 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020806 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999226 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 31906072 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8054900 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3731002 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43691974 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31906072 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8054900 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3731002 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43691974 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31906072 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8054900 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3731002 # number of overall hits -system.cpu0.icache.overall_hits::total 43691974 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 476577 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 130192 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 309459 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916228 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 476577 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 130192 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 309459 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916228 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 476577 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 130192 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 309459 # number of overall misses -system.cpu0.icache.overall_misses::total 916228 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1761830250 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4180298881 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5942129131 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1761830250 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4180298881 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5942129131 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1761830250 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4180298881 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5942129131 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32382649 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8185092 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4040461 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 44608202 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32382649 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8185092 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4040461 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 44608202 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32382649 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8185092 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4040461 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 44608202 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014717 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015906 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076590 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020539 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014717 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015906 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076590 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020539 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014717 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015906 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076590 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.020539 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13532.553844 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13508.409453 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6485.426260 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13532.553844 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13508.409453 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6485.426260 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13532.553844 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13508.409453 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6485.426260 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4261 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 891412 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.602619 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43641790 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 891924 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 48.929942 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8178595250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 492.265032 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.623785 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 11.713802 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.961455 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014890 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.022879 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999224 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 31851952 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 8051251 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3738587 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 43641790 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31851952 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 8051251 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3738587 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 43641790 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31851952 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 8051251 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3738587 # number of overall hits +system.cpu0.icache.overall_hits::total 43641790 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 475959 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 131403 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 308483 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 915845 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 475959 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 131403 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 308483 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 915845 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 475959 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 131403 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 308483 # number of overall misses +system.cpu0.icache.overall_misses::total 915845 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1773590500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4162650116 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5936240616 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1773590500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4162650116 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5936240616 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1773590500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4162650116 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5936240616 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32327911 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 8182654 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 4047070 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 44557635 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32327911 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 8182654 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4047070 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 44557635 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32327911 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8182654 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4047070 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 44557635 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014723 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016059 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076224 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020554 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014723 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016059 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076224 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020554 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014723 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016059 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076224 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.020554 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13497.336438 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13493.936833 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6481.708822 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13497.336438 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13493.936833 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6481.708822 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13497.336438 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13493.936833 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6481.708822 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3646 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 235 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 241 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.131915 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.128631 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24229 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 24229 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 24229 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 24229 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 24229 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 24229 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 130192 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 285230 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 415422 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 130192 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 285230 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 415422 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 130192 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 285230 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 415422 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1500951750 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3402203278 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4903155028 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1500951750 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3402203278 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4903155028 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1500951750 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3402203278 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4903155028 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015906 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070593 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009313 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015906 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070593 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009313 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015906 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070593 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009313 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11528.755607 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11927.929313 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11802.829479 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11528.755607 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11927.929313 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11802.829479 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11528.755607 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11927.929313 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11802.829479 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23908 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 23908 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 23908 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 23908 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 23908 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 23908 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 131403 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 284575 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 415978 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 131403 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 284575 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 415978 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 131403 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 284575 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 415978 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1510394500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3385597029 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4895991529 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1510394500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3385597029 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4895991529 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1510394500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3385597029 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4895991529 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016059 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070316 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009336 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016059 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070316 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009336 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016059 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070316 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009336 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11494.368470 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11897.029005 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11769.832849 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11494.368470 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11897.029005 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11769.832849 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11494.368470 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11897.029005 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11769.832849 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 629636 # number of replacements +system.cpu0.dcache.tags.replacements 629916 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997119 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23222123 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 630148 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 36.851855 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 23219265 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 630428 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 36.830955 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.117005 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.034615 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.845498 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970932 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015693 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013370 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.028749 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.124022 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.844348 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970759 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015867 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013368 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6875315 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1820667 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4627275 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13323257 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5963983 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1316466 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2129753 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9410202 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131811 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33157 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73317 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238285 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 138270 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34889 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74229 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247388 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12839298 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3137133 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6757028 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22733459 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12839298 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3137133 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6757028 # number of overall hits -system.cpu0.dcache.overall_hits::total 22733459 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 177356 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 63959 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 269175 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 510490 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167727 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 28874 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 609519 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 806120 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6458 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1732 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3768 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11958 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 3 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 345083 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 92833 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 878694 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1316610 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 345083 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 92833 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 878694 # number of overall misses -system.cpu0.dcache.overall_misses::total 1316610 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 908429000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3875625037 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4784054037 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 912156249 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 22615267762 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 23527424011 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22739750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 50485499 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 73225249 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 39000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 39000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1820585249 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 26490892799 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 28311478048 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1820585249 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 26490892799 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 28311478048 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7052671 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1884626 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4896450 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13833747 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6131710 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1345340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2739272 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216322 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138269 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34889 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77085 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250243 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138270 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34889 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74232 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits::cpu0.data 6862135 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1819979 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4638838 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13320952 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5960420 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1315170 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2133916 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9409506 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131682 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33066 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73671 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238419 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 138143 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34804 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74442 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247389 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12822555 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3135149 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6772754 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 22730458 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12822555 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3135149 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6772754 # number of overall hits +system.cpu0.dcache.overall_hits::total 22730458 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 176872 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 63653 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 271744 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 512269 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167825 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 28657 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 610336 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 806818 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6461 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1738 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3756 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11955 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 344697 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 92310 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 882080 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1319087 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 344697 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 92310 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 882080 # number of overall misses +system.cpu0.dcache.overall_misses::total 1319087 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 905796750 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3920290585 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4826087335 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1012897489 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 23468295787 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24481193276 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22815750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 50223749 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 73039499 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 1918694239 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 27388586372 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 29307280611 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1918694239 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 27388586372 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 29307280611 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7039007 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1883632 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4910582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13833221 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6128245 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1343827 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2744252 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10216324 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138143 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34804 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77427 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250374 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138143 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34804 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74444 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247391 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13184381 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3229966 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7635722 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24050069 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13184381 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3229966 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7635722 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24050069 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025147 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033937 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.054974 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036902 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027354 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021462 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.222511 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.078905 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046706 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049643 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048881 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047786 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000040 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000012 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026174 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028741 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115077 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054745 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026174 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028741 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.115077 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054745 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14203.302115 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14398.161185 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9371.494127 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 31590.920863 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37103.466442 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 29186.007060 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13129.185912 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13398.486996 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6123.536461 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_accesses::cpu0.data 13167252 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3227459 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7654834 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24049545 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13167252 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3227459 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7654834 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24049545 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025127 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033793 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055338 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037032 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027385 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021325 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.222405 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.078973 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046770 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049937 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048510 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047749 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026178 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028601 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115232 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054849 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026178 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028601 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.115232 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054849 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14230.228740 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14426.410832 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9421.002120 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35345.552186 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 38451.436237 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30342.894279 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13127.589183 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13371.605165 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6109.535675 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19611.401646 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30148.029688 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 21503.313850 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19611.401646 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30148.029688 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21503.313850 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7835 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2458 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 871 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 50 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.995408 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 49.160000 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20785.334622 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31050.002689 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22217.852659 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20785.334622 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31050.002689 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22217.852659 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8471 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2566 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 892 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 49 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.496637 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 52.367347 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597529 # number of writebacks -system.cpu0.dcache.writebacks::total 597529 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 138849 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 138849 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 556206 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 556206 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 431 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 431 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 695055 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 695055 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 695055 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 695055 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63959 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 130326 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 194285 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28874 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53313 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 82187 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1732 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3337 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5069 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 92833 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 183639 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 276472 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 92833 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 183639 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 276472 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 779964000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1680980850 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2460944850 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 849834751 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1771488501 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2621323252 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19274250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38952001 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 58226251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1629798751 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3452469351 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5082268102 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1629798751 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3452469351 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5082268102 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27446152500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28893354250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56339506750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1446442000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341405748 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14787847748 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28892594500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42234759998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71127354498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033937 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026616 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014044 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021462 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019462 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008045 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049643 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043290 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020256 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028741 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024050 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011496 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028741 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024050 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011496 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12194.749762 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12898.277013 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12666.674473 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29432.525836 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33228.077598 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31894.621436 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11128.319861 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11672.760264 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11486.733281 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597747 # number of writebacks +system.cpu0.dcache.writebacks::total 597747 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 140335 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 140335 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 556925 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 556925 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 415 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 415 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 697260 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 697260 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 697260 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 697260 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63653 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 131409 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 195062 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28657 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53411 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 82068 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1738 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3341 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5079 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 92310 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 184820 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 277130 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 92310 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 184820 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 277130 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 778293250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1698666084 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2476959334 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 952956511 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1898218478 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2851174989 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19339250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38699751 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 58039001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1731249761 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3596884562 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5328134323 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1731249761 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3596884562 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5328134323 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27375287500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28782575500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56157863000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1442314990 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341314242 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14783629232 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28817602490 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42123889742 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70941492232 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033793 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026760 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014101 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021325 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019463 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008033 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049937 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043150 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020286 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028601 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024144 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011523 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028601 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024144 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011523 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12227.125980 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12926.558181 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12698.318145 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33253.882507 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35539.841568 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34741.616574 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11127.301496 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11583.283747 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11427.249655 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17556.243480 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18800.305768 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18382.577990 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17556.243480 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18800.305768 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18382.577990 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18754.736876 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19461.554821 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19226.118872 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18754.736876 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19461.554821 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19226.118872 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1442,388 +1576,388 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2098287 # DTB read hits -system.cpu1.dtb.read_misses 2070 # DTB read misses -system.cpu1.dtb.write_hits 1420937 # DTB write hits -system.cpu1.dtb.write_misses 371 # DTB write misses +system.cpu1.dtb.read_hits 2096740 # DTB read hits +system.cpu1.dtb.read_misses 2075 # DTB read misses +system.cpu1.dtb.write_hits 1419315 # DTB write hits +system.cpu1.dtb.write_misses 373 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1726 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1735 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 38 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2100357 # DTB read accesses -system.cpu1.dtb.write_accesses 1421308 # DTB write accesses +system.cpu1.dtb.read_accesses 2098815 # DTB read accesses +system.cpu1.dtb.write_accesses 1419688 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3519224 # DTB hits -system.cpu1.dtb.misses 2441 # DTB misses -system.cpu1.dtb.accesses 3521665 # DTB accesses -system.cpu1.itb.inst_hits 8185092 # ITB inst hits -system.cpu1.itb.inst_misses 1172 # ITB inst misses +system.cpu1.dtb.hits 3516055 # DTB hits +system.cpu1.dtb.misses 2448 # DTB misses +system.cpu1.dtb.accesses 3518503 # DTB accesses +system.cpu1.itb.inst_hits 8182654 # ITB inst hits +system.cpu1.itb.inst_misses 1200 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 867 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 888 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8186264 # ITB inst accesses -system.cpu1.itb.hits 8185092 # DTB hits -system.cpu1.itb.misses 1172 # DTB misses -system.cpu1.itb.accesses 8186264 # DTB accesses -system.cpu1.numCycles 580203625 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8183854 # ITB inst accesses +system.cpu1.itb.hits 8182654 # DTB hits +system.cpu1.itb.misses 1200 # DTB misses +system.cpu1.itb.accesses 8183854 # DTB accesses +system.cpu1.numCycles 581318737 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7980801 # Number of instructions committed -system.cpu1.committedOps 10142634 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9072894 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2143 # Number of float alu accesses -system.cpu1.num_func_calls 304668 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1116676 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9072894 # number of integer instructions -system.cpu1.num_fp_insts 2143 # number of float instructions -system.cpu1.num_int_register_reads 52281658 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9864872 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1630 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written -system.cpu1.num_mem_refs 3686646 # number of memory refs -system.cpu1.num_load_insts 2191239 # Number of load instructions -system.cpu1.num_store_insts 1495407 # Number of store instructions -system.cpu1.num_idle_cycles 544226668.771142 # Number of idle cycles -system.cpu1.num_busy_cycles 35976956.228858 # Number of busy cycles -system.cpu1.not_idle_fraction 0.062007 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.937993 # Percentage of idle cycles +system.cpu1.committedInsts 7974693 # Number of instructions committed +system.cpu1.committedOps 10126531 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9058549 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1938 # Number of float alu accesses +system.cpu1.num_func_calls 304877 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1114107 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9058549 # number of integer instructions +system.cpu1.num_fp_insts 1938 # number of float instructions +system.cpu1.num_int_register_reads 52214198 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9844324 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1424 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written +system.cpu1.num_mem_refs 3684398 # number of memory refs +system.cpu1.num_load_insts 2190368 # Number of load instructions +system.cpu1.num_store_insts 1494030 # Number of store instructions +system.cpu1.num_idle_cycles 546218260.044225 # Number of idle cycles +system.cpu1.num_busy_cycles 35100476.955774 # Number of busy cycles +system.cpu1.not_idle_fraction 0.060381 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.939619 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4715473 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3836739 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223495 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3141743 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2527502 # Number of BTB hits +system.cpu2.branchPred.lookups 4723221 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3843292 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 222521 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3120017 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2528037 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.449037 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 411571 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21589 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 81.026385 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 412365 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21211 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10976033 # DTB read hits -system.cpu2.dtb.read_misses 22752 # DTB read misses -system.cpu2.dtb.write_hits 3346841 # DTB write hits -system.cpu2.dtb.write_misses 6453 # DTB write misses +system.cpu2.dtb.read_hits 10969613 # DTB read hits +system.cpu2.dtb.read_misses 23045 # DTB read misses +system.cpu2.dtb.write_hits 3352330 # DTB write hits +system.cpu2.dtb.write_misses 6440 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 531 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2303 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 671 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 173 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2328 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 714 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 159 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 460 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10998785 # DTB read accesses -system.cpu2.dtb.write_accesses 3353294 # DTB write accesses +system.cpu2.dtb.perms_faults 478 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10992658 # DTB read accesses +system.cpu2.dtb.write_accesses 3358770 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14322874 # DTB hits -system.cpu2.dtb.misses 29205 # DTB misses -system.cpu2.dtb.accesses 14352079 # DTB accesses -system.cpu2.itb.inst_hits 4041881 # ITB inst hits -system.cpu2.itb.inst_misses 4586 # ITB inst misses +system.cpu2.dtb.hits 14321943 # DTB hits +system.cpu2.dtb.misses 29485 # DTB misses +system.cpu2.dtb.accesses 14351428 # DTB accesses +system.cpu2.itb.inst_hits 4048520 # ITB inst hits +system.cpu2.itb.inst_misses 4581 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 531 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1634 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1671 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1002 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1028 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4046467 # ITB inst accesses -system.cpu2.itb.hits 4041881 # DTB hits -system.cpu2.itb.misses 4586 # DTB misses -system.cpu2.itb.accesses 4046467 # DTB accesses -system.cpu2.numCycles 88343562 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4053101 # ITB inst accesses +system.cpu2.itb.hits 4048520 # DTB hits +system.cpu2.itb.misses 4581 # DTB misses +system.cpu2.itb.accesses 4053101 # DTB accesses +system.cpu2.numCycles 88363580 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9345666 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32463757 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4715473 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2939073 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6849430 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1758819 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50954 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18707448 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 397 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 820 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 32452 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 720275 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 489 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4040467 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 290046 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2014 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36916106 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.056921 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.443441 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9342746 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32497136 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4723221 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2940402 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6855397 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1756636 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50446 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18848050 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 334 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 925 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 34178 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 721824 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 449 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4047074 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 289511 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1970 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37061318 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.053700 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.440521 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30071749 81.46% 81.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 384570 1.04% 82.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 513519 1.39% 83.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 818109 2.22% 86.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 634612 1.72% 87.83% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 341178 0.92% 88.75% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1041484 2.82% 91.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 228835 0.62% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2882050 7.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30210914 81.52% 81.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 385385 1.04% 82.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 515477 1.39% 83.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 820134 2.21% 86.16% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 628486 1.70% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 342820 0.93% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1044433 2.82% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 229207 0.62% 92.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2884462 7.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36916106 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053377 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367472 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9928442 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19318553 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6233841 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 278394 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1155918 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 607967 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53425 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36920328 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 180410 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1155918 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10478416 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6754031 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11105712 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5942637 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1478447 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34829842 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2448 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 324847 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 890462 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 131 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37304234 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 159387361 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148242103 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3218 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26430435 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10873798 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 231762 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 208068 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3242623 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6608021 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3899448 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 530191 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 761841 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32138723 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 510591 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34782251 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 56051 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7186073 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19057300 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 153940 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36916106 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.942197 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.600639 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37061318 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053452 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367766 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9926500 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19460558 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6238388 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 279816 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1155131 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 608208 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53066 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36958585 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 178391 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1155131 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10476553 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6920166 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11076723 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5947862 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1483966 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34870863 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2458 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 328650 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 889849 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 96 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37358262 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 159586833 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 148423376 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3369 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26507725 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10850536 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 232822 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 209087 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3256835 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6623705 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3904787 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 530493 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 775113 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32195808 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 505146 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34809127 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54913 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7172484 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19086467 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 147942 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37061318 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.939231 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.598560 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24329752 65.91% 65.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3820331 10.35% 76.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2317804 6.28% 82.53% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2003808 5.43% 87.96% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2797781 7.58% 95.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 970796 2.63% 98.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 496090 1.34% 99.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144708 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 35036 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24455957 65.99% 65.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3833682 10.34% 76.33% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2322342 6.27% 82.60% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2005181 5.41% 88.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2795966 7.54% 95.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 971107 2.62% 98.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 498292 1.34% 99.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 144261 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34530 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36916106 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37061318 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19314 1.26% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1407095 91.52% 92.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 111138 7.23% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19660 1.28% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1402550 91.51% 92.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 110445 7.21% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61377 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19718575 56.69% 56.87% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 27760 0.08% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 10 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 9 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 371 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11459171 32.95% 89.89% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3514969 10.11% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61175 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19747110 56.73% 56.91% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 27980 0.08% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 388 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11452276 32.90% 89.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3520179 10.11% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34782251 # Type of FU issued -system.cpu2.iq.rate 0.393716 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1537548 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044205 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108096303 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39840742 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28020326 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6981 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3693 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3127 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36254698 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3724 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 204617 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34809127 # Type of FU issued +system.cpu2.iq.rate 0.393931 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1532656 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044030 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108288948 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39878610 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28070823 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7546 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3965 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3367 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36276582 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 4026 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 205280 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1527306 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1908 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9375 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 562929 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1528845 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1875 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9489 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 562920 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5348773 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344308 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5328051 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 344229 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1155918 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5077664 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 88593 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32732277 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60627 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6608021 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3899448 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 368370 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29616 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2740 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9375 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107393 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89251 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196644 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33865771 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11188559 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 916480 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1155131 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5244365 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 89322 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32783919 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60352 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6623705 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3904787 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 362611 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 30261 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2481 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9489 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 106879 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89021 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 195900 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33894861 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11182187 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 914266 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82963 # number of nop insts executed -system.cpu2.iew.exec_refs 14669578 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3700003 # Number of branches executed -system.cpu2.iew.exec_stores 3481019 # Number of stores executed -system.cpu2.iew.exec_rate 0.383342 # Inst execution rate -system.cpu2.iew.wb_sent 33465265 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28023453 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16087448 # num instructions producing a value -system.cpu2.iew.wb_consumers 29114707 # num instructions consuming a value +system.cpu2.iew.exec_nop 82965 # number of nop insts executed +system.cpu2.iew.exec_refs 14668868 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3706634 # Number of branches executed +system.cpu2.iew.exec_stores 3486681 # Number of stores executed +system.cpu2.iew.exec_rate 0.383584 # Inst execution rate +system.cpu2.iew.wb_sent 33494578 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28074190 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16115456 # num instructions producing a value +system.cpu2.iew.wb_consumers 29164308 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317210 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.552554 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.317712 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.552575 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7129352 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356651 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 170839 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35759991 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.708498 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.752281 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7126752 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357204 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 170224 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35906001 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.707499 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.751012 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27025739 75.58% 75.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4219923 11.80% 87.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1248297 3.49% 90.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 635334 1.78% 92.64% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 557295 1.56% 94.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 319233 0.89% 95.09% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 417712 1.17% 96.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 309905 0.87% 97.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1026553 2.87% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27147368 75.61% 75.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4230684 11.78% 87.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1251387 3.49% 90.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 639812 1.78% 92.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 559957 1.56% 94.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 318640 0.89% 95.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 417979 1.16% 96.27% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 311730 0.87% 97.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1028444 2.86% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35759991 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20506693 # Number of instructions committed -system.cpu2.commit.committedOps 25335895 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35906001 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20561870 # Number of instructions committed +system.cpu2.commit.committedOps 25403458 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8417234 # Number of memory references committed -system.cpu2.commit.loads 5080715 # Number of loads committed -system.cpu2.commit.membars 94304 # Number of memory barriers committed -system.cpu2.commit.branches 3173719 # Number of branches committed -system.cpu2.commit.fp_insts 3091 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22548127 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294799 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1026553 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8436727 # Number of memory references committed +system.cpu2.commit.loads 5094860 # Number of loads committed +system.cpu2.commit.membars 94449 # Number of memory barriers committed +system.cpu2.commit.branches 3185060 # Number of branches committed +system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 22606405 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295605 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1028444 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66675347 # The number of ROB reads -system.cpu2.rob.rob_writes 66130617 # The number of ROB writes -system.cpu2.timesIdled 360964 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51427456 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3556668435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20451214 # Number of Instructions Simulated -system.cpu2.committedOps 25280416 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20451214 # Number of Instructions Simulated -system.cpu2.cpi 4.319722 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.319722 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.231496 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.231496 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 156902302 # number of integer regfile reads -system.cpu2.int_regfile_writes 29839836 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22382 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20836 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9252861 # number of misc regfile reads -system.cpu2.misc_regfile_writes 241910 # number of misc regfile writes +system.cpu2.rob.rob_reads 66885510 # The number of ROB reads +system.cpu2.rob.rob_writes 66259648 # The number of ROB writes +system.cpu2.timesIdled 359925 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51302262 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3553994827 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20506347 # Number of Instructions Simulated +system.cpu2.committedOps 25347935 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20506347 # Number of Instructions Simulated +system.cpu2.cpi 4.309084 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.309084 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.232068 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.232068 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157055367 # number of integer regfile reads +system.cpu2.int_regfile_writes 29889640 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22622 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20830 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9269321 # number of misc regfile reads +system.cpu2.misc_regfile_writes 242794 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1838,10 +1972,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1279629373750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1279629373750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1279629373750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1279629373750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1346583006000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1346583006000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1346583006000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1346583006000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index b715fd89b..cc97b6f9f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,150 +1,164 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.548576 # Number of seconds simulated -sim_ticks 2548576209000 # Number of ticks simulated -final_tick 2548576209000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.549325 # Number of seconds simulated +sim_ticks 2549325180000 # Number of ticks simulated +final_tick 2549325180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64501 # Simulator instruction rate (inst/s) -host_op_rate 82996 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2725389479 # Simulator tick rate (ticks/s) -host_mem_usage 403492 # Number of bytes of host memory used -host_seconds 935.12 # Real time elapsed on the host -sim_insts 60316464 # Number of instructions simulated -sim_ops 77611603 # Number of ops (including micro ops) simulated +host_inst_rate 61075 # Simulator instruction rate (inst/s) +host_op_rate 78588 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2581455626 # Simulator tick rate (ticks/s) +host_mem_usage 428832 # Number of bytes of host memory used +host_seconds 987.55 # Real time elapsed on the host +sim_insts 60314884 # Number of instructions simulated +sim_ops 77609482 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 483776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5166800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 315264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3924504 # Number of bytes read from this memory -system.physmem.bytes_read::total 131003560 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 483776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 315264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783488 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1522020 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494080 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799588 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 507840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4720464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 291712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4372184 # Number of bytes read from this memory +system.physmem.bytes_read::total 131005480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 507840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 291712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785664 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1521520 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494580 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801764 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7559 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 80765 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 61326 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293434 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59117 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380505 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373520 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813142 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47520858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7935 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73791 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 68321 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293464 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59151 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380380 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373645 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813176 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47506897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 678 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 189822 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2027328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 123702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1539881 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51402646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 189822 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 123702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313524 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484550 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 597204 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586241 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2667995 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47520858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 199206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1851652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 114427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1715036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51388297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 199206 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 114427 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313633 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596832 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586265 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2668064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47506897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 678 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 189822 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2624532 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 123702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2126122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54070641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293434 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 813142 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15293434 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 813142 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 978779776 # Total number of bytes read from memory -system.physmem.bytesWritten 52041088 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131003560 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799588 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 13 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 955864 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955534 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955684 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 955879 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 955769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955991 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955868 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 955778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955947 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955508 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955111 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956226 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955972 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956075 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955979 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6690 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6478 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6630 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6589 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6842 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6835 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6779 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7114 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6901 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6563 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6214 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6772 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7070 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6922 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2548575024500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 42 # Categorize read packet sizes -system.physmem.readPktSize::3 15138816 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154576 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754025 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59117 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1061686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 987876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 978214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3738072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2813374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2806969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2769477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 15679 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 43265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 29260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.bw_total::cpu0.inst 199206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2448485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 114427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2301301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54056362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293464 # Number of read requests accepted +system.physmem.writeReqs 813176 # Number of write requests accepted +system.physmem.readBursts 15293464 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813176 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 978217536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 564160 # Total number of bytes read from write queue +system.physmem.bytesWritten 6910272 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131005480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6801764 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8815 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705189 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4711 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955865 # Per bank write bursts +system.physmem.perBankRdBursts::1 955523 # Per bank write bursts +system.physmem.perBankRdBursts::2 954611 # Per bank write bursts +system.physmem.perBankRdBursts::3 954852 # Per bank write bursts +system.physmem.perBankRdBursts::4 955764 # Per bank write bursts +system.physmem.perBankRdBursts::5 955945 # Per bank write bursts +system.physmem.perBankRdBursts::6 954843 # Per bank write bursts +system.physmem.perBankRdBursts::7 954680 # Per bank write bursts +system.physmem.perBankRdBursts::8 956251 # Per bank write bursts +system.physmem.perBankRdBursts::9 955822 # Per bank write bursts +system.physmem.perBankRdBursts::10 954302 # Per bank write bursts +system.physmem.perBankRdBursts::11 954022 # Per bank write bursts +system.physmem.perBankRdBursts::12 956218 # Per bank write bursts +system.physmem.perBankRdBursts::13 955977 # Per bank write bursts +system.physmem.perBankRdBursts::14 955052 # Per bank write bursts +system.physmem.perBankRdBursts::15 954922 # Per bank write bursts +system.physmem.perBankWrBursts::0 6685 # Per bank write bursts +system.physmem.perBankWrBursts::1 6462 # Per bank write bursts +system.physmem.perBankWrBursts::2 6616 # Per bank write bursts +system.physmem.perBankWrBursts::3 6625 # Per bank write bursts +system.physmem.perBankWrBursts::4 6578 # Per bank write bursts +system.physmem.perBankWrBursts::5 6834 # Per bank write bursts +system.physmem.perBankWrBursts::6 6825 # Per bank write bursts +system.physmem.perBankWrBursts::7 6778 # Per bank write bursts +system.physmem.perBankWrBursts::8 7112 # Per bank write bursts +system.physmem.perBankWrBursts::9 6876 # Per bank write bursts +system.physmem.perBankWrBursts::10 6540 # Per bank write bursts +system.physmem.perBankWrBursts::11 6189 # Per bank write bursts +system.physmem.perBankWrBursts::12 7142 # Per bank write bursts +system.physmem.perBankWrBursts::13 6759 # Per bank write bursts +system.physmem.perBankWrBursts::14 7042 # Per bank write bursts +system.physmem.perBankWrBursts::15 6910 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2549324058500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 42 # Read request sizes (log2) +system.physmem.readPktSize::3 15138816 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 154606 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 754025 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 59151 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1187642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1126920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1081304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3687011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2647213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2642028 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2655762 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 54010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 60825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -157,31 +171,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -189,456 +203,675 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39284 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 25091.701456 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2070.748672 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31471.829892 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-79 6644 16.91% 16.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-143 3436 8.75% 25.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-207 2300 5.85% 31.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-271 1832 4.66% 36.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-335 1227 3.12% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-399 1105 2.81% 42.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-463 800 2.04% 44.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-527 812 2.07% 46.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-591 554 1.41% 47.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-655 516 1.31% 48.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-719 427 1.09% 50.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-783 432 1.10% 51.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-847 277 0.71% 51.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-911 299 0.76% 52.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-975 172 0.44% 53.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1039 211 0.54% 53.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1103 136 0.35% 53.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1167 132 0.34% 54.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1231 101 0.26% 54.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1295 106 0.27% 54.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1359 70 0.18% 54.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1423 391 1.00% 55.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1487 264 0.67% 56.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1551 450 1.15% 57.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1615 85 0.22% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1679 167 0.43% 58.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1743 56 0.14% 58.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1807 95 0.24% 58.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1871 44 0.11% 58.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1935 79 0.20% 59.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1999 30 0.08% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2063 69 0.18% 59.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2127 18 0.05% 59.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2191 44 0.11% 59.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2255 15 0.04% 59.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2319 32 0.08% 59.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2447 19 0.05% 59.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2511 8 0.02% 59.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2575 26 0.07% 59.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2639 6 0.02% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2703 18 0.05% 59.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2767 15 0.04% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2831 16 0.04% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2895 7 0.02% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2959 13 0.03% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3023 4 0.01% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3087 18 0.05% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3215 6 0.02% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3279 6 0.02% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3343 11 0.03% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3599 6 0.02% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3727 10 0.03% 60.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3791 5 0.01% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3855 3 0.01% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3919 1 0.00% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3983 13 0.03% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4047 4 0.01% 60.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4111 32 0.08% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4175 5 0.01% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4239 4 0.01% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4303 3 0.01% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4367 6 0.02% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4495 5 0.01% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4559 4 0.01% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4623 6 0.02% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4687 3 0.01% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4879 4 0.01% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5007 7 0.02% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5135 8 0.02% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5199 2 0.01% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5263 2 0.01% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5391 3 0.01% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5455 3 0.01% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5519 4 0.01% 60.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5583 1 0.00% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5775 2 0.01% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5903 2 0.01% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6095 1 0.00% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6223 3 0.01% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6287 2 0.01% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6351 1 0.00% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6479 2 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6607 1 0.00% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6735 1 0.00% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6799 20 0.05% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6863 3 0.01% 60.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7119 2 0.01% 60.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7311 3 0.01% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7375 2 0.01% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7439 4 0.01% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7567 9 0.02% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7631 1 0.00% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7695 7 0.02% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7823 3 0.01% 60.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7887 4 0.01% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7951 2 0.01% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8079 11 0.03% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8143 1 0.00% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8207 311 0.79% 61.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8463 63 0.16% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8527 194 0.49% 62.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8591 13 0.03% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8783 3 0.01% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20495 1 0.00% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25615 2 0.01% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28367 1 0.00% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32192-32207 1 0.00% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33359 1 0.00% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33679 2 0.01% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33807 2 0.01% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34575 1 0.00% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37184-37199 1 0.00% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39488-39503 1 0.00% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45071 1 0.00% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58112-58127 1 0.00% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64768-64783 1 0.00% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65551 14685 37.38% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::68736-68751 1 0.00% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73920-73935 9 0.02% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-73999 43 0.11% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74048-74063 33 0.08% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39284 # Bytes accessed per row activation -system.physmem.totQLat 294283871250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 386089225000 # Sum of mem lat for all requests -system.physmem.totBusLat 76467105000 # Total cycles spent in databus access -system.physmem.totBankLat 15338248750 # Total cycles spent in bank access -system.physmem.avgQLat 19242.51 # Average queueing delay per request -system.physmem.avgBankLat 1002.93 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25245.45 # Average memory access latency -system.physmem.avgRdBW 384.05 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.42 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.40 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.16 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 1.08 # Average write queue length over time -system.physmem.readRowHits 15268174 # Number of row buffer hits during reads -system.physmem.writeRowHits 94166 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.58 # Row buffer hit rate for writes -system.physmem.avgGap 158231.96 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55011549 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346066 # Transaction distribution -system.membus.trans_dist::ReadResp 16346069 # Transaction distribution +system.physmem.bytesPerActivate::samples 86834 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11344.953359 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1015.074534 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16830.192081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23626 27.21% 27.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14089 16.23% 43.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2724 3.14% 46.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2126 2.45% 49.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1310 1.51% 50.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1204 1.39% 51.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 811 0.93% 52.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1018 1.17% 54.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 572 0.66% 54.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 583 0.67% 55.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 533 0.61% 55.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 603 0.69% 56.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 284 0.33% 56.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 265 0.31% 57.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 147 0.17% 57.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 578 0.67% 58.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 113 0.13% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 129 0.15% 58.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 72 0.08% 58.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 237 0.27% 58.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 56 0.06% 58.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 502 0.58% 59.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 39 0.04% 59.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 171 0.20% 59.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 11 0.01% 59.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 115 0.13% 59.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 15 0.02% 59.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 109 0.13% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 18 0.02% 59.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 54 0.06% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 24 0.03% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 490 0.56% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 17 0.02% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 36 0.04% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 7 0.01% 60.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 154 0.18% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 14 0.02% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 32 0.04% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 7 0.01% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 95 0.11% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 10 0.01% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 14 0.02% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 9 0.01% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 155 0.18% 61.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 16 0.02% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 17 0.02% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 10 0.01% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 408 0.47% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 10 0.01% 61.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 7 0.01% 61.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 96 0.11% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 10 0.01% 61.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 20 0.02% 61.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 9 0.01% 61.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 86 0.10% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 6 0.01% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 21 0.02% 62.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 12 0.01% 62.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 58 0.07% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 407 0.47% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 10 0.01% 62.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 18 0.02% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 3 0.00% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 75 0.09% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 12 0.01% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 7 0.01% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 139 0.16% 62.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 8 0.01% 62.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 15 0.02% 63.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 9 0.01% 63.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 72 0.08% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 6 0.01% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 6 0.01% 63.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 409 0.47% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 7 0.01% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 17 0.02% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 14 0.02% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 76 0.09% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 9 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 13 0.01% 63.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 8 0.01% 63.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 144 0.17% 63.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 9 0.01% 63.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 13 0.01% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 142 0.16% 64.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 12 0.01% 64.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 6 0.01% 64.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 262 0.30% 64.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 5 0.01% 64.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 6 0.01% 64.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 136 0.16% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 3 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 8 0.01% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 8 0.01% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 6 0.01% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 21 0.02% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 74 0.09% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 5 0.01% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 8 0.01% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 452 0.52% 65.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 4 0.00% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 13 0.01% 65.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 11 0.01% 65.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 23 0.03% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 4 0.00% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 73 0.08% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 1 0.00% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 2 0.00% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 3 0.00% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 132 0.15% 65.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 4 0.00% 65.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 8 0.01% 65.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 243 0.28% 66.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 128 0.15% 66.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 66 0.08% 66.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 67 0.08% 66.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 450 0.52% 66.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 67 0.08% 66.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 2 0.00% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 1 0.00% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 133 0.15% 67.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 1 0.00% 67.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 251 0.29% 67.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 68 0.08% 67.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10695 1 0.00% 67.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 128 0.15% 67.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 66 0.08% 67.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 387 0.45% 68.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 67 0.08% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11719 1 0.00% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 121 0.14% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 66 0.08% 68.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12103 1 0.00% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 380 0.44% 68.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 37 0.04% 68.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 69 0.08% 68.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 65 0.07% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13255 1 0.00% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 389 0.45% 69.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 129 0.15% 69.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 66 0.08% 69.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 120 0.14% 69.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 443 0.51% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 57 0.07% 70.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 13 0.01% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 119 0.14% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 388 0.45% 71.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 123 0.14% 71.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15751 1 0.00% 71.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 64 0.07% 71.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 66 0.08% 71.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16327 1 0.00% 71.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 526 0.61% 71.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 68 0.08% 72.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 64 0.07% 72.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 122 0.14% 72.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 391 0.45% 72.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 120 0.14% 72.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 15 0.02% 72.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 57 0.07% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 1 0.00% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 444 0.51% 73.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 119 0.14% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 66 0.08% 73.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 129 0.15% 73.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 384 0.44% 74.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 64 0.07% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 70 0.08% 74.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 37 0.04% 74.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 1 0.00% 74.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 382 0.44% 74.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 65 0.07% 74.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 119 0.14% 75.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 66 0.08% 75.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 385 0.44% 75.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 68 0.08% 75.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21952-21959 1 0.00% 75.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 128 0.15% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 69 0.08% 75.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 1 0.00% 75.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 253 0.29% 76.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22592-22599 1 0.00% 76.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22720-22727 1 0.00% 76.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 132 0.15% 76.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22976-22983 1 0.00% 76.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 67 0.08% 76.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 450 0.52% 76.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 68 0.08% 77.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 1 0.00% 77.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 67 0.08% 77.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 129 0.15% 77.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 137 0.16% 77.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24704-24711 1 0.00% 77.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 129 0.15% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 67 0.08% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25216-25223 1 0.00% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 67 0.08% 77.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 448 0.52% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25664-25671 1 0.00% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 66 0.08% 78.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 134 0.15% 78.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 253 0.29% 78.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 68 0.08% 78.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 129 0.15% 78.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27264-27271 1 0.00% 78.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 68 0.08% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27463 1 0.00% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 384 0.44% 79.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 66 0.08% 79.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 119 0.14% 79.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 64 0.07% 79.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 380 0.44% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 1 0.00% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 37 0.04% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 72 0.08% 80.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 65 0.07% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 385 0.44% 80.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 1 0.00% 80.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 129 0.15% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 64 0.07% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 119 0.14% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 443 0.51% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 56 0.06% 81.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 13 0.01% 81.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 119 0.14% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 2 0.00% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 1 0.00% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 389 0.45% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31808-31815 1 0.00% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 124 0.14% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 66 0.08% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 66 0.08% 82.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 526 0.61% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 65 0.07% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 65 0.07% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 1 0.00% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 125 0.14% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 390 0.45% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 119 0.14% 84.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 13 0.01% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 56 0.06% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 441 0.51% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 119 0.14% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 64 0.07% 84.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 129 0.15% 85.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 385 0.44% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 64 0.07% 85.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 72 0.08% 85.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36416-36423 1 0.00% 85.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 37 0.04% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 380 0.44% 86.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 64 0.07% 86.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 119 0.14% 86.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 66 0.08% 86.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 384 0.44% 86.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38080-38087 1 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 67 0.08% 87.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 128 0.15% 87.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 68 0.08% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 253 0.29% 87.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 134 0.15% 87.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 66 0.08% 87.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 448 0.52% 88.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 68 0.08% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40320-40327 1 0.00% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 66 0.08% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 129 0.15% 88.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 137 0.16% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 129 0.15% 88.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 67 0.08% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 68 0.08% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 449 0.52% 89.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42176-42183 1 0.00% 89.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 67 0.08% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 2 0.00% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 132 0.15% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42944-42951 1 0.00% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 251 0.29% 90.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 67 0.08% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43392-43399 2 0.00% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 128 0.15% 90.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 67 0.08% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 384 0.44% 90.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 90.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 68 0.08% 90.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 1 0.00% 90.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44480-44487 1 0.00% 90.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 119 0.14% 91.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44736-44743 1 0.00% 91.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 66 0.08% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 383 0.44% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 41 0.05% 91.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 70 0.08% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45639 1 0.00% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 65 0.07% 91.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45952-45959 1 0.00% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 385 0.44% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 129 0.15% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 64 0.07% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 119 0.14% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 440 0.51% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 1 0.00% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 58 0.07% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 14 0.02% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 120 0.14% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 388 0.45% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 122 0.14% 93.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 64 0.07% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 65 0.07% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 2 0.00% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5147 5.93% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49344-49351 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49472-49479 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50816-50823 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51072-51079 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86834 # Bytes accessed per row activation +system.physmem.totQLat 369633946000 # Total ticks spent queuing +system.physmem.totMemAccLat 463601929750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76423245000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17544738750 # Total ticks spent accessing banks +system.physmem.avgQLat 24183.35 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1147.87 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30331.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.39 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.02 # Data bus utilization in percentage +system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 1.05 # Average write queue length when enqueuing +system.physmem.readRowHits 15212610 # Number of row buffer hits during reads +system.physmem.writeRowHits 93178 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 86.29 # Row buffer hit rate for writes +system.physmem.avgGap 158277.83 # Average gap between requests +system.physmem.pageHitRate 99.44 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.88 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 54996997 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346113 # Transaction distribution +system.membus.trans_dist::ReadResp 16346116 # Transaction distribution system.membus.trans_dist::WriteReq 763348 # Transaction distribution system.membus.trans_dist::WriteResp 763348 # Transaction distribution -system.membus.trans_dist::Writeback 59117 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4675 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4677 # Transaction distribution -system.membus.trans_dist::ReadExReq 131414 # Transaction distribution -system.membus.trans_dist::ReadExResp 131414 # Transaction distribution +system.membus.trans_dist::Writeback 59151 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4708 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4711 # Transaction distribution +system.membus.trans_dist::ReadExReq 131399 # Transaction distribution +system.membus.trans_dist::ReadExResp 131399 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382956 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382960 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885757 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272507 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885919 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272673 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550139 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390329 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34550305 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390337 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16692620 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19090597 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16696716 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19094701 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140201125 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140201125 # Total data (bytes) +system.membus.tot_pkt_size::total 140205229 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140205229 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475672000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487741000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3615000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3601000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17572541000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17567405000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4757385335 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4737923280 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34173123993 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34188515482 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 64349 # number of replacements -system.l2c.tags.tagsinuse 51432.213982 # Cycle average of tags in use -system.l2c.tags.total_refs 1904557 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129741 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.679685 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2511462555500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36971.376669 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 19.336615 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000368 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4863.234399 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3340.353025 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.819885 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3340.869034 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2888.223986 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564138 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000295 # Average percentage of cache occupancy +system.l2c.tags.replacements 64379 # number of replacements +system.l2c.tags.tagsinuse 51427.622498 # Cycle average of tags in use +system.l2c.tags.total_refs 1904241 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129768 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.674195 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2512188924000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36951.825179 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.926736 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4986.850446 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3336.949611 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.947160 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3226.583152 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2894.539843 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.563840 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000289 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050970 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.050978 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044071 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784793 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 31056 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6811 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 489944 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 180708 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 32283 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7013 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 480968 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 206794 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435577 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608201 # number of Writeback hits -system.l2c.Writeback_hits::total 608201 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 22 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.076093 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.050918 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000182 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.049234 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044167 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.784723 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 32603 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7139 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 505956 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 182118 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30730 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6661 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 464492 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 205502 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1435201 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608382 # number of Writeback hits +system.l2c.Writeback_hits::total 608382 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 22 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 18 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 40 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56719 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56246 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112965 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 31056 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6811 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 489944 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 237427 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 32283 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7013 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 480968 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 263040 # number of demand (read+write) hits -system.l2c.demand_hits::total 1548542 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 31056 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6811 # number of overall hits -system.l2c.overall_hits::cpu0.inst 489944 # number of overall hits -system.l2c.overall_hits::cpu0.data 237427 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 32283 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7013 # number of overall hits -system.l2c.overall_hits::cpu1.inst 480968 # number of overall hits -system.l2c.overall_hits::cpu1.data 263040 # number of overall hits -system.l2c.overall_hits::total 1548542 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 29 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 10 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 15 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 58173 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 54780 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112953 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32603 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7139 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 505956 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 240291 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30730 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6661 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 464492 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 260282 # number of demand (read+write) hits +system.l2c.demand_hits::total 1548154 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 32603 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7139 # number of overall hits +system.l2c.overall_hits::cpu0.inst 505956 # number of overall hits +system.l2c.overall_hits::cpu0.data 240291 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30730 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6661 # number of overall hits +system.l2c.overall_hits::cpu1.inst 464492 # number of overall hits +system.l2c.overall_hits::cpu1.data 260282 # number of overall hits +system.l2c.overall_hits::total 1548154 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 27 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7450 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6327 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4932 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4374 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23125 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1313 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1598 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu0.inst 7825 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6187 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4565 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4551 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23171 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1285 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1631 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2916 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 75216 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 57962 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133178 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 29 # number of demand (read+write) misses +system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 68474 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 64717 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133191 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7450 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 81543 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4932 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 62336 # number of demand (read+write) misses -system.l2c.demand_misses::total 156303 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 29 # number of overall misses +system.l2c.demand_misses::cpu0.inst 7825 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 74661 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4565 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 69268 # number of demand (read+write) misses +system.l2c.demand_misses::total 156362 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7450 # number of overall misses -system.l2c.overall_misses::cpu0.data 81543 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4932 # number of overall misses -system.l2c.overall_misses::cpu1.data 62336 # number of overall misses -system.l2c.overall_misses::total 156303 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2773750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 130250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 535863000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 458241999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1150250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 375877250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 330560248 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1704596747 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 185492 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 279988 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5248575225 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3913924011 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9162499236 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 2773750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 130250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 535863000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 5706817224 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1150250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 375877250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4244484259 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 10867095983 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 2773750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 130250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 535863000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 5706817224 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1150250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 375877250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4244484259 # number of overall miss cycles -system.l2c.overall_miss_latency::total 10867095983 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 31085 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6813 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 497394 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 187035 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 32294 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 7013 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 485900 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 211168 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1458702 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 608201 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 608201 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1331 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1620 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2951 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 131935 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 114208 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246143 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 31085 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6813 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 497394 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 318970 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 32294 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7013 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 485900 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 325376 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1704845 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 31085 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6813 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 497394 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 318970 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 32294 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7013 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 485900 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 325376 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1704845 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000933 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000294 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014978 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.033828 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000341 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010150 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.020713 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015853 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.986476 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.986420 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.986445 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.250000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.570099 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.507513 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541059 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000933 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000294 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014978 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.255645 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000341 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010150 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.191581 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091682 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000933 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000294 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014978 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.255645 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000341 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010150 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.191581 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091682 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 95646.551724 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 65125 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71927.919463 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 72426.426268 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 104568.181818 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76211.932279 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75573.902149 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 73712.291762 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 141.273420 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 175.211514 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 159.903813 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69780.036495 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 67525.689434 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 68798.894983 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 95646.551724 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 65125 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 71927.919463 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 69985.372429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 104568.181818 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76211.932279 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 68090.417399 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 69525.831129 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 95646.551724 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 65125 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 71927.919463 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 69985.372429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 104568.181818 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76211.932279 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 68090.417399 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 69525.831129 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 7825 # number of overall misses +system.l2c.overall_misses::cpu0.data 74661 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4565 # number of overall misses +system.l2c.overall_misses::cpu1.data 69268 # number of overall misses +system.l2c.overall_misses::total 156362 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2234250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 158000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 566532750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 458261500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1111500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 342566000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 354437999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1725301999 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 254989 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 187492 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 442481 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5097311886 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4928859322 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10026171208 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 2234250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 158000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 566532750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 5555573386 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1111500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 342566000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 5283297321 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11751473207 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 2234250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 158000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 566532750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 5555573386 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1111500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 342566000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 5283297321 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11751473207 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 32630 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 7141 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 513781 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 188305 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30744 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6661 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 469057 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 210053 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1458372 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 608382 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 608382 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1307 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1649 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2956 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 6 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 12 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 18 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 126647 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 119497 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246144 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 32630 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7141 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 513781 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 314952 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30744 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6661 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 469057 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 329550 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1704516 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 32630 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7141 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 513781 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 314952 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30744 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6661 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 469057 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 329550 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1704516 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000827 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000280 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015230 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.032856 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000455 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009732 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.021666 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015888 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.983168 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989084 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.986468 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.166667 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.166667 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.166667 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.540668 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.541578 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541110 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000827 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000280 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015230 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.237055 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000455 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009732 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.210190 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.091734 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000827 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000280 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015230 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.237055 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000455 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009732 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.210190 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.091734 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 82750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72400.351438 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 74068.449976 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79392.857143 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75041.840088 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 77881.344540 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 74459.539899 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 198.435019 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 114.955242 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 151.742455 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74441.567398 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76160.194725 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 75276.641875 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 82750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 72400.351438 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 74410.647942 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79392.857143 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75041.840088 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 76273.276563 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 75155.557022 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 82750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 72400.351438 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 74410.647942 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79392.857143 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75041.840088 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 76273.276563 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 75155.557022 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -647,166 +880,170 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59117 # number of writebacks -system.l2c.writebacks::total 59117 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 27 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 27 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 27 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 78 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 29 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 59151 # number of writebacks +system.l2c.writebacks::total 59151 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 42 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 25 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 42 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 25 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 42 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 25 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 79 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 7444 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6288 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4926 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4347 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23047 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1313 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1598 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2911 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 7820 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6145 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 14 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4558 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4526 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23092 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1285 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1631 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2916 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 75216 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 57962 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133178 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 29 # number of demand (read+write) MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 68474 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 64717 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133191 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7444 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 81504 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4926 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 62309 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156225 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 29 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7820 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 74619 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 14 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4558 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 69243 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156283 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7444 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 81504 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4926 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 62309 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156225 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2403250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 105750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 440932000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 376527749 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1009250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 313110000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 273532998 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1407620997 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13131313 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15986098 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29117411 # number of UpgradeReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu0.inst 7820 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 74619 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 14 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 4558 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 69243 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156283 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1902250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 133500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 467782250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 379156500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 939000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 284899750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 296279749 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1431092999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 12851285 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 16316631 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29167916 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10001 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20002 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4295181775 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3176975989 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7472157764 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2403250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 105750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 440932000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4671709524 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1009250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 313110000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3450508987 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8879778761 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2403250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 105750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 440932000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4671709524 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1009250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 313110000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3450508987 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8879778761 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6023999 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84465244500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82459599500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166930867999 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8917288738 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8449538500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17366827238 # number of WriteReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4242388114 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4120773678 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8363161792 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1902250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 133500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 467782250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4621544614 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 939000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 284899750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4417053427 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9794254791 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1902250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 133500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 467782250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4621544614 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 939000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 284899750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4417053427 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9794254791 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6012999 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84576136750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82361165750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166943315499 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8951295259 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8415675500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17366970759 # number of WriteReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 116250 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 116250 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 60000 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 60000 # number of StoreCondReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6023999 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 93382533238 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90909138000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184297695237 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000933 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.033619 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020586 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015800 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.986476 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.986420 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.986445 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.570099 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.507513 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541059 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000933 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.255522 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.191498 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091636 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000933 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.255522 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.191498 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091636 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 59880.367207 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62924.545204 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61076.105220 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6012999 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 93527432009 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90776841250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184310286258 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000827 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000280 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015220 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.032633 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009717 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021547 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015834 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.983168 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989084 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.986468 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540668 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.541578 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541110 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000827 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000280 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015220 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.236922 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009717 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.210114 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091688 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000827 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000280 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015220 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.236922 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009717 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.210114 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091688 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61701.627339 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65461.720946 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61973.540577 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.816020 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.545861 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.065604 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.714678 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57104.629002 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 54811.358977 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56106.547358 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57318.776060 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55377.377056 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 56839.678419 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57318.776060 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55377.377056 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 56839.678419 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61956.189415 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63673.743808 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62790.742558 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61935.225800 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63790.613159 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62669.994760 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61935.225800 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63790.613159 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62669.994760 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -829,49 +1066,49 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58475740 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2676749 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2676751 # Transaction distribution +system.toL2Bus.throughput 58456334 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2676393 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2676395 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608201 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2951 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2961 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246143 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246143 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608382 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2974 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246144 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246144 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967991 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5797697 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37845 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149237 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7952770 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62938176 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85577189 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253516 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148824185 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148824185 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 205696 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4963674463 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967115 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798220 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37803 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149157 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7952295 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62908992 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85598765 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253496 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148816461 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148816461 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 207744 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4964319701 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4434137240 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4431802148 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4494378467 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4486267320 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24064152 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24046904 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86310594 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86228845 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48458766 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322134 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322134 # Transaction distribution +system.iobus.throughput 48444532 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322136 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322136 # Transaction distribution system.iobus.trans_dist::WriteReq 8160 # Transaction distribution system.iobus.trans_dist::WriteResp 8160 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -893,12 +1130,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382960 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660588 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660592 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -920,14 +1157,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390329 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390337 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500857 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500857 # Total data (bytes) +system.iobus.tot_pkt_size::total 123500865 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500865 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -973,684 +1210,684 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374796000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41501700007 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41492591518 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 7055231 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5603867 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 360036 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4627391 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3766189 # Number of BTB hits +system.cpu0.branchPred.lookups 7178846 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5689563 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 376334 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4735029 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3823898 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.389038 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 696378 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 37374 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 80.757647 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 708733 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39412 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25604020 # DTB read hits -system.cpu0.dtb.read_misses 37101 # DTB read misses -system.cpu0.dtb.write_hits 6019786 # DTB write hits -system.cpu0.dtb.write_misses 10089 # DTB write misses +system.cpu0.dtb.read_hits 25686724 # DTB read hits +system.cpu0.dtb.read_misses 37672 # DTB read misses +system.cpu0.dtb.write_hits 5882199 # DTB write hits +system.cpu0.dtb.write_misses 9157 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 658 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5563 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1360 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5402 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1359 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 227 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 609 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25641121 # DTB read accesses -system.cpu0.dtb.write_accesses 6029875 # DTB write accesses +system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25724396 # DTB read accesses +system.cpu0.dtb.write_accesses 5891356 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31623806 # DTB hits -system.cpu0.dtb.misses 47190 # DTB misses -system.cpu0.dtb.accesses 31670996 # DTB accesses -system.cpu0.itb.inst_hits 5711817 # ITB inst hits -system.cpu0.itb.inst_misses 6786 # ITB inst misses +system.cpu0.dtb.hits 31568923 # DTB hits +system.cpu0.dtb.misses 46829 # DTB misses +system.cpu0.dtb.accesses 31615752 # DTB accesses +system.cpu0.itb.inst_hits 5794960 # ITB inst hits +system.cpu0.itb.inst_misses 6979 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 658 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2595 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2537 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1280 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1462 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5718603 # ITB inst accesses -system.cpu0.itb.hits 5711817 # DTB hits -system.cpu0.itb.misses 6786 # DTB misses -system.cpu0.itb.accesses 5718603 # DTB accesses -system.cpu0.numCycles 240384739 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5801939 # ITB inst accesses +system.cpu0.itb.hits 5794960 # DTB hits +system.cpu0.itb.misses 6979 # DTB misses +system.cpu0.itb.accesses 5801939 # DTB accesses +system.cpu0.numCycles 241329954 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15036708 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 44324460 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7055231 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4462567 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 9979880 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2348952 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 79920 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 48371030 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1557 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1896 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 40136 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1395788 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 332 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5710035 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 358939 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3057 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 76524952 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.728839 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.080650 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15402359 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 44612176 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7178846 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4532631 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10046821 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2409329 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 81802 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 48777724 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1779 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1966 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 42894 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1416575 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 470 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5793020 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 368373 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3163 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77432013 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.722773 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.070911 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 66552751 86.97% 86.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 648002 0.85% 87.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 843291 1.10% 88.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1146450 1.50% 90.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1051496 1.37% 91.79% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 533927 0.70% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1248962 1.63% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 369566 0.48% 94.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4130507 5.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67393349 87.04% 87.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 663167 0.86% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 850708 1.10% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1161944 1.50% 90.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1070979 1.38% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 538004 0.69% 92.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1258402 1.63% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 372673 0.48% 94.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4122787 5.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 76524952 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.029350 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.184390 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15988793 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49427885 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9067900 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 506950 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1531254 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 959604 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 89006 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 53104636 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 296594 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1531254 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16866391 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20063365 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 26274348 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8616750 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3170765 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 50610961 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7411 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 529520 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2115247 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 208 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 52034450 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 231667374 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 214169305 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 4937 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 38251156 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13783293 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411980 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 362796 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6588533 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9723453 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6830710 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1010499 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1245426 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 47056287 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 968125 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 61041577 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 84130 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9522170 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 23883479 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 244384 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 76524952 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.797669 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.517362 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77432013 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.029747 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.184860 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16324291 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49901037 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9152885 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 482910 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1568783 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 985989 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 93507 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 53239353 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 312067 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1568783 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17193647 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20516369 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 26371209 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8691714 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3088262 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 50703360 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7236 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 484563 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2089605 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 237 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 52223867 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 231534090 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 214067803 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5431 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 38086867 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14136999 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 416413 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 366902 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6391113 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9801074 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6698586 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1023553 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1394670 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 47085778 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 981191 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 61028996 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87181 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9766291 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24255892 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256976 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77432013 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.788162 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.509612 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54759555 71.56% 71.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6733047 8.80% 80.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3420180 4.47% 84.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2920085 3.82% 88.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6164290 8.06% 96.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1467950 1.92% 98.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 772657 1.01% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 222441 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 64747 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55649099 71.87% 71.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6737778 8.70% 80.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3435441 4.44% 85.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2925983 3.78% 88.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6185685 7.99% 96.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1437832 1.86% 98.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 773159 1.00% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 224755 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 62281 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 76524952 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77432013 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27542 0.62% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4220431 94.60% 95.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 213140 4.78% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29912 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4221653 94.70% 95.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 206360 4.63% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 171568 0.28% 0.28% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 28242983 46.27% 46.55% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47431 0.08% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1218 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26256845 43.01% 89.64% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6321515 10.36% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 165947 0.27% 0.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 28282024 46.34% 46.61% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46844 0.08% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1271 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26348641 43.17% 89.87% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6184237 10.13% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 61041577 # Type of FU issued -system.cpu0.iq.rate 0.253933 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4461113 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.073083 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 203189112 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 57554843 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 42164489 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11244 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 5997 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4944 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 65325122 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6000 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 306679 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 61028996 # Type of FU issued +system.cpu0.iq.rate 0.252886 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4457926 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.073046 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 204069737 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57841875 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 42095336 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12029 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6474 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5396 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 65314591 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6384 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 305188 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2052481 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3874 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 14810 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 826086 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2103037 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3902 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15671 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 837358 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17207144 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348104 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17232684 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348213 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1531254 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15306015 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 241273 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 48127004 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 101529 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9723453 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6830710 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 683062 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 53931 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 11240 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 14810 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 174193 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 137584 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 311777 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 60001377 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 25939220 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1040200 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1568783 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15829049 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 237688 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 48167223 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105126 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9801074 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6698586 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 691561 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 54422 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4242 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15671 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 182031 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 143561 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 325592 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 59970791 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26024613 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1058205 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 102592 # number of nop insts executed -system.cpu0.iew.exec_refs 32204815 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5606114 # Number of branches executed -system.cpu0.iew.exec_stores 6265595 # Number of stores executed -system.cpu0.iew.exec_rate 0.249606 # Inst execution rate -system.cpu0.iew.wb_sent 59520960 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 42169433 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22855569 # num instructions producing a value -system.cpu0.iew.wb_consumers 42162980 # num instructions consuming a value +system.cpu0.iew.exec_nop 100254 # number of nop insts executed +system.cpu0.iew.exec_refs 32151728 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5674244 # Number of branches executed +system.cpu0.iew.exec_stores 6127115 # Number of stores executed +system.cpu0.iew.exec_rate 0.248501 # Inst execution rate +system.cpu0.iew.wb_sent 59482820 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 42100732 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22797313 # num instructions producing a value +system.cpu0.iew.wb_consumers 41683102 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.175425 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.542077 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.174453 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.546920 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9402485 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 723741 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 272429 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 74993698 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.510414 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.487877 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9635326 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 724215 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 284304 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75863230 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.501725 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.477269 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61390308 81.86% 81.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6607868 8.81% 90.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1921399 2.56% 93.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1064491 1.42% 94.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 990154 1.32% 95.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 565334 0.75% 96.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 721378 0.96% 97.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 343964 0.46% 98.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1388802 1.85% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 62300247 82.12% 82.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6632163 8.74% 90.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1905948 2.51% 93.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1063803 1.40% 94.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 963459 1.27% 96.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 539688 0.71% 96.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 720050 0.95% 97.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 348558 0.46% 98.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1389314 1.83% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 74993698 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29384265 # Number of instructions committed -system.cpu0.commit.committedOps 38277857 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75863230 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29321704 # Number of instructions committed +system.cpu0.commit.committedOps 38062462 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13675596 # Number of memory references committed -system.cpu0.commit.loads 7670972 # Number of loads committed -system.cpu0.commit.membars 201047 # Number of memory barriers committed -system.cpu0.commit.branches 4859392 # Number of branches committed -system.cpu0.commit.fp_insts 4891 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 33962414 # Number of committed integer instructions. -system.cpu0.commit.function_calls 491145 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1388802 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13559265 # Number of memory references committed +system.cpu0.commit.loads 7698037 # Number of loads committed +system.cpu0.commit.membars 204059 # Number of memory barriers committed +system.cpu0.commit.branches 4889328 # Number of branches committed +system.cpu0.commit.fp_insts 5354 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 33742241 # Number of committed integer instructions. +system.cpu0.commit.function_calls 497179 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1389314 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 120378043 # The number of ROB reads -system.cpu0.rob.rob_writes 96934970 # The number of ROB writes -system.cpu0.timesIdled 903993 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 163859787 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2252055071 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29315772 # Number of Instructions Simulated -system.cpu0.committedOps 38209364 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29315772 # Number of Instructions Simulated -system.cpu0.cpi 8.199843 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.199843 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.121954 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.121954 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 271685631 # number of integer regfile reads -system.cpu0.int_regfile_writes 42795201 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22306 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19768 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15093810 # number of misc regfile reads -system.cpu0.misc_regfile_writes 401151 # number of misc regfile writes -system.cpu0.icache.tags.replacements 983925 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.538497 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10508756 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984437 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.674889 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6941856250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 321.486243 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 190.052254 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.627903 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.371196 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999099 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5171009 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5337747 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10508756 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5171009 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5337747 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10508756 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5171009 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5337747 # number of overall hits -system.cpu0.icache.overall_hits::total 10508756 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 538904 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 526390 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065294 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 538904 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 526390 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065294 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 538904 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 526390 # number of overall misses -system.cpu0.icache.overall_misses::total 1065294 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7446919215 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7105468986 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14552388201 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7446919215 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 7105468986 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14552388201 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7446919215 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 7105468986 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14552388201 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5709913 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5864137 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11574050 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5709913 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5864137 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11574050 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5709913 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5864137 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11574050 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.094380 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089764 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.092042 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.094380 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089764 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.092042 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.094380 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089764 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.092042 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13818.637856 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13498.487787 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13660.443221 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13818.637856 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13498.487787 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13660.443221 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13818.637856 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13498.487787 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13660.443221 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6869 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1025 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 398 # number of cycles access was blocked +system.cpu0.rob.rob_reads 121250209 # The number of ROB reads +system.cpu0.rob.rob_writes 97007351 # The number of ROB writes +system.cpu0.timesIdled 906901 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 163897941 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2251401803 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 29254206 # Number of Instructions Simulated +system.cpu0.committedOps 37994964 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 29254206 # Number of Instructions Simulated +system.cpu0.cpi 8.249410 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.249410 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.121221 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.121221 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 271506841 # number of integer regfile reads +system.cpu0.int_regfile_writes 42814380 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22646 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19918 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15055897 # number of misc regfile reads +system.cpu0.misc_regfile_writes 404161 # number of misc regfile writes +system.cpu0.icache.tags.replacements 983492 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.574238 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10516196 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 984004 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.687148 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6986136250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 318.901478 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 192.672760 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.622854 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.376314 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999168 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5235281 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5280915 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10516196 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5235281 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5280915 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10516196 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5235281 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5280915 # number of overall hits +system.cpu0.icache.overall_hits::total 10516196 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 557620 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 507749 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1065369 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 557620 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 507749 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1065369 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 557620 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 507749 # number of overall misses +system.cpu0.icache.overall_misses::total 1065369 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7715888650 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6834076460 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14549965110 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7715888650 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6834076460 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14549965110 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7715888650 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6834076460 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14549965110 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5792901 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5788664 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11581565 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5792901 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5788664 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11581565 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5792901 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5788664 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11581565 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.096259 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087714 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.091988 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.096259 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087714 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.091988 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.096259 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087714 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.091988 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13837.180607 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13459.556710 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.207137 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13837.180607 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13459.556710 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13657.207137 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13837.180607 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13459.556710 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13657.207137 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6518 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 829 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 410 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.258794 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 1025 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.897561 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 829 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40970 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39858 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 80828 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 40970 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 39858 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 80828 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 40970 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39858 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 80828 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 497934 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 486532 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984466 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 497934 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 486532 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984466 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 497934 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 486532 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984466 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6047465345 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5786819388 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11834284733 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6047465345 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5786819388 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11834284733 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6047465345 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5786819388 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11834284733 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8439000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8439000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8439000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8439000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087205 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.082967 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085058 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087205 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.082967 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.085058 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087205 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.082967 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.085058 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12145.114302 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11894.015991 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12021.019246 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12145.114302 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11894.015991 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12021.019246 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12145.114302 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11894.015991 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12021.019246 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43249 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 38074 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 81323 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43249 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 38074 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 81323 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43249 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 38074 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 81323 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 514371 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 469675 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 984046 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 514371 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 469675 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 984046 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 514371 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 469675 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 984046 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6258994404 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5567069659 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11826064063 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6258994404 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5567069659 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11826064063 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6258994404 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5567069659 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11826064063 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8426500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8426500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8426500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8426500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084967 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.084967 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.084967 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12017.795980 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12017.795980 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12017.795980 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643834 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.993352 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21533253 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644346 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.418773 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 42568250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.929916 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.063436 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497910 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502077 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 643990 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.993324 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21534082 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 644502 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.411971 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 43026250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 255.795317 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 256.198007 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.499600 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.500387 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6778619 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6998983 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13777602 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3655456 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3606248 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261704 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113306 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 129840 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243146 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 115957 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 131727 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247684 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10434075 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10605231 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21039306 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10434075 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10605231 # number of overall hits -system.cpu0.dcache.overall_hits::total 21039306 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 328027 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 420957 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 748984 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1610503 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1351638 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2962141 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7363 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6159 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13522 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 8 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1938530 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1772595 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3711125 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1938530 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1772595 # number of overall misses -system.cpu0.dcache.overall_misses::total 3711125 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5252707334 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6136741422 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11389448756 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 82511290457 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 60760612895 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 143271903352 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104363999 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 83076247 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 187440246 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 129002 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 155002 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 87763997791 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 66897354317 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 154661352108 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 87763997791 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 66897354317 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 154661352108 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7106646 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 7419940 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14526586 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5265959 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4957886 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10223845 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 120669 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 135999 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 256668 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 115959 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 131735 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247694 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12372605 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12377826 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24750431 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12372605 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12377826 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24750431 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.046158 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.056733 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051560 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.305833 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.272624 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289729 # miss rate for WriteReq accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6836118 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6942659 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13778777 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3601868 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3659456 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261324 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114429 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 128738 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243167 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 116989 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 130670 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247659 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10437986 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10602115 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21040101 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10437986 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10602115 # number of overall hits +system.cpu0.dcache.overall_hits::total 21040101 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 327145 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 421730 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 748875 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1520256 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1442024 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2962280 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7436 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6109 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13545 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 12 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1847401 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1863754 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3711155 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1847401 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1863754 # number of overall misses +system.cpu0.dcache.overall_misses::total 3711155 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5258794781 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6175311803 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11434106584 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76116558084 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 73496602051 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 149613160135 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 106253499 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 82007996 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 188261495 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90501 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 181002 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 271503 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 81375352865 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 79671913854 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 161047266719 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 81375352865 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 79671913854 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 161047266719 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7163263 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 7364389 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14527652 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5122124 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5101480 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10223604 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 121865 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 134847 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 256712 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 116995 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 130682 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247677 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12285387 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 12465869 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24751256 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12285387 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12465869 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24751256 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045670 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057266 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.051548 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.296802 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.282668 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.289749 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061018 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045287 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052683 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000017 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000061 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.156679 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.143207 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149942 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.156679 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.143207 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149942 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16013.033482 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14578.071922 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15206.531456 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51233.242321 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44953.318044 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 48367.685182 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14174.113676 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13488.593440 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13861.872948 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16125.250000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15500.200000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45273.479281 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37739.785070 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 41675.058670 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45273.479281 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37739.785070 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41675.058670 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 36870 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 26211 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3510 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 295 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.504274 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 88.850847 # average number of cycles each access was blocked +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045303 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052763 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000051 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000092 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000073 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.150374 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.149509 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.149938 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.150374 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.149509 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.149938 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16074.813251 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14642.808913 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15268.378012 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50068.250403 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 50967.669089 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50506.083198 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14289.066568 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13424.127680 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13898.966039 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15083.500000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15083.500000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15083.500000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44048.559498 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 42748.084701 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43395.456864 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44048.559498 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42748.084701 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43395.456864 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 38322 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 25151 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3482 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 293 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11.005744 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 85.839590 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 608201 # number of writebacks -system.cpu0.dcache.writebacks::total 608201 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 147533 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 215292 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 362825 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1477292 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1235866 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2713158 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 767 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 600 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1367 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1624825 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1451158 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3075983 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1624825 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1451158 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3075983 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 180494 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 205665 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 386159 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 133211 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 115772 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 248983 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6596 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5559 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12155 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 8 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 313705 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 321437 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 635142 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 313705 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 321437 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 635142 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2529137468 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2700943395 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5230080863 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6074560248 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4703819078 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10778379326 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 82036251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64895003 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146931254 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 112998 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 134998 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8603697716 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7404762473 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16008460189 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8603697716 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7404762473 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16008460189 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 92246094501 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90072157750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182318252251 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13667158074 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13097409574 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26764567648 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.writebacks::writebacks 608382 # number of writebacks +system.cpu0.dcache.writebacks::total 608382 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 145500 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 217105 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 362605 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1392355 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1320933 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2713288 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 723 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 626 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1349 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1537855 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1538038 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3075893 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1537855 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1538038 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3075893 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 181645 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 204625 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386270 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127901 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 121091 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248992 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6713 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5483 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12196 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 12 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 18 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 309546 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 325716 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635262 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 309546 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 325716 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635262 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2539210775 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2715181297 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5254392072 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5938244941 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5721716845 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11659961786 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84451251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63563504 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148014755 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 156998 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 235497 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8477455716 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8436898142 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16914353858 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8477455716 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 8436898142 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16914353858 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 92366768250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 89963955251 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182330723501 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13704367995 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13062365000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26766732995 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105913252575 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103169567324 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209082819899 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025398 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027718 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026583 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025297 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023351 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054662 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040875 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047357 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000061 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025355 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025969 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025662 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025355 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025969 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025662 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14012.307711 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13132.732332 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13543.853343 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45601.040815 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40630.023477 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43289.619476 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12437.272741 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11673.862745 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12088.132785 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13499.800000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27426.077735 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23036.434738 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25204.537236 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27426.077735 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23036.434738 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25204.537236 # average overall mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106071136245 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103026320251 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209097456496 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025358 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027786 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026589 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024970 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023736 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055086 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040661 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047508 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000051 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000092 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000073 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025196 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025666 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025196 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025666 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13978.974235 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13269.059484 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13602.899713 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46428.448104 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47251.379913 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46828.660302 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12580.254879 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11592.833121 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12136.336094 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13083.166667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 13083.166667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13083.166667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27386.739664 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25902.621124 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26625.791969 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27386.739664 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25902.621124 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26625.791969 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1665,324 +1902,324 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7417918 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5931932 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 364646 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4881678 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3917644 # Number of BTB hits +system.cpu1.branchPred.lookups 7299586 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5849815 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 347289 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4589899 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3862662 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 80.251995 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 703527 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35801 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 84.155708 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 691728 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34987 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25617777 # DTB read hits -system.cpu1.dtb.read_misses 38543 # DTB read misses -system.cpu1.dtb.write_hits 5691491 # DTB write hits -system.cpu1.dtb.write_misses 8859 # DTB write misses +system.cpu1.dtb.read_hits 25535708 # DTB read hits +system.cpu1.dtb.read_misses 37819 # DTB read misses +system.cpu1.dtb.write_hits 5832824 # DTB write hits +system.cpu1.dtb.write_misses 9748 # DTB write misses system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 781 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5585 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2011 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5631 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2100 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 278 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 659 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25656320 # DTB read accesses -system.cpu1.dtb.write_accesses 5700350 # DTB write accesses +system.cpu1.dtb.perms_faults 694 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25573527 # DTB read accesses +system.cpu1.dtb.write_accesses 5842572 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31309268 # DTB hits -system.cpu1.dtb.misses 47402 # DTB misses -system.cpu1.dtb.accesses 31356670 # DTB accesses -system.cpu1.itb.inst_hits 5866342 # ITB inst hits -system.cpu1.itb.inst_misses 7403 # ITB inst misses +system.cpu1.dtb.hits 31368532 # DTB hits +system.cpu1.dtb.misses 47567 # DTB misses +system.cpu1.dtb.accesses 31416099 # DTB accesses +system.cpu1.itb.inst_hits 5790816 # ITB inst hits +system.cpu1.itb.inst_misses 7158 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 781 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2681 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2684 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1687 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1580 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5873745 # ITB inst accesses -system.cpu1.itb.hits 5866342 # DTB hits -system.cpu1.itb.misses 7403 # DTB misses -system.cpu1.itb.accesses 5873745 # DTB accesses -system.cpu1.numCycles 234836749 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5797974 # ITB inst accesses +system.cpu1.itb.hits 5790816 # DTB hits +system.cpu1.itb.misses 7158 # DTB misses +system.cpu1.itb.accesses 5797974 # DTB accesses +system.cpu1.numCycles 235384601 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14958684 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46343438 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7417918 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4621171 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10240931 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2382000 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 84846 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47705916 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1885 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 51796 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1300956 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.icacheStallCycles 14589178 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46084175 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7299586 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4554390 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10179964 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2322435 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 82610 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 48394674 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1151 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1760 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 51069 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1300436 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5864138 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 361139 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3128 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 75991069 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.753206 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.110012 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 5788667 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 351586 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2955 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76205210 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.749083 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.107109 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 65758157 86.53% 86.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 661623 0.87% 87.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 874095 1.15% 88.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1155735 1.52% 90.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1058337 1.39% 91.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 579833 0.76% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1309635 1.72% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 379645 0.50% 94.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4214009 5.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66032287 86.65% 86.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 647062 0.85% 87.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 866139 1.14% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1142625 1.50% 90.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1039142 1.36% 91.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 573208 0.75% 92.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1303078 1.71% 93.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 377648 0.50% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4224021 5.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 75991069 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.031588 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.197343 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15934805 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 48666188 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9324612 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 504366 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1558997 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1010894 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 88249 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54549781 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 295589 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1558997 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16808618 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19027959 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 26571393 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8885070 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3136997 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 52018175 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 13230 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 586421 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2033878 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 525 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 54353089 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 236755846 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 219276243 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5446 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 40151278 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14201811 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 419760 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 374760 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6443032 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10070258 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6501681 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 951169 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1220754 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 48367033 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1016747 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 62006899 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 95474 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9693963 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24244292 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 257471 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 75991069 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.815976 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521890 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76205210 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.031011 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.195782 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15588837 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 49317422 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9252055 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 521656 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1523167 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 986244 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 83403 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54452083 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 278013 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1523167 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16469267 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19674049 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 26510190 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8818021 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3208448 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51956781 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 13421 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 604219 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2079670 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 451 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 54191440 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237039699 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 219510796 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 4998 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 40313487 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13877953 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 415796 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 370913 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6599828 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9995387 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6641278 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 924791 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1180275 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 48354458 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1004264 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 62036555 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93414 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9463744 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23885542 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 245582 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76205210 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.814072 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.522064 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53638566 70.59% 70.59% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7003056 9.22% 79.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3617950 4.76% 84.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3068918 4.04% 88.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6184871 8.14% 96.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1401826 1.84% 98.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 782382 1.03% 99.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 229717 0.30% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 63783 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53886192 70.71% 70.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6968313 9.14% 79.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3603419 4.73% 84.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3067011 4.02% 88.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6180907 8.11% 96.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1416351 1.86% 98.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 790440 1.04% 99.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 228268 0.30% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 64309 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 75991069 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76205210 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 31911 0.73% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 5 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4158175 94.76% 95.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 198234 4.52% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29954 0.68% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 6 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4154847 94.70% 95.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 202692 4.62% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 192098 0.31% 0.31% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 29460264 47.51% 47.82% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45939 0.07% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 896 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26296905 42.41% 90.31% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6010767 9.69% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 197719 0.32% 0.32% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 29431617 47.44% 47.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46723 0.08% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 843 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26206761 42.24% 90.08% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6152865 9.92% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 62006899 # Type of FU issued -system.cpu1.iq.rate 0.264043 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4388325 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.070772 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 204523942 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59086561 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 43409940 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11938 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6483 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5383 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 66196788 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6338 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 319760 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 62036555 # Type of FU issued +system.cpu1.iq.rate 0.263554 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4387499 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.070724 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 204795562 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58831312 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 43493604 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11047 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6062 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4926 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 66220464 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5871 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 319800 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2083716 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3064 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15874 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 772589 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2036379 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2915 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15518 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 769053 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16902604 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 332952 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16877667 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 333288 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1558997 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14375191 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 227377 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 49504406 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98291 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10070258 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6501681 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 727587 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 51733 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 9370 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15874 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 179251 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 141654 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 320905 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 60955471 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25970384 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1051428 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1523167 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14985510 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 225691 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 49480647 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 96107 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9995387 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6641278 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 719443 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50947 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6143 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15518 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 171517 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 135143 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 306660 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 61000330 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25886068 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1036225 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 120626 # number of nop insts executed -system.cpu1.iew.exec_refs 31928214 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5888736 # Number of branches executed -system.cpu1.iew.exec_stores 5957830 # Number of stores executed -system.cpu1.iew.exec_rate 0.259565 # Inst execution rate -system.cpu1.iew.wb_sent 60476945 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 43415323 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 24094324 # num instructions producing a value -system.cpu1.iew.wb_consumers 44023151 # num instructions consuming a value +system.cpu1.iew.exec_nop 121925 # number of nop insts executed +system.cpu1.iew.exec_refs 31986182 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5823905 # Number of branches executed +system.cpu1.iew.exec_stores 6100114 # Number of stores executed +system.cpu1.iew.exec_rate 0.259152 # Inst execution rate +system.cpu1.iew.wb_sent 60530443 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 43498530 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 24164344 # num instructions producing a value +system.cpu1.iew.wb_consumers 44485345 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.184874 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.547310 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.184798 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.543198 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9567264 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 759276 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 277731 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 74432072 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.530472 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.515537 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9351616 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 758682 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 265186 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 74682043 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.531552 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.520144 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60336914 81.06% 81.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6930423 9.31% 90.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1972494 2.65% 93.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1094851 1.47% 94.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1021489 1.37% 95.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 524731 0.70% 96.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 707921 0.95% 97.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 378966 0.51% 98.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1464283 1.97% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60574973 81.11% 81.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6925092 9.27% 90.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1956264 2.62% 93.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1088628 1.46% 94.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1022152 1.37% 95.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 532797 0.71% 96.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 718663 0.96% 97.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 378466 0.51% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1485008 1.99% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 74432072 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 31082580 # Number of instructions committed -system.cpu1.commit.committedOps 39484127 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 74682043 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 31143561 # Number of instructions committed +system.cpu1.commit.committedOps 39697401 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13715634 # Number of memory references committed -system.cpu1.commit.loads 7986542 # Number of loads committed -system.cpu1.commit.membars 202747 # Number of memory barriers committed -system.cpu1.commit.branches 5103464 # Number of branches committed -system.cpu1.commit.fp_insts 5321 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34903456 # Number of committed integer instructions. -system.cpu1.commit.function_calls 500366 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1464283 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13831233 # Number of memory references committed +system.cpu1.commit.loads 7959008 # Number of loads committed +system.cpu1.commit.membars 199700 # Number of memory barriers committed +system.cpu1.commit.branches 5073252 # Number of branches committed +system.cpu1.commit.fp_insts 4858 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 35121772 # Number of committed integer instructions. +system.cpu1.commit.function_calls 494294 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1485008 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 121076761 # The number of ROB reads -system.cpu1.rob.rob_writes 99705340 # The number of ROB writes -system.cpu1.timesIdled 873554 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 158845680 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2319747272 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 31000692 # Number of Instructions Simulated -system.cpu1.committedOps 39402239 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 31000692 # Number of Instructions Simulated -system.cpu1.cpi 7.575210 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.575210 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.132010 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.132010 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 276194442 # number of integer regfile reads -system.cpu1.int_regfile_writes 44861664 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22699 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19852 # number of floating regfile writes -system.cpu1.misc_regfile_reads 15196533 # number of misc regfile reads -system.cpu1.misc_regfile_writes 431717 # number of misc regfile writes +system.cpu1.rob.rob_reads 121317994 # The number of ROB reads +system.cpu1.rob.rob_writes 99664484 # The number of ROB writes +system.cpu1.timesIdled 865516 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159179391 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2318646728 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 31060678 # Number of Instructions Simulated +system.cpu1.committedOps 39614518 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 31060678 # Number of Instructions Simulated +system.cpu1.cpi 7.578218 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.578218 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.131957 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.131957 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 276434717 # number of integer regfile reads +system.cpu1.int_regfile_writes 44854574 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22375 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19728 # number of floating regfile writes +system.cpu1.misc_regfile_reads 15285924 # number of misc regfile reads +system.cpu1.misc_regfile_writes 428613 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1997,17 +2234,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1441896554007 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1441896554007 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1441896554007 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1441896554007 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518441783518 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1518441783518 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518441783518 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1518441783518 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83067 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83063 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 820046126..87a0dc109 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,143 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.630640 # Number of seconds simulated -sim_ticks 2630640106500 # Number of ticks simulated -final_tick 2630640106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.631415 # Number of seconds simulated +sim_ticks 2631415171500 # Number of ticks simulated +final_tick 2631415171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 544255 # Simulator instruction rate (inst/s) -host_op_rate 692557 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23778611565 # Simulator tick rate (ticks/s) -host_mem_usage 394548 # Number of bytes of host memory used -host_seconds 110.63 # Real time elapsed on the host -sim_insts 60211209 # Number of instructions simulated -sim_ops 76617916 # Number of ops (including micro ops) simulated +host_inst_rate 471038 # Simulator instruction rate (inst/s) +host_op_rate 599389 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20585916294 # Simulator tick rate (ticks/s) +host_mem_usage 424736 # Number of bytes of host memory used +host_seconds 127.83 # Real time elapsed on the host +sim_insts 60210883 # Number of instructions simulated +sim_ops 76617506 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 310496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4767440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 278752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4724944 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 393856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4293936 # Number of bytes read from this memory -system.physmem.bytes_read::total 134022176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 310496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 393856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3690624 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1534960 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1481192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6706776 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 425732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4336188 # Number of bytes read from this memory +system.physmem.bytes_read::total 134022064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 278752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 425732 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704484 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3690496 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1530592 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1485560 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706648 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11054 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 74525 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73861 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6154 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 67119 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690887 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57666 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 383740 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 370298 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811704 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47234229 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 67782 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690904 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57664 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 382648 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 371390 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811702 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47220316 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 118031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1812274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 105932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1795590 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 149719 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1632278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50946603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 118031 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 149719 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1402938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 583493 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 563054 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2549484 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1402938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47234229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 161788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1647854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50931554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 105932 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 161788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267721 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1402476 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 581661 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 564548 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2548685 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1402476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47220316 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 118031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2395767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 105932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2377252 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 149719 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2195332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53496087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690887 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 811704 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15690887 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 811704 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 1004216768 # Total number of bytes read from memory -system.physmem.bytesWritten 51949056 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 134022176 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6706776 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4522 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 980391 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 980205 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 980224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 980428 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 986950 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 980709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 980611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 980420 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 980615 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 980431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 979815 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 979555 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 980154 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 980076 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 980165 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 980109 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6740 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6615 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6627 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6678 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6754 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7054 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7042 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6898 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7014 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6836 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6333 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6140 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6629 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6411 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6640 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6624 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2630635687000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 6680 # Categorize read packet sizes -system.physmem.readPktSize::3 15532032 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152175 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754038 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57666 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1132703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 975077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1005041 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3836885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2878586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2878042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2847020 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 15834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 44009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 29620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 792 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 761 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 748 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 10 # What read queue length does an incoming req see +system.physmem.bw_total::cpu1.inst 161788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2212402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53480239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690904 # Number of read requests accepted +system.physmem.writeReqs 811702 # Number of write requests accepted +system.physmem.readBursts 15690904 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811702 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004216000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1856 # Total number of bytes read from write queue +system.physmem.bytesWritten 6838848 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134022064 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6706648 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 704845 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4517 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 980392 # Per bank write bursts +system.physmem.perBankRdBursts::1 980205 # Per bank write bursts +system.physmem.perBankRdBursts::2 980222 # Per bank write bursts +system.physmem.perBankRdBursts::3 980428 # Per bank write bursts +system.physmem.perBankRdBursts::4 986950 # Per bank write bursts +system.physmem.perBankRdBursts::5 980709 # Per bank write bursts +system.physmem.perBankRdBursts::6 980611 # Per bank write bursts +system.physmem.perBankRdBursts::7 980420 # Per bank write bursts +system.physmem.perBankRdBursts::8 980615 # Per bank write bursts +system.physmem.perBankRdBursts::9 980431 # Per bank write bursts +system.physmem.perBankRdBursts::10 979815 # Per bank write bursts +system.physmem.perBankRdBursts::11 979555 # Per bank write bursts +system.physmem.perBankRdBursts::12 980153 # Per bank write bursts +system.physmem.perBankRdBursts::13 980095 # Per bank write bursts +system.physmem.perBankRdBursts::14 980165 # Per bank write bursts +system.physmem.perBankRdBursts::15 980109 # Per bank write bursts +system.physmem.perBankWrBursts::0 6734 # Per bank write bursts +system.physmem.perBankWrBursts::1 6600 # Per bank write bursts +system.physmem.perBankWrBursts::2 6608 # Per bank write bursts +system.physmem.perBankWrBursts::3 6671 # Per bank write bursts +system.physmem.perBankWrBursts::4 6747 # Per bank write bursts +system.physmem.perBankWrBursts::5 7057 # Per bank write bursts +system.physmem.perBankWrBursts::6 7034 # Per bank write bursts +system.physmem.perBankWrBursts::7 6884 # Per bank write bursts +system.physmem.perBankWrBursts::8 7000 # Per bank write bursts +system.physmem.perBankWrBursts::9 6825 # Per bank write bursts +system.physmem.perBankWrBursts::10 6323 # Per bank write bursts +system.physmem.perBankWrBursts::11 6129 # Per bank write bursts +system.physmem.perBankWrBursts::12 6612 # Per bank write bursts +system.physmem.perBankWrBursts::13 6395 # Per bank write bursts +system.physmem.perBankWrBursts::14 6622 # Per bank write bursts +system.physmem.perBankWrBursts::15 6616 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2631410752000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 6700 # Read request sizes (log2) +system.physmem.readPktSize::3 15532032 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 152172 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 754038 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 57664 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1280991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1124435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1124568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3790382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2700913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2699740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2717442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 51875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 37 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -153,29 +155,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -185,193 +187,315 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37970 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 26627.977877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2487.931344 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31806.056461 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 5445 14.34% 14.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 3318 8.74% 23.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2184 5.75% 28.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1677 4.42% 33.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1130 2.98% 36.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1067 2.81% 39.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 805 2.12% 41.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 712 1.88% 43.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 588 1.55% 44.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 469 1.24% 45.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 450 1.19% 47.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 409 1.08% 48.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 266 0.70% 48.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 255 0.67% 49.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 222 0.58% 50.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 208 0.55% 50.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 140 0.37% 50.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 130 0.34% 51.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 95 0.25% 51.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 109 0.29% 51.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 83 0.22% 52.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 158 0.42% 52.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 757 1.99% 54.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 208 0.55% 55.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 141 0.37% 55.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 116 0.31% 55.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 79 0.21% 55.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 86 0.23% 56.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 52 0.14% 56.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 50 0.13% 56.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 43 0.11% 56.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 55 0.14% 56.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 50 0.13% 56.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 19 0.05% 56.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 25 0.07% 56.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 19 0.05% 56.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 17 0.04% 56.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 20 0.05% 57.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 17 0.04% 57.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 13 0.03% 57.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 10 0.03% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 12 0.03% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 10 0.03% 57.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 7 0.02% 57.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 10 0.03% 57.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 4 0.01% 57.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 9 0.02% 57.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 14 0.04% 57.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 6 0.02% 57.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 9 0.02% 57.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 11 0.03% 57.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 5 0.01% 57.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 7 0.02% 57.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 7 0.02% 57.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 8 0.02% 57.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 10 0.03% 57.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 12 0.03% 57.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 14 0.04% 57.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 7 0.02% 57.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 5 0.01% 57.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 7 0.02% 57.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 5 0.01% 57.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 35 0.09% 57.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 3 0.01% 57.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 2 0.01% 57.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 2 0.01% 57.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 8 0.02% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 5 0.01% 57.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 2 0.01% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 2 0.01% 57.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 7 0.02% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 2 0.01% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 1 0.00% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 3 0.01% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 2 0.01% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 2 0.01% 57.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 2 0.01% 57.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 8 0.02% 57.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 5 0.01% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 3 0.01% 57.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 1 0.00% 57.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 5 0.01% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 1 0.00% 57.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 1 0.00% 57.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 4 0.01% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 3 0.01% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6079 1 0.00% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 2 0.01% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 8 0.02% 57.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 4 0.01% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 3 0.01% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 2 0.01% 57.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 2 0.01% 57.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 2 0.01% 57.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 2 0.01% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 2 0.01% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 17 0.04% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 1 0.00% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 3 0.01% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 5 0.01% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 3 0.01% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 6 0.02% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 7 0.02% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 5 0.01% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 5 0.01% 58.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 2 0.01% 58.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 1 0.00% 58.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 9 0.02% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 3 0.01% 58.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 309 0.81% 59.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 22 0.06% 59.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8575 151 0.40% 59.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8639 180 0.47% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8703 3 0.01% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 1 0.00% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8831 1 0.00% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8895 2 0.01% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-9023 1 0.00% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 1 0.00% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11327 1 0.00% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12863 1 0.00% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14143 1 0.00% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 1 0.00% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15423 2 0.01% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 1 0.00% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 2 0.01% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17215 1 0.00% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21055 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27199 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27967 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 3 0.01% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31039 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31551 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 1 0.00% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32575 1 0.00% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 7 0.02% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 12 0.03% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33855 1 0.00% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47423 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49215 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51263 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55872-55935 1 0.00% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 15142 39.88% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::67392-67455 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37970 # Bytes accessed per row activation -system.physmem.totQLat 300039544000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 394721941500 # Sum of mem lat for all requests -system.physmem.totBusLat 78454290000 # Total cycles spent in databus access -system.physmem.totBankLat 16228107500 # Total cycles spent in bank access -system.physmem.avgQLat 19121.93 # Average queueing delay per request -system.physmem.avgBankLat 1034.24 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25156.17 # Average memory access latency -system.physmem.avgRdBW 381.74 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 19.75 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.95 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.55 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 1.25 # Average write queue length over time -system.physmem.readRowHits 15666199 # Number of row buffer hits during reads -system.physmem.writeRowHits 93719 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.55 # Row buffer hit rate for writes -system.physmem.avgGap 159407.43 # Average gap between requests +system.physmem.bytesPerActivate::samples 90271 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11200.204894 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1031.239605 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16762.903946 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23441 25.97% 25.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14726 16.31% 42.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2829 3.13% 45.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2153 2.39% 47.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1359 1.51% 49.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1176 1.30% 50.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 955 1.06% 51.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1145 1.27% 52.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 612 0.68% 53.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 559 0.62% 54.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 621 0.69% 54.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 534 0.59% 55.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 322 0.36% 55.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 268 0.30% 56.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 218 0.24% 56.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 586 0.65% 57.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 164 0.18% 57.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 127 0.14% 57.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 130 0.14% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 257 0.28% 57.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 105 0.12% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2231 2.47% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 89 0.10% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 142 0.16% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 48 0.05% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 45 0.05% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 41 0.05% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 166 0.18% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 19 0.02% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 18 0.02% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 150 0.17% 61.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 341 0.38% 61.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 18 0.02% 61.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 19 0.02% 61.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 17 0.02% 61.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 76 0.08% 61.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 15 0.02% 61.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 8 0.01% 61.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 16 0.02% 61.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 76 0.08% 61.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 11 0.01% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 6 0.01% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 7 0.01% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 22 0.02% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 8 0.01% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 3 0.00% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 6 0.01% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 382 0.42% 62.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 7 0.01% 62.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 8 0.01% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 6 0.01% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 146 0.16% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 2 0.00% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 137 0.15% 62.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 6 0.01% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 197 0.22% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 7 0.01% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 7 0.01% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 32 0.04% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 137 0.15% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 6 0.01% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 2 0.00% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 6 0.01% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 337 0.37% 63.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 1 0.00% 63.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 1 0.00% 63.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 2 0.00% 63.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 130 0.14% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 2 0.00% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 1 0.00% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 71 0.08% 63.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 129 0.14% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 3 0.00% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 75 0.08% 63.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 4 0.00% 63.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 261 0.29% 64.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 1 0.00% 64.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 1 0.00% 64.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 62 0.07% 64.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 15 0.02% 64.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 204 0.23% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 122 0.14% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 133 0.15% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 389 0.43% 65.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 64 0.07% 65.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 68 0.08% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 120 0.13% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 252 0.28% 65.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 133 0.15% 65.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 13 0.01% 66.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 68 0.08% 66.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 520 0.58% 66.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 68 0.08% 66.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 11 0.01% 66.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 136 0.15% 66.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 250 0.28% 67.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 121 0.13% 67.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 68 0.08% 67.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 65 0.07% 67.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 388 0.43% 67.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 132 0.15% 68.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 1 0.00% 68.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 121 0.13% 68.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10823 2 0.00% 68.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 55 0.06% 68.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 259 0.29% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 71 0.08% 68.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 1 0.00% 68.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 69 0.08% 68.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 128 0.14% 68.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 328 0.36% 69.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 133 0.15% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 193 0.21% 69.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 136 0.15% 69.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 377 0.42% 70.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 11 0.01% 70.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 64 0.07% 70.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 70 0.08% 70.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 322 0.36% 70.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 132 0.15% 70.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 68 0.08% 70.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 129 0.14% 70.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 391 0.43% 71.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 67 0.07% 71.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 129 0.14% 71.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 641 0.71% 72.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 136 0.15% 72.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 66 0.07% 72.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 2 0.00% 72.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 391 0.43% 73.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 128 0.14% 73.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 67 0.07% 73.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 131 0.15% 73.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 320 0.35% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 67 0.07% 73.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 67 0.07% 73.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 13 0.01% 73.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 1 0.00% 73.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 376 0.42% 74.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19591 1 0.00% 74.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 137 0.15% 74.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 192 0.21% 74.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 131 0.15% 74.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 326 0.36% 75.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 124 0.14% 75.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 68 0.08% 75.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21056-21063 1 0.00% 75.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 71 0.08% 75.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 259 0.29% 75.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 56 0.06% 75.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 75.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 120 0.13% 75.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 134 0.15% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 388 0.43% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 64 0.07% 76.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 67 0.07% 76.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 121 0.13% 76.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 253 0.28% 77.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 133 0.15% 77.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 10 0.01% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 70 0.08% 77.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 519 0.57% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 69 0.08% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 10 0.01% 77.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 133 0.15% 78.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 251 0.28% 78.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 120 0.13% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 70 0.08% 78.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 64 0.07% 78.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 387 0.43% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 134 0.15% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 119 0.13% 79.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 56 0.06% 79.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 259 0.29% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 71 0.08% 79.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 68 0.08% 79.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 125 0.14% 80.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 325 0.36% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 133 0.15% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 192 0.21% 80.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 136 0.15% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 377 0.42% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 11 0.01% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 65 0.07% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 69 0.08% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 321 0.36% 81.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 130 0.14% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 67 0.07% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 128 0.14% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 390 0.43% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 1 0.00% 82.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 67 0.07% 82.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 130 0.14% 82.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 640 0.71% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 132 0.15% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 70 0.08% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 1 0.00% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 389 0.43% 84.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 128 0.14% 84.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 67 0.07% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 130 0.14% 84.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 318 0.35% 84.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 68 0.08% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 64 0.07% 85.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 10 0.01% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 377 0.42% 85.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 136 0.15% 85.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 192 0.21% 85.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 132 0.15% 86.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 324 0.36% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 125 0.14% 86.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 68 0.08% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 71 0.08% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 259 0.29% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 56 0.06% 87.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 119 0.13% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 134 0.15% 87.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 387 0.43% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 64 0.07% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 69 0.08% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 119 0.13% 88.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 251 0.28% 88.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 133 0.15% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 9 0.01% 88.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 68 0.08% 88.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 518 0.57% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 69 0.08% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 10 0.01% 89.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 133 0.15% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 252 0.28% 89.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 120 0.13% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 67 0.07% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 64 0.07% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 388 0.43% 90.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 134 0.15% 90.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 119 0.13% 90.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 90.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 56 0.06% 90.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 260 0.29% 90.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 71 0.08% 91.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 69 0.08% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 124 0.14% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 325 0.36% 91.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 131 0.15% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 191 0.21% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 137 0.15% 92.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 375 0.42% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 11 0.01% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 66 0.07% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 66 0.07% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 319 0.35% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 133 0.15% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 67 0.07% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 129 0.14% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 390 0.43% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 1 0.00% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 67 0.07% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 131 0.15% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5359 5.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90271 # Bytes accessed per row activation +system.physmem.totQLat 377292466250 # Total ticks spent queuing +system.physmem.totMemAccLat 474547986250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78454375000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18801145000 # Total ticks spent accessing banks +system.physmem.avgQLat 24045.34 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1198.22 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30243.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.93 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.00 # Data bus utilization in percentage +system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 1.22 # Average write queue length when enqueuing +system.physmem.readRowHits 15616441 # Number of row buffer hits during reads +system.physmem.writeRowHits 91020 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.18 # Row buffer hit rate for writes +system.physmem.avgGap 159454.26 # Average gap between requests +system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 2.38 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -384,249 +508,249 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54407704 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743613 # Transaction distribution -system.membus.trans_dist::ReadResp 16743613 # Transaction distribution +system.membus.throughput 54391586 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743633 # Transaction distribution +system.membus.trans_dist::ReadResp 16743633 # Transaction distribution system.membus.trans_dist::WriteReq 763392 # Transaction distribution system.membus.trans_dist::WriteResp 763392 # Transaction distribution -system.membus.trans_dist::Writeback 57666 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4522 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4522 # Transaction distribution -system.membus.trans_dist::ReadExReq 131350 # Transaction distribution -system.membus.trans_dist::ReadExResp 131350 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 57664 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution +system.membus.trans_dist::ReadExReq 131346 # Transaction distribution +system.membus.trans_dist::ReadExResp 131346 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892496 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279356 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892518 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279376 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343420 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 35343440 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472696 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18870833 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18870589 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143127089 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143127089 # Total data (bytes) +system.membus.tot_pkt_size::total 143126845 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143126845 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1209125000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1220589500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3743000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3747000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18109707000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18118484000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4946568726 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4951896724 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 35058992750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 35075499000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 62061 # number of replacements -system.l2c.tags.tagsinuse 51615.718916 # Cycle average of tags in use -system.l2c.tags.total_refs 1699022 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127446 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.331309 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2575798778500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38215.031353 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000689 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2892.274749 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3021.606158 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4129.656737 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3357.149045 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.583115 # Average percentage of cache occupancy +system.l2c.tags.replacements 62057 # number of replacements +system.l2c.tags.tagsinuse 51615.015118 # Cycle average of tags in use +system.l2c.tags.total_refs 1699237 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127445 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.333101 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2576505750500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38217.986822 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000701 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2603.292629 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3037.110347 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4418.327235 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3338.297198 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583160 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.044133 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046106 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.039723 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.046343 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.063014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.051226 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.787593 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 9999 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3590 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 436599 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 185177 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9919 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3623 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 407829 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 185133 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1241869 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596358 # number of Writeback hits -system.l2c.Writeback_hits::total 596358 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.067418 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.050938 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.787583 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 9914 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3649 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 415311 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 183212 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10008 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3517 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 429187 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 187142 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1241940 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596380 # number of Writeback hits +system.l2c.Writeback_hits::total 596380 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 59730 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 54783 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114513 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9999 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3590 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 436599 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 244907 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9919 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3623 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 407829 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 239916 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356382 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9999 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3590 # number of overall hits -system.l2c.overall_hits::cpu0.inst 436599 # number of overall hits -system.l2c.overall_hits::cpu0.data 244907 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9919 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3623 # number of overall hits -system.l2c.overall_hits::cpu1.inst 407829 # number of overall hits -system.l2c.overall_hits::cpu1.data 239916 # number of overall hits -system.l2c.overall_hits::total 1356382 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 56696 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 57849 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114545 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9914 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3649 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 415311 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 239908 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10008 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3517 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 429187 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 244991 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356485 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9914 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3649 # number of overall hits +system.l2c.overall_hits::cpu0.inst 415311 # number of overall hits +system.l2c.overall_hits::cpu0.data 239908 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 10008 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3517 # number of overall hits +system.l2c.overall_hits::cpu1.inst 429187 # number of overall hits +system.l2c.overall_hits::cpu1.data 244991 # number of overall hits +system.l2c.overall_hits::total 1356485 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4438 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5378 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 3942 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5224 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6154 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4852 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20825 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1446 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1435 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2881 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 69963 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 63028 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 132991 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 6651 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 5006 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20826 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1375 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1512 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2887 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 69398 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 63578 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 132976 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 4438 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 75341 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 3942 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 74622 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6154 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 67880 # number of demand (read+write) misses -system.l2c.demand_misses::total 153816 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6651 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 68584 # number of demand (read+write) misses +system.l2c.demand_misses::total 153802 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 4438 # number of overall misses -system.l2c.overall_misses::cpu0.data 75341 # number of overall misses +system.l2c.overall_misses::cpu0.inst 3942 # number of overall misses +system.l2c.overall_misses::cpu0.data 74622 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6154 # number of overall misses -system.l2c.overall_misses::cpu1.data 67880 # number of overall misses -system.l2c.overall_misses::total 153816 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 122500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 307218750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 368704500 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu1.inst 6651 # number of overall misses +system.l2c.overall_misses::cpu1.data 68584 # number of overall misses +system.l2c.overall_misses::total 153802 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 279121500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 387849000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 89250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 431930250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 347894250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1455959500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 232490 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 232990 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4479114898 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4038724211 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8517839109 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 122500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 307218750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4847819398 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 474818500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 382257500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1524285750 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 256989 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 208991 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 465980 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4923800203 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4505788417 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9429588620 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 279121500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 5311649203 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 89250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 431930250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4386618461 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9973798609 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 122500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 307218750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4847819398 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu1.inst 474818500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4888045917 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 10953874370 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 279121500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 5311649203 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 89250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 431930250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4386618461 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9973798609 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9999 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3592 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 441037 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 190555 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 9920 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 413983 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 189985 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1262694 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 596358 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 596358 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1464 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1443 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2907 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 129693 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 117811 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247504 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9999 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3592 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 441037 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 320248 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9920 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 3623 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 413983 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 307796 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1510198 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9999 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3592 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 441037 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 320248 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9920 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 3623 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 413983 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 307796 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1510198 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000557 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.010063 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.028223 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000101 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.014865 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.025539 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016493 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.987705 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.994456 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991056 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.539451 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.534992 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.537329 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000557 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.010063 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.235258 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000101 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.014865 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.220536 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.101852 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000557 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.010063 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.235258 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000101 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.014865 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.220536 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.101852 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 61250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69224.594412 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 68557.921160 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu1.inst 474818500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4888045917 # number of overall miss cycles +system.l2c.overall_miss_latency::total 10953874370 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 9914 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3651 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 419253 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 188436 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 10009 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 3517 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 435838 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 192148 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1262766 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 596380 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 596380 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1389 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1524 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2913 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 126094 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 121427 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247521 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 9914 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3651 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 419253 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 314530 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 10009 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 3517 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 435838 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 313575 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1510287 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 9914 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3651 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 419253 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 314530 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 10009 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 3517 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 435838 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 313575 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1510287 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000548 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.009402 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.027723 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000100 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.015260 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.026053 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016492 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989921 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992126 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991074 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.550367 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.523590 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.537231 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000548 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.009402 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.237249 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000100 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.015260 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.218716 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.101836 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000548 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.009402 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.237249 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000100 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.015260 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.218716 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.101836 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70807.077626 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 74243.683002 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70186.910952 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 71701.205688 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 69914.021609 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 160.781466 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 162.362369 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 161.568900 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 64021.195460 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 64078.254284 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 64048.237166 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 69224.594412 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 64345.036541 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71390.542776 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 76359.868158 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 73191.479401 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 186.901091 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 138.221561 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 161.406304 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70950.174400 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70870.244692 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 70911.958699 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 70807.077626 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 71180.740304 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 70186.910952 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 64623.135843 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 64842.400069 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 69224.594412 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 64345.036541 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 71390.542776 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 71270.936618 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71220.623724 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 70807.077626 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 71180.740304 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 70186.910952 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 64623.135843 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 64842.400069 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 71390.542776 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 71270.936618 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71220.623724 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -635,129 +759,132 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57666 # number of writebacks -system.l2c.writebacks::total 57666 # number of writebacks +system.l2c.writebacks::writebacks 57664 # number of writebacks +system.l2c.writebacks::total 57664 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 4438 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 5378 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 3942 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 5224 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6154 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4852 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 20825 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1446 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1435 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2881 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 69963 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 63028 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 132991 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6651 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 5006 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 20826 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1375 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1512 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2887 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 69398 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 63578 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 132976 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 4438 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 75341 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 3942 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 74622 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6154 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 67880 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 153816 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6651 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 68584 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 153802 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 4438 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 75341 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 3942 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 74622 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6154 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 67880 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 153816 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 97500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 251180750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 300683500 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu1.inst 6651 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 68584 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 153802 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 229630000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 322854500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 354229750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 286200750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1192468500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14461446 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14352435 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 28813881 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3602203602 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3248593789 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 6850797391 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 97500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 251180750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3902887102 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 391301000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 319831000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1263817750 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13751375 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15121512 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 28872887 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4053929797 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3708851583 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7762781380 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 229630000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4376784297 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 354229750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3534794539 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8043265891 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 251180750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3902887102 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 391301000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4028682583 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9026599130 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 229630000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4376784297 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 354229750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3534794539 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8043265891 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 322980250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84062460250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82598359000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166983799500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8379652001 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8320086501 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16699738502 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 322980250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92442112251 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90918445501 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183683538002 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000557 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010063 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028223 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014865 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025539 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016493 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987705 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.994456 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991056 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.539451 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.534992 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.537329 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000557 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010063 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.235258 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014865 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.220536 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.101852 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000557 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010063 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.235258 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014865 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.220536 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.101852 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56597.735466 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 55909.910747 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_latency::cpu1.inst 391301000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4028682583 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9026599130 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 343871250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83402251750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 842500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83269942750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167016908250 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8431436509 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8268193000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16699629509 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 343871250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91833688259 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 842500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91538135750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183716537759 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000548 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009402 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027723 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015260 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026053 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016492 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989921 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992126 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991074 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.550367 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.523590 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537231 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000548 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009402 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.237249 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015260 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.218716 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.101836 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000548 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009402 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.237249 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015260 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.218716 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.101836 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61802.163093 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57560.895353 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 58986.139736 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 57261.392557 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63889.532561 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60684.612984 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.696864 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.347102 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 51487.266155 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51542.073190 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 51513.240678 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56597.735466 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51802.963884 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58415.657469 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58335.455393 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58377.311545 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58652.733738 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57560.895353 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52074.168223 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 52291.477421 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56597.735466 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51802.963884 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58740.851846 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58689.738300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58652.733738 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57560.895353 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52074.168223 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 52291.477421 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58740.851846 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58689.738300 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -765,6 +892,7 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate @@ -774,45 +902,45 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52764048 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471787 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471787 # Transaction distribution +system.toL2Bus.throughput 52751818 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471631 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471631 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596358 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2907 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2907 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247504 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247504 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1724904 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753314 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20307 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50676 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549201 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54747764 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83776253 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28860 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79676 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138632553 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138632553 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 170668 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808102000 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 596380 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2913 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2913 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247521 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247521 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725079 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753474 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20108 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50543 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549204 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54752376 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83781573 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79692 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138642313 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138642313 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 169620 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808134500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865742750 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865505750 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4428115774 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4420696776 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13092500 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 12940000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30757250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30620250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48142902 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16715359 # Transaction distribution -system.iobus.trans_dist::ReadResp 16715359 # Transaction distribution +system.iobus.throughput 48128720 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16715358 # Transaction distribution +system.iobus.trans_dist::ReadResp 16715358 # Transaction distribution system.iobus.trans_dist::WriteReq 8167 # Transaction distribution system.iobus.trans_dist::WriteResp 8167 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -834,12 +962,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33447052 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33447050 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -861,14 +989,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 126646649 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 126646649 # Total data (bytes) +system.iobus.tot_pkt_size::total 126646645 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 126646645 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -914,141 +1042,141 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374821000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374819000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42581193250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42584048000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7542817 # DTB read hits -system.cpu0.dtb.read_misses 7082 # DTB read misses -system.cpu0.dtb.write_hits 5717425 # DTB write hits -system.cpu0.dtb.write_misses 1778 # DTB write misses +system.cpu0.dtb.read_hits 7352406 # DTB read hits +system.cpu0.dtb.read_misses 6766 # DTB read misses +system.cpu0.dtb.write_hits 5599485 # DTB write hits +system.cpu0.dtb.write_misses 1847 # DTB write misses system.cpu0.dtb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 734 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6542 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 6337 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 149 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 131 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7549899 # DTB read accesses -system.cpu0.dtb.write_accesses 5719203 # DTB write accesses +system.cpu0.dtb.perms_faults 221 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7359172 # DTB read accesses +system.cpu0.dtb.write_accesses 5601332 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13260242 # DTB hits -system.cpu0.dtb.misses 8860 # DTB misses -system.cpu0.dtb.accesses 13269102 # DTB accesses -system.cpu0.itb.inst_hits 30610477 # ITB inst hits -system.cpu0.itb.inst_misses 3712 # ITB inst misses +system.cpu0.dtb.hits 12951891 # DTB hits +system.cpu0.dtb.misses 8613 # DTB misses +system.cpu0.dtb.accesses 12960504 # DTB accesses +system.cpu0.itb.inst_hits 30170189 # ITB inst hits +system.cpu0.itb.inst_misses 3579 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 734 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2775 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2699 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30614189 # ITB inst accesses -system.cpu0.itb.hits 30610477 # DTB hits -system.cpu0.itb.misses 3712 # DTB misses -system.cpu0.itb.accesses 30614189 # DTB accesses -system.cpu0.numCycles 2629428479 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30173768 # ITB inst accesses +system.cpu0.itb.hits 30170189 # DTB hits +system.cpu0.itb.misses 3579 # DTB misses +system.cpu0.itb.accesses 30173768 # DTB accesses +system.cpu0.numCycles 2629696361 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30009354 # Number of instructions committed -system.cpu0.committedOps 38372334 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34511671 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5157 # Number of float alu accesses -system.cpu0.num_func_calls 1080838 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3989390 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34511671 # number of integer instructions -system.cpu0.num_fp_insts 5157 # number of float instructions -system.cpu0.num_int_register_reads 198034256 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36980567 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3554 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1606 # number of times the floating registers were written -system.cpu0.num_mem_refs 13842126 # number of memory refs -system.cpu0.num_load_insts 7871888 # Number of load instructions -system.cpu0.num_store_insts 5970238 # Number of store instructions -system.cpu0.num_idle_cycles 2283161569.446249 # Number of idle cycles -system.cpu0.num_busy_cycles 346266909.553751 # Number of busy cycles -system.cpu0.not_idle_fraction 0.131689 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.868311 # Percentage of idle cycles +system.cpu0.committedInsts 29597158 # Number of instructions committed +system.cpu0.committedOps 37762240 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33970200 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4584 # Number of float alu accesses +system.cpu0.num_func_calls 1050225 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3920547 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33970200 # number of integer instructions +system.cpu0.num_fp_insts 4584 # number of float instructions +system.cpu0.num_int_register_reads 194623734 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36521551 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3225 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1362 # number of times the floating registers were written +system.cpu0.num_mem_refs 13522491 # number of memory refs +system.cpu0.num_load_insts 7673972 # Number of load instructions +system.cpu0.num_store_insts 5848519 # Number of store instructions +system.cpu0.num_idle_cycles 2290697984.129271 # Number of idle cycles +system.cpu0.num_busy_cycles 338998376.870729 # Number of busy cycles +system.cpu0.not_idle_fraction 0.128912 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.871088 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83028 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 856130 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.884273 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60648659 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856642 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.798139 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 19947189250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 210.188035 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 300.696238 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.410524 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.587297 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997821 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 30168630 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30480029 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60648659 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30168630 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30480029 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60648659 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 30168630 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30480029 # number of overall hits -system.cpu0.icache.overall_hits::total 60648659 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 441847 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 414795 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856642 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 441847 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 414795 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 856642 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 441847 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 414795 # number of overall misses -system.cpu0.icache.overall_misses::total 856642 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6019417250 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5775014750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11794432000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6019417250 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 5775014750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11794432000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6019417250 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 5775014750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11794432000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30610477 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 30894824 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61505301 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30610477 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 30894824 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61505301 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30610477 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 30894824 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61505301 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014435 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013426 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013928 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014435 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013426 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013928 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014435 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013426 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013928 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13623.306823 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13922.575610 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13768.215894 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13623.306823 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13922.575610 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13768.215894 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13623.306823 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13922.575610 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13768.215894 # average overall miss latency +system.cpu0.kern.inst.quiesce 83029 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 856199 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.856725 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60648231 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 856711 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.791937 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 20135568250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 208.641443 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 302.215282 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.407503 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.590264 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997767 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29750188 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30898043 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60648231 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29750188 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30898043 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60648231 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29750188 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30898043 # number of overall hits +system.cpu0.icache.overall_hits::total 60648231 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 420001 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 436711 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 856712 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 420001 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 436711 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 856712 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 420001 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 436711 # number of overall misses +system.cpu0.icache.overall_misses::total 856712 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5711192500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6097938000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11809130500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5711192500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6097938000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11809130500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5711192500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6097938000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11809130500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30170189 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 31334754 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 61504943 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30170189 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 31334754 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 61504943 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30170189 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 31334754 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 61504943 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013921 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013937 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013929 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013921 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013937 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013929 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013921 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013937 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013929 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13598.045005 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13963.325861 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13784.247799 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13598.045005 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13963.325861 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13784.247799 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13598.045005 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13963.325861 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13784.247799 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1057,158 +1185,162 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 441847 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 414795 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 856642 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 441847 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 414795 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 856642 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 441847 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 414795 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 856642 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5133544750 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 4942408250 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10075953000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5133544750 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 4942408250 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10075953000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5133544750 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 4942408250 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10075953000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 414413750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 414413750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 414413750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 414413750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014435 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013426 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013928 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014435 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.013426 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.013928 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014435 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.013426 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013928 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11618.376384 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11915.303343 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11762.151517 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11618.376384 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11915.303343 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11762.151517 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11618.376384 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11915.303343 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11762.151517 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 420001 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 436711 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 856712 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 420001 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 436711 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 856712 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 420001 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 436711 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 856712 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869726500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5221934000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10091660500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869726500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5221934000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10091660500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869726500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5221934000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10091660500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 435321250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1072000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 435321250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1072000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013921 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013937 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013929 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013921 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.013937 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013929 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013921 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.013937 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013929 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11594.559299 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11957.413484 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11779.525091 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11594.559299 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11957.413484 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11779.525091 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11594.559299 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11957.413484 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11779.525091 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 627532 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.881676 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23660522 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 628044 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.673351 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 640880250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 182.734555 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 329.147121 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.356903 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.642865 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999769 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6634061 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6564802 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13198863 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5075609 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 4899184 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9974793 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 120623 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 115578 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236201 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126785 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 120973 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247758 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11709670 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 11463986 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 23173656 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11709670 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 11463986 # number of overall hits -system.cpu0.dcache.overall_hits::total 23173656 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 184394 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 184588 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 368982 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 131157 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 119254 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 250411 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6161 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5397 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11558 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 315551 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 303842 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 619393 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 315551 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 303842 # number of overall misses -system.cpu0.dcache.overall_misses::total 619393 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2725468500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2705402500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5430871000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5537493548 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5008087224 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10545580772 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 82157000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 77679750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 159836750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8262962048 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 7713489724 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 15976451772 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8262962048 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 7713489724 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 15976451772 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6818455 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6749390 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13567845 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5206766 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5018438 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10225204 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126784 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 120975 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 247759 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126785 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 120973 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247758 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12025221 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11767828 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23793049 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12025221 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11767828 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23793049 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027043 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027349 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.027195 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025190 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023763 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.024490 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048594 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044613 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046650 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026241 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025820 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026241 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025820 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14780.678872 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14656.437580 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14718.525565 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42220.343161 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41995.129924 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42113.089169 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13335.010550 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14393.135075 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13829.101056 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26185.821145 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25386.515768 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25793.723487 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26185.821145 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 25386.515768 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 25793.723487 # average overall miss latency +system.cpu0.dcache.tags.replacements 627593 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.877442 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23660330 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 628105 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.669386 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 182.884282 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 328.993161 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.357196 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.642565 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999761 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6452957 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6745780 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13198737 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4964348 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 5010385 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9974733 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118524 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117664 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236188 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 124634 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 123125 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247759 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11417305 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 11756165 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 23173470 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11417305 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 11756165 # number of overall hits +system.cpu0.dcache.overall_hits::total 23173470 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 182326 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 186686 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 369012 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 127483 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 122951 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 250434 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6110 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5462 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11572 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 309809 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 309637 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 619446 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 309809 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 309637 # number of overall misses +system.cpu0.dcache.overall_misses::total 619446 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2717177250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2764634500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5481811750 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5932563172 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5512471095 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11445034267 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 81881250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 78503500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 160384750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8649740422 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 8277105595 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 16926846017 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8649740422 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 8277105595 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 16926846017 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6635283 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6932466 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13567749 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5091831 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5133336 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10225167 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124634 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 123126 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 247760 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 124634 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123125 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247759 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11727114 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 12065802 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 23792916 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11727114 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12065802 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23792916 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027478 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026929 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.027198 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025037 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023951 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.024492 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049024 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044361 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046706 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026418 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025662 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026418 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025662 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14902.851212 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14809.008174 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14855.375299 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46536.112046 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44834.699148 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45700.800478 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13401.186579 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14372.665690 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13859.726063 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27919.590528 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26731.642520 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 27325.781451 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27919.590528 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26731.642520 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 27325.781451 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1217,77 +1349,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596358 # number of writebacks -system.cpu0.dcache.writebacks::total 596358 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184394 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 184588 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 368982 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131157 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 119254 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250411 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6161 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5397 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11558 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 315551 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 303842 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 619393 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 315551 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 303842 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 619393 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2354074500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2333925500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4688000000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5241357452 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4739135776 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9980493228 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69822000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66822250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136644250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7595431952 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7073061276 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 14668493228 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7595431952 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7073061276 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14668493228 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91831657250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90223318750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182054976000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13223525999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13011841499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235367498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105055183249 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103235160249 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208290343498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027043 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027349 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027195 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025190 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023763 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048594 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044613 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046650 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026241 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025820 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026241 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025820 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12766.546092 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12643.971981 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.226813 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39962.468278 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39739.847519 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39856.448910 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11332.900503 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12381.369279 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11822.482263 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24070.378329 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23278.747757 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23682.045532 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24070.378329 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23278.747757 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23682.045532 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 596380 # number of writebacks +system.cpu0.dcache.writebacks::total 596380 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182326 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186686 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369012 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127483 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 122951 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250434 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6110 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5462 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11572 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 309809 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 309637 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619446 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 309809 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 309637 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619446 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2351238750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2390198500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741437250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5650406828 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5242308905 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10892715733 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69656750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67531500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137188250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8001645578 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7632507405 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15634152983 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8001645578 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7632507405 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15634152983 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91105263250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90961118500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182066381750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13264461491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12970911500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235372991 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104369724741 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103932030000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208301754741 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027478 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026929 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027198 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025037 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023951 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024492 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049024 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044361 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046706 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026418 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025662 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026418 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025662 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12895.795169 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12803.308764 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12849.005588 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44322.826008 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42637.383226 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43495.354996 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11400.450082 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12363.877700 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11855.189250 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25827.673108 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24649.855815 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25238.927982 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25827.673108 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24649.855815 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25238.927982 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1300,68 +1432,68 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7456887 # DTB read hits -system.cpu1.dtb.read_misses 7096 # DTB read misses -system.cpu1.dtb.write_hits 5515190 # DTB write hits -system.cpu1.dtb.write_misses 1853 # DTB write misses -system.cpu1.dtb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7647205 # DTB read hits +system.cpu1.dtb.read_misses 7298 # DTB read misses +system.cpu1.dtb.write_hits 5633094 # DTB write hits +system.cpu1.dtb.write_misses 1843 # DTB write misses +system.cpu1.dtb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 705 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6662 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 730 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6730 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7463983 # DTB read accesses -system.cpu1.dtb.write_accesses 5517043 # DTB write accesses +system.cpu1.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7654503 # DTB read accesses +system.cpu1.dtb.write_accesses 5634937 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12972077 # DTB hits -system.cpu1.dtb.misses 8949 # DTB misses -system.cpu1.dtb.accesses 12981026 # DTB accesses -system.cpu1.itb.inst_hits 30894824 # ITB inst hits -system.cpu1.itb.inst_misses 3669 # ITB inst misses +system.cpu1.dtb.hits 13280299 # DTB hits +system.cpu1.dtb.misses 9141 # DTB misses +system.cpu1.dtb.accesses 13289440 # DTB accesses +system.cpu1.itb.inst_hits 31334771 # ITB inst hits +system.cpu1.itb.inst_misses 3728 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 705 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2813 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 730 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2858 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 30898493 # ITB inst accesses -system.cpu1.itb.hits 30894824 # DTB hits -system.cpu1.itb.misses 3669 # DTB misses -system.cpu1.itb.accesses 30898493 # DTB accesses -system.cpu1.numCycles 2631851734 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 31338499 # ITB inst accesses +system.cpu1.itb.hits 31334771 # DTB hits +system.cpu1.itb.misses 3728 # DTB misses +system.cpu1.itb.accesses 31338499 # DTB accesses +system.cpu1.numCycles 2633133982 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30201855 # Number of instructions committed -system.cpu1.committedOps 38245582 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34372038 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5112 # Number of float alu accesses -system.cpu1.num_func_calls 1059508 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3959978 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34372038 # number of integer instructions -system.cpu1.num_fp_insts 5112 # number of float instructions -system.cpu1.num_int_register_reads 196814123 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37215593 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3939 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1174 # number of times the floating registers were written -system.cpu1.num_mem_refs 13557754 # number of memory refs -system.cpu1.num_load_insts 7792008 # Number of load instructions -system.cpu1.num_store_insts 5765746 # Number of store instructions -system.cpu1.num_idle_cycles 2293589601.195636 # Number of idle cycles -system.cpu1.num_busy_cycles 338262132.804364 # Number of busy cycles -system.cpu1.not_idle_fraction 0.128526 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.871474 # Percentage of idle cycles +system.cpu1.committedInsts 30613725 # Number of instructions committed +system.cpu1.committedOps 38855266 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34913201 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5685 # Number of float alu accesses +system.cpu1.num_func_calls 1090107 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4028756 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34913201 # number of integer instructions +system.cpu1.num_fp_insts 5685 # number of float instructions +system.cpu1.num_int_register_reads 200222637 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37674133 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4268 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written +system.cpu1.num_mem_refs 13877284 # number of memory refs +system.cpu1.num_load_insts 7989860 # Number of load instructions +system.cpu1.num_store_insts 5887424 # Number of store instructions +system.cpu1.num_idle_cycles 2288817928.029144 # Number of idle cycles +system.cpu1.num_busy_cycles 344316053.970855 # Number of busy cycles +system.cpu1.not_idle_fraction 0.130763 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.869237 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1378,10 +1510,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1478384126250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1478384126250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1478384126250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1478384126250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557205456000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1557205456000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557205456000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1557205456000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index ded25c3bb..8fd17006a 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,133 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.149802 # Number of seconds simulated -sim_ticks 5149801602000 # Number of ticks simulated -final_tick 5149801602000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133932 # Number of seconds simulated +sim_ticks 5133932129000 # Number of ticks simulated +final_tick 5133932129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149544 # Simulator instruction rate (inst/s) -host_op_rate 295611 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1888705545 # Simulator tick rate (ticks/s) -host_mem_usage 733444 # Number of bytes of host memory used -host_seconds 2726.63 # Real time elapsed on the host -sim_insts 407752265 # Number of instructions simulated -sim_ops 806021401 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2464448 # Number of bytes read from this memory +host_inst_rate 157497 # Simulator instruction rate (inst/s) +host_op_rate 311329 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1982921852 # Simulator tick rate (ticks/s) +host_mem_usage 759792 # Number of bytes of host memory used +host_seconds 2589.07 # Real time elapsed on the host +sim_insts 407772261 # Number of instructions simulated +sim_ops 806052921 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2442496 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1029696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10712000 # Number of bytes read from this memory -system.physmem.bytes_read::total 14210368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1029696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1029696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9492864 # Number of bytes written to this memory -system.physmem.bytes_written::total 9492864 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38507 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1029568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10759232 # Number of bytes read from this memory +system.physmem.bytes_read::total 14235520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1029568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1029568 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9509568 # Number of bytes written to this memory +system.physmem.bytes_written::total 9509568 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38164 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167375 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222037 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148326 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148326 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 478552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 758 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16087 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168113 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222430 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148587 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148587 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 475755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 760 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 199949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2080080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2759401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199949 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199949 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1843346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1843346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1843346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 478552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 200542 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2095710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2772830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 200542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 200542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1852297 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1852297 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1852297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 475755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 760 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2080080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4602747 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222037 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 148326 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 222037 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 148326 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 14210368 # Total number of bytes read from memory -system.physmem.bytesWritten 9492864 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14210368 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9492864 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 1678 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 14222 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 14028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 14693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 13767 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 13963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13415 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 13462 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13512 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 13712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 14980 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 14150 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13362 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 13288 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9612 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 9534 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 9830 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 9200 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 9484 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 9208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 9093 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 9396 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8748 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8829 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 9077 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 9138 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 10300 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 9366 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8795 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8716 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry -system.physmem.totGap 5149801548000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 222037 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 148326 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 173642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1084 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.bw_total::cpu.inst 200542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2095710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4625127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222430 # Number of read requests accepted +system.physmem.writeReqs 148587 # Number of write requests accepted +system.physmem.readBursts 222430 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 148587 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14231616 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3904 # Total number of bytes read from write queue +system.physmem.bytesWritten 9508480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14235520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9509568 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 61 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1723 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 14853 # Per bank write bursts +system.physmem.perBankRdBursts::1 13635 # Per bank write bursts +system.physmem.perBankRdBursts::2 14415 # Per bank write bursts +system.physmem.perBankRdBursts::3 13770 # Per bank write bursts +system.physmem.perBankRdBursts::4 14136 # Per bank write bursts +system.physmem.perBankRdBursts::5 13341 # Per bank write bursts +system.physmem.perBankRdBursts::6 13755 # Per bank write bursts +system.physmem.perBankRdBursts::7 13953 # Per bank write bursts +system.physmem.perBankRdBursts::8 13590 # Per bank write bursts +system.physmem.perBankRdBursts::9 13369 # Per bank write bursts +system.physmem.perBankRdBursts::10 13469 # Per bank write bursts +system.physmem.perBankRdBursts::11 13962 # Per bank write bursts +system.physmem.perBankRdBursts::12 14252 # Per bank write bursts +system.physmem.perBankRdBursts::13 14454 # Per bank write bursts +system.physmem.perBankRdBursts::14 13844 # Per bank write bursts +system.physmem.perBankRdBursts::15 13571 # Per bank write bursts +system.physmem.perBankWrBursts::0 10225 # Per bank write bursts +system.physmem.perBankWrBursts::1 9089 # Per bank write bursts +system.physmem.perBankWrBursts::2 9605 # Per bank write bursts +system.physmem.perBankWrBursts::3 9165 # Per bank write bursts +system.physmem.perBankWrBursts::4 9475 # Per bank write bursts +system.physmem.perBankWrBursts::5 8866 # Per bank write bursts +system.physmem.perBankWrBursts::6 9032 # Per bank write bursts +system.physmem.perBankWrBursts::7 9363 # Per bank write bursts +system.physmem.perBankWrBursts::8 8843 # Per bank write bursts +system.physmem.perBankWrBursts::9 8764 # Per bank write bursts +system.physmem.perBankWrBursts::10 9099 # Per bank write bursts +system.physmem.perBankWrBursts::11 9352 # Per bank write bursts +system.physmem.perBankWrBursts::12 9596 # Per bank write bursts +system.physmem.perBankWrBursts::13 9639 # Per bank write bursts +system.physmem.perBankWrBursts::14 9447 # Per bank write bursts +system.physmem.perBankWrBursts::15 9010 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 5133932076000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 222430 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 148587 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 174915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21440 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 749 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 638 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -137,343 +139,366 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62488 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 379.140187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 154.041653 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1280.875932 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 27817 44.52% 44.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 9622 15.40% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 5951 9.52% 69.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 3940 6.31% 75.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 2520 4.03% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1986 3.18% 82.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1542 2.47% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 1215 1.94% 87.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 1005 1.61% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 910 1.46% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 598 0.96% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 543 0.87% 92.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 367 0.59% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 364 0.58% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 356 0.57% 94.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 454 0.73% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 284 0.45% 95.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 192 0.31% 95.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 180 0.29% 95.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 146 0.23% 96.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 174 0.28% 96.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 177 0.28% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 484 0.77% 97.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 176 0.28% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 118 0.19% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 94 0.15% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 80 0.13% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 58 0.09% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 28 0.04% 98.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 25 0.04% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 31 0.05% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 34 0.05% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 13 0.02% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 15 0.02% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 10 0.02% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 19 0.03% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 17 0.03% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 8 0.01% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 10 0.02% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 8 0.01% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 3 0.00% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 9 0.01% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 5 0.01% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 9 0.01% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 4 0.01% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 3 0.00% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 7 0.01% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 2 0.00% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 3 0.00% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 3 0.00% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 5 0.01% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 14 0.02% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 5 0.01% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 4 0.01% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 6 0.01% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 11 0.02% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 3 0.00% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 5 0.01% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 1 0.00% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 21 0.03% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 7 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 4 0.01% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 6 0.01% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 3 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 5 0.01% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 4 0.01% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 3 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 4 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 2 0.00% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 3 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 4 0.01% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 2 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 2 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 2 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 2 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 2 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 1 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 2 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 1 0.00% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 6 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 2 0.00% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 7 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 1 0.00% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 2 0.00% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 2 0.00% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 4 0.01% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 2 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 2 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 2 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 1 0.00% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 339 0.54% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9411 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 8 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 3 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 4 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10755 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12099 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 3 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 28 0.04% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 15 0.02% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 10 0.02% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 9 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 7 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 4 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 5 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 3 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 5 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 6 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 3 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 4 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 6 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 6 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 7 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 6 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 4 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 8 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 6 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 10 0.02% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 12 0.02% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 11 0.02% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 62 0.10% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 3 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17219 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62488 # Bytes accessed per row activation -system.physmem.totQLat 4021160000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8281507500 # Sum of mem lat for all requests -system.physmem.totBusLat 1109590000 # Total cycles spent in databus access -system.physmem.totBankLat 3150757500 # Total cycles spent in bank access -system.physmem.avgQLat 18120.03 # Average queueing delay per request -system.physmem.avgBankLat 14197.85 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 37317.87 # Average memory access latency -system.physmem.avgRdBW 2.76 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.84 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.76 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.84 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 6034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 6271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 7044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 7025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 7044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 7124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 7641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 7124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 7239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 25 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 69161 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 343.214933 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 150.395098 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1078.627974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 31181 45.08% 45.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 10634 15.38% 60.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 6892 9.97% 70.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 4363 6.31% 76.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2774 4.01% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 2145 3.10% 83.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1632 2.36% 86.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 1184 1.71% 87.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 1083 1.57% 89.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 997 1.44% 90.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 641 0.93% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 593 0.86% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 458 0.66% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 430 0.62% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 348 0.50% 94.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 543 0.79% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 251 0.36% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 231 0.33% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 148 0.21% 96.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 131 0.19% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 159 0.23% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 414 0.60% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 146 0.21% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 132 0.19% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 102 0.15% 97.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 88 0.13% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 56 0.08% 98.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 31 0.04% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 34 0.05% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 24 0.03% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 33 0.05% 98.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 49 0.07% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 19 0.03% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 10 0.01% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 32 0.05% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 8 0.01% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 7 0.01% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 11 0.02% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 29 0.04% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 12 0.02% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.00% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 32 0.05% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 7 0.01% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 13 0.02% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 8 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 25 0.04% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 5 0.01% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 4 0.01% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 26 0.04% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.00% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 7 0.01% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 5 0.01% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 31 0.04% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 9 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 7 0.01% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 28 0.04% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 5 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 17 0.02% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 2 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 24 0.03% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 3 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 2 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 22 0.03% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 3 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 28 0.04% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 2 0.00% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 2 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 23 0.03% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 3 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 3 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 3 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 26 0.04% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 1 0.00% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 22 0.03% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 5 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 4 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 2 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 26 0.04% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 3 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 25 0.04% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 6 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 3 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 5 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 25 0.04% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 2 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 3 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 26 0.04% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 3 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 76 0.11% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 4 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 6 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 6 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 6 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 11 0.02% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 3 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 3 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 2 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 14 0.02% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 3 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 3 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 6 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 3 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 4 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 4 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11331 2 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 3 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12099 4 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 2 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 2 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 2 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 3 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 5 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 5 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 3 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 20 0.03% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 9 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 7 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 4 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 5 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 4 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 9 0.01% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 5 0.01% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 42 0.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69161 # Bytes accessed per row activation +system.physmem.totQLat 5163279754 # Total ticks spent queuing +system.physmem.totMemAccLat 9388468504 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1111845000 # Total ticks spent in databus transfers +system.physmem.totBankLat 3113343750 # Total ticks spent accessing banks +system.physmem.avgQLat 23219.42 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14000.80 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 42220.22 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 9.63 # Average write queue length over time -system.physmem.readRowHits 198603 # Number of row buffer hits during reads -system.physmem.writeRowHits 109131 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.58 # Row buffer hit rate for writes -system.physmem.avgGap 13904740.88 # Average gap between requests -system.membus.throughput 5073674 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662109 # Transaction distribution -system.membus.trans_dist::ReadResp 662107 # Transaction distribution -system.membus.trans_dist::WriteReq 13770 # Transaction distribution -system.membus.trans_dist::WriteResp 13770 # Transaction distribution -system.membus.trans_dist::Writeback 148326 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2172 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1696 # Transaction distribution -system.membus.trans_dist::ReadExReq 179020 # Transaction distribution -system.membus.trans_dist::ReadExResp 179014 # Transaction distribution -system.membus.trans_dist::MessageReq 1646 # Transaction distribution -system.membus.trans_dist::MessageResp 1646 # Transaction distribution -system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471038 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775088 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473242 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1719372 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132805 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 132805 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1855469 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6584 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6584 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241802 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550173 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18252032 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20044007 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5451200 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5451200 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25501791 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25501791 # Total data (bytes) -system.membus.snoop_data_through_bus 626624 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 250581000 # Layer occupancy (ticks) +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.54 # Average write queue length when enqueuing +system.physmem.readRowHits 193089 # Number of row buffer hits during reads +system.physmem.writeRowHits 108689 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes +system.physmem.avgGap 13837457.79 # Average gap between requests +system.physmem.pageHitRate 81.35 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.14 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 5101771 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662370 # Transaction distribution +system.membus.trans_dist::ReadResp 662362 # Transaction distribution +system.membus.trans_dist::WriteReq 13778 # Transaction distribution +system.membus.trans_dist::WriteResp 13778 # Transaction distribution +system.membus.trans_dist::Writeback 148587 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2227 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1742 # Transaction distribution +system.membus.trans_dist::ReadExReq 179504 # Transaction distribution +system.membus.trans_dist::ReadExResp 179502 # Transaction distribution +system.membus.trans_dist::MessageReq 1643 # Transaction distribution +system.membus.trans_dist::MessageResp 1643 # Transaction distribution +system.membus.trans_dist::BadAddressError 8 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721244 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1856992 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550145 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18315904 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20107877 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5429184 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5429184 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25543633 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25543633 # Total data (bytes) +system.membus.snoop_data_through_bus 648512 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 250559500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583304500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583301000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3292000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1605050249 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1608447497 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1646000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3149132971 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3153020380 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429400997 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429468745 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 47576 # number of replacements -system.iocache.tags.tagsinuse 0.153339 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.103982 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992838664000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.153339 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.009584 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.009584 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses +system.iocache.tags.warmup_cycle 4992954297000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103982 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006499 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses -system.iocache.demand_misses::total 47630 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses -system.iocache.overall_misses::total 47630 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152977935 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 152977935 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10361858110 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10361858110 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10514836045 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10514836045 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10514836045 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10514836045 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses +system.iocache.demand_misses::total 47631 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses +system.iocache.overall_misses::total 47631 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149420946 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 149420946 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11534885027 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11534885027 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 11684305973 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11684305973 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 11684305973 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11684305973 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -482,40 +507,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 168107.620879 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 168107.620879 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 221786.346533 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 221786.346533 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 220760.781965 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 220760.781965 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 220760.781965 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 220760.781965 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 148180 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164018.601537 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 164018.601537 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 246893.943215 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 246893.943215 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 245308.852911 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 245308.852911 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 173314 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 13622 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10321 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.877991 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 16.792365 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46668 # number of writebacks -system.iocache.writebacks::total 46668 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46667 # number of writebacks +system.iocache.writebacks::total 46667 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105623935 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 105623935 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7930990116 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7930990116 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8036614051 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8036614051 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8036614051 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8036614051 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 102021946 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 102021946 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9103892537 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9103892537 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9205914483 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9205914483 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -524,18 +549,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116070.258242 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 116070.258242 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169755.781592 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 169755.781592 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 168730.087151 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 168730.087151 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 168730.087151 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 168730.087151 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111988.963776 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 111988.963776 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 194860.713549 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 194860.713549 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -545,16 +570,16 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 636182 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225558 # Transaction distribution -system.iobus.trans_dist::ReadResp 225558 # Transaction distribution -system.iobus.trans_dist::WriteReq 57591 # Transaction distribution -system.iobus.trans_dist::WriteResp 57591 # Transaction distribution -system.iobus.trans_dist::MessageReq 1646 # Transaction distribution -system.iobus.trans_dist::MessageResp 1646 # Transaction distribution +system.iobus.throughput 638153 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225567 # Transaction distribution +system.iobus.trans_dist::ReadResp 225567 # Transaction distribution +system.iobus.trans_dist::WriteReq 57606 # Transaction distribution +system.iobus.trans_dist::WriteResp 57606 # Transaction distribution +system.iobus.trans_dist::MessageReq 1643 # Transaction distribution +system.iobus.trans_dist::MessageResp 1643 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) @@ -570,15 +595,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3292 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3292 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569590 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569632 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) @@ -594,20 +619,20 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 241802 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6584 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6584 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276210 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276210 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3927144 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3276232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276232 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3917850 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -637,456 +662,456 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424444048 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424362228 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460167000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53407003 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53078255 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1646000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 85588006 # Number of BP lookups -system.cpu.branchPred.condPredicted 85588006 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 877454 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79215990 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77530840 # Number of BTB hits +system.cpu.branchPred.lookups 85592238 # Number of BP lookups +system.cpu.branchPred.condPredicted 85592238 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 882873 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79245732 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77532748 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.872715 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1437704 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180381 # Number of incorrect RAS predictions. -system.cpu.numCycles 453669464 # number of cpu cycles simulated +system.cpu.branchPred.BTBHitPct 97.838390 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1439092 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180819 # Number of incorrect RAS predictions. +system.cpu.numCycles 453841851 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25482716 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422686689 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85588006 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78968544 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162633276 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3972302 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 106554 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 71193509 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 45334 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 89294 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 278 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8469801 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 382535 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2385 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 262601517 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.178991 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.411463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25587982 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422693278 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85592238 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78971840 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162652701 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3982002 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 104057 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 71419426 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 42857 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 89331 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 200 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8481476 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 385696 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2322 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 262951613 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.174902 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.411090 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 100383881 38.23% 38.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1533037 0.58% 38.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71821115 27.35% 66.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 895642 0.34% 66.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1564995 0.60% 67.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2390879 0.91% 68.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1017520 0.39% 68.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1329446 0.51% 68.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81665002 31.10% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 100714901 38.30% 38.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1542522 0.59% 38.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71823019 27.31% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 902488 0.34% 66.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1566536 0.60% 67.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2391041 0.91% 68.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1017988 0.39% 68.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1324647 0.50% 68.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81668471 31.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 262601517 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.188657 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.931706 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29392698 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 68340203 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158479192 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3338868 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3050556 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832478930 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 959 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3050556 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32088006 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 43079490 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12529275 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158770454 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13083736 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829577701 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21771 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6064622 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5141489 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 991205554 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800191267 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1106790785 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 123 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963930499 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27275048 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 452761 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 458610 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29575764 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16714812 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9817459 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1139197 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 962008 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 824812969 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1184552 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 820895267 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 151456 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19155682 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29185416 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 129934 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 262601517 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.126011 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.400353 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 262951613 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.188595 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.931367 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29471400 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 68588335 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158500700 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3336119 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3055059 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832519072 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 997 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3055059 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32166739 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 43365867 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12492763 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158788078 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13083107 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829619005 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21424 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6060149 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5145730 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 991238350 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800229618 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1106821161 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 116 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963974807 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27263541 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 455448 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 461036 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29565034 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16718678 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9823839 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1099301 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 921701 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 824848453 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1187045 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820941370 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 145995 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19149103 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29112205 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 132366 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 262951613 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.122024 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.401319 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 76255592 29.04% 29.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15761044 6.00% 35.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10531368 4.01% 39.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7369443 2.81% 41.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75730840 28.84% 70.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3739599 1.42% 72.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72299562 27.53% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 768121 0.29% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 145948 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 76573555 29.12% 29.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15783174 6.00% 35.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10543493 4.01% 39.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7363188 2.80% 41.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75733020 28.80% 70.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3745069 1.42% 72.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72294186 27.49% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 768319 0.29% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 147609 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 262601517 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 262951613 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 345012 32.94% 32.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 241 0.02% 32.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 974 0.09% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547730 52.30% 85.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153356 14.64% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 346888 33.04% 33.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 241 0.02% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 2034 0.19% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547279 52.12% 85.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 153573 14.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 307746 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793434579 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149572 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124688 0.02% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17663300 2.15% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9215382 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 309747 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793469361 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149710 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124599 0.02% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17668051 2.15% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9219902 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 820895267 # Type of FU issued -system.cpu.iq.rate 1.809457 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1047313 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001276 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905699959 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845163637 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 816985295 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 199 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821634741 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1691465 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 820941370 # Type of FU issued +system.cpu.iq.rate 1.808871 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1050015 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001279 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1906138377 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845194990 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817033315 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 197 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821681548 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1692176 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2728859 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17017 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11975 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1400009 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2727781 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18489 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12047 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1402321 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1931860 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12243 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931655 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11924 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3050556 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 31208951 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2150350 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 825997521 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 243405 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16714812 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9817459 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 689575 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1619766 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13837 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11975 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 493977 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 506066 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1000043 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819488058 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17361171 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1407208 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3055059 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 31495600 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2151607 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826035498 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 247681 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16718678 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9823839 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 691406 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1620111 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12282 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12047 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 498908 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 509123 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1008031 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819536653 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17366589 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1404716 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26390625 # number of memory reference insts executed -system.cpu.iew.exec_branches 83079645 # Number of branches executed -system.cpu.iew.exec_stores 9029454 # Number of stores executed -system.cpu.iew.exec_rate 1.806355 # Inst execution rate -system.cpu.iew.wb_sent 819086222 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 816985349 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638544896 # num instructions producing a value -system.cpu.iew.wb_consumers 1043866074 # num instructions consuming a value +system.cpu.iew.exec_refs 26403509 # number of memory reference insts executed +system.cpu.iew.exec_branches 83090404 # Number of branches executed +system.cpu.iew.exec_stores 9036920 # Number of stores executed +system.cpu.iew.exec_rate 1.805776 # Inst execution rate +system.cpu.iew.wb_sent 819134916 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817033367 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638560375 # num instructions producing a value +system.cpu.iew.wb_consumers 1043850178 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.800838 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611712 # average fanout of values written-back +system.cpu.iew.wb_rate 1.800260 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611736 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19867682 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054616 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 887449 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259550960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.105446 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863698 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19875138 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054679 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 892733 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259896554 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.101438 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863911 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 88027122 33.92% 33.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11847553 4.56% 38.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3827434 1.47% 39.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74752127 28.80% 68.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2379438 0.92% 69.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1475953 0.57% 70.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 857436 0.33% 70.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70850710 27.30% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5533187 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 88349043 33.99% 33.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11862829 4.56% 38.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3832305 1.47% 40.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74754047 28.76% 68.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2383630 0.92% 69.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1474941 0.57% 70.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 857586 0.33% 70.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70848784 27.26% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5533389 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259550960 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407752265 # Number of instructions committed -system.cpu.commit.committedOps 806021401 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 259896554 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407772261 # Number of instructions committed +system.cpu.commit.committedOps 806052921 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22403400 # Number of memory references committed -system.cpu.commit.loads 13985950 # Number of loads committed -system.cpu.commit.membars 474657 # Number of memory barriers committed -system.cpu.commit.branches 82156128 # Number of branches committed +system.cpu.commit.refs 22412414 # Number of memory references committed +system.cpu.commit.loads 13990896 # Number of loads committed +system.cpu.commit.membars 474709 # Number of memory barriers committed +system.cpu.commit.branches 82160310 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734862948 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155170 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5533187 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 734896243 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155289 # Number of function calls committed. +system.cpu.commit.bw_lim_events 5533389 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1079828496 # The number of ROB reads -system.cpu.rob.rob_writes 1654843441 # The number of ROB writes -system.cpu.timesIdled 1258915 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 191067947 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9845938983 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407752265 # Number of Instructions Simulated -system.cpu.committedOps 806021401 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407752265 # Number of Instructions Simulated -system.cpu.cpi 1.112611 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.112611 # CPI: Total CPI of All Threads -system.cpu.ipc 0.898787 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.898787 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1088694796 # number of integer regfile reads -system.cpu.int_regfile_writes 653771353 # number of integer regfile writes -system.cpu.fp_regfile_reads 54 # number of floating regfile reads -system.cpu.cc_regfile_reads 415601025 # number of cc regfile reads -system.cpu.cc_regfile_writes 321483560 # number of cc regfile writes -system.cpu.misc_regfile_reads 264032145 # number of misc regfile reads -system.cpu.misc_regfile_writes 402444 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53392020 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3013693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3013151 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1577044 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2235 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2235 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 334035 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1908198 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121437 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18680 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 151603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8199918 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61058944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207524391 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 566848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5217216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 274367399 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 274343271 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 615040 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4030545417 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1080212949 # The number of ROB reads +system.cpu.rob.rob_writes 1654925831 # The number of ROB writes +system.cpu.timesIdled 1261862 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190890238 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9814027971 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407772261 # Number of Instructions Simulated +system.cpu.committedOps 806052921 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407772261 # Number of Instructions Simulated +system.cpu.cpi 1.112979 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.112979 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898490 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898490 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1088746320 # number of integer regfile reads +system.cpu.int_regfile_writes 653799671 # number of integer regfile writes +system.cpu.fp_regfile_reads 52 # number of floating regfile reads +system.cpu.cc_regfile_reads 415603862 # number of cc regfile reads +system.cpu.cc_regfile_writes 321491324 # number of cc regfile writes +system.cpu.misc_regfile_reads 264059604 # number of misc regfile reads +system.cpu.misc_regfile_writes 402440 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53738291 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3018879 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3018337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13778 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13778 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1585586 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2261 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2261 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 334835 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 288140 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919324 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6124632 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18318 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159709 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8221983 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61414400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207642981 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 603136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5731328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 275391845 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 275366117 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 522624 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4046374411 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 565500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 603000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1435258580 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1442983054 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3141587747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3140518579 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 14741736 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 13344744 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 105191645 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 105297384 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 953576 # number of replacements -system.cpu.icache.tags.tagsinuse 510.036469 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7463561 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 954088 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.822718 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147479259250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.036469 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996165 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996165 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7463561 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7463561 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7463561 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7463561 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7463561 # number of overall hits -system.cpu.icache.overall_hits::total 7463561 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1006237 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1006237 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1006237 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1006237 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1006237 # number of overall misses -system.cpu.icache.overall_misses::total 1006237 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14239259264 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14239259264 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14239259264 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14239259264 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14239259264 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14239259264 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8469798 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8469798 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8469798 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8469798 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8469798 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8469798 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118803 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.118803 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.118803 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.118803 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.118803 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.118803 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14150.999480 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14150.999480 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14150.999480 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14150.999480 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14150.999480 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14150.999480 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7035 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 587 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 207 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 33.985507 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 587 # average number of cycles each access was blocked +system.cpu.icache.tags.replacements 959142 # number of replacements +system.cpu.icache.tags.tagsinuse 509.299647 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7468451 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 959654 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.782441 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147611306250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.299647 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994726 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994726 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7468451 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7468451 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7468451 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7468451 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7468451 # number of overall hits +system.cpu.icache.overall_hits::total 7468451 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1013022 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1013022 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1013022 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1013022 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1013022 # number of overall misses +system.cpu.icache.overall_misses::total 1013022 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14172498740 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14172498740 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14172498740 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14172498740 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14172498740 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14172498740 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8481473 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8481473 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8481473 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8481473 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8481473 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8481473 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119439 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.119439 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.119439 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.119439 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.119439 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.119439 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13990.316834 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13990.316834 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13990.316834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13990.316834 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 172 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 26.023256 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52085 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 52085 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 52085 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 52085 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 52085 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 52085 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 954152 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 954152 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 954152 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 954152 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 954152 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 954152 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11748055164 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11748055164 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11748055164 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11748055164 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11748055164 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11748055164 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112653 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112653 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112653 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.112653 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112653 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.112653 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12312.561483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12312.561483 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12312.561483 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12312.561483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12312.561483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12312.561483 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53298 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53298 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53298 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53298 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53298 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53298 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 959724 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 959724 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 959724 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 959724 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 959724 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 959724 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11694537694 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11694537694 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11694537694 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11694537694 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11694537694 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11694537694 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113155 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.113155 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.113155 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12185.313376 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12185.313376 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12185.313376 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12185.313376 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12185.313376 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12185.313376 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 8937 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.031585 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 20273 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 8949 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.265393 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5104907998500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.031585 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376974 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.376974 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20288 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 20288 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 8004 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.959011 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 21893 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 8020 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.729800 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5103903665500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.959011 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.434938 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.434938 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21891 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 21891 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20290 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 20290 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20290 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 20290 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9823 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 9823 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9823 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 9823 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9823 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 9823 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 106143491 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 106143491 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 106143491 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 106143491 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 106143491 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 106143491 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30111 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 30111 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21893 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 21893 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21893 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 21893 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8894 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 8894 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8894 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 8894 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8894 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 8894 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 101842497 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 101842497 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 101842497 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 101842497 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 101842497 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 101842497 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30785 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 30785 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30113 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 30113 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30113 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 30113 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.326226 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.326226 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.326205 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.326205 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.326205 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.326205 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10805.608368 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10805.608368 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10805.608368 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10805.608368 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10805.608368 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10805.608368 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30787 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 30787 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30787 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 30787 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.288907 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.288907 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.288888 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.288888 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.288888 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.288888 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11450.696762 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11450.696762 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11450.696762 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11450.696762 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1095,78 +1120,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1536 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1536 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9823 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9823 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9823 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 9823 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9823 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 9823 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 86483019 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 86483019 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 86483019 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 86483019 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 86483019 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 86483019 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.326226 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.326226 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.326205 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.326205 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.326205 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.326205 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8804.135091 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8804.135091 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8804.135091 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8804.135091 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8804.135091 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8804.135091 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 2197 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 2197 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8894 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8894 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 8894 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8894 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 8894 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 84047009 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 84047009 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 84047009 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 84047009 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 84047009 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 84047009 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.288907 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.288907 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.288888 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.288888 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9449.854846 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.tags.replacements 69051 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 14.904441 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 92410 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.tagsinuse 14.134079 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 90874 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.tags.sampled_refs 69067 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.337976 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 4994136871250 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.904441 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.931528 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.931528 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92410 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 92410 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92410 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 92410 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92410 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 92410 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 70084 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 70084 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 70084 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 70084 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 70084 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 70084 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 863900211 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 863900211 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 863900211 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 863900211 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 863900211 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 863900211 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 162494 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 162494 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 162494 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 162494 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 162494 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 162494 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.431302 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.431302 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.431302 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.431302 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.431302 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.431302 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12326.639618 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12326.639618 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12326.639618 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12326.639618 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12326.639618 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12326.639618 # average overall miss latency +system.cpu.dtb_walker_cache.tags.avg_refs 1.315737 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 4994243678000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.134079 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.883380 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.883380 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90874 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 90874 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90874 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 90874 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90874 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 90874 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 70157 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 70157 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 70157 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 70157 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 70157 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 70157 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 871654701 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 871654701 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 871654701 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 871654701 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 871654701 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 871654701 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161031 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 161031 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161031 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 161031 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161031 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 161031 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.435674 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.435674 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.435674 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.435674 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.435674 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.435674 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.343986 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.343986 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.343986 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.343986 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1175,146 +1200,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 17433 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 17433 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 70084 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 70084 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 70084 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 70084 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 70084 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 70084 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 723600921 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 723600921 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 723600921 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 723600921 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 723600921 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 723600921 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.431302 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.431302 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.431302 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.431302 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.431302 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.431302 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10324.766295 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10324.766295 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10324.766295 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 24645 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 24645 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 70157 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 70157 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 70157 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 70157 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 70157 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 70157 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 731216933 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 731216933 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 731216933 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 731216933 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 731216933 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 731216933 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.435674 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.435674 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.435674 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10422.579828 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1656223 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.995363 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18981681 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1656735 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.457283 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 38296250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.995363 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10886449 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10886449 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8092566 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8092566 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 18979015 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18979015 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18979015 # number of overall hits -system.cpu.dcache.overall_hits::total 18979015 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2233485 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2233485 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315362 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315362 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2548847 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2548847 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2548847 # number of overall misses -system.cpu.dcache.overall_misses::total 2548847 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33146878091 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33146878091 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12110851955 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12110851955 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45257730046 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45257730046 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45257730046 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45257730046 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13119934 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13119934 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8407928 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8407928 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21527862 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21527862 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21527862 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21527862 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170236 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170236 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037508 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037508 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118398 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118398 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118398 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118398 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14840.877862 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14840.877862 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38403.016074 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38403.016074 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17756.157998 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17756.157998 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17756.157998 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17756.157998 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 397029 # number of cycles access was blocked +system.cpu.dcache.tags.replacements 1657437 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.988912 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18989388 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1657949 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.453542 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 39724250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.988912 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999978 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999978 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10890920 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10890920 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8095777 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8095777 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 18986697 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18986697 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18986697 # number of overall hits +system.cpu.dcache.overall_hits::total 18986697 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2234479 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2234479 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316198 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316198 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2550677 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2550677 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2550677 # number of overall misses +system.cpu.dcache.overall_misses::total 2550677 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33004921637 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33004921637 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12257889032 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12257889032 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45262810669 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45262810669 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45262810669 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45262810669 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13125399 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13125399 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8411975 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8411975 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21537374 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21537374 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21537374 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21537374 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170241 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.170241 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037589 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037589 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118430 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118430 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118430 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118430 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14770.745949 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14770.745949 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38766.497676 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38766.497676 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17745.410598 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17745.410598 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17745.410598 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17745.410598 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 397669 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42211 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42042 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.405818 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.458851 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1558075 # number of writebacks -system.cpu.dcache.writebacks::total 1558075 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 863964 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 863964 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25903 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25903 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 889867 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 889867 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 889867 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 889867 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369521 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1369521 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289459 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289459 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1658980 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1658980 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1658980 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1658980 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17890697467 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17890697467 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11213904776 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11213904776 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29104602243 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29104602243 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29104602243 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29104602243 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97363389500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97363389500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537212500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537212500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99900602000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99900602000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104385 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104385 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034427 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034427 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077062 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077062 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077062 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13063.470708 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13063.470708 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38740.908992 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38740.908992 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17543.672765 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17543.672765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17543.672765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17543.672765 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1558744 # number of writebacks +system.cpu.dcache.writebacks::total 1558744 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864490 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 864490 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25919 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 25919 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 890409 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 890409 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 890409 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 890409 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369989 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1369989 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290279 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 290279 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1660268 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1660268 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1660268 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1660268 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17836083706 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17836083706 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11362753211 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11362753211 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29198836917 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29198836917 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29198836917 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29198836917 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364613500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364613500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538583500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538583500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903197000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903197000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034508 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034508 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.077088 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077088 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13019.143735 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13019.143735 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39144.248158 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39144.248158 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17586.821475 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17586.821475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17586.821475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17586.821475 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1322,141 +1347,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111030 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64826.472459 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3778684 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.568570 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 111632 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64821.705622 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3786761 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175570 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.568383 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50681.739726 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.389473 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.126360 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3154.839076 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10976.377823 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.773342 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000204 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50709.515998 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 7.756367 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.126012 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3028.517183 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11075.790063 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.773766 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000118 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048139 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.167486 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989173 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64025 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7316 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 937955 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1333061 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2342357 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1577044 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1577044 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 316 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 316 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 154757 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 154757 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 64025 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 7316 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 937955 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1487818 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2497114 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 64025 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 7316 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 937955 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1487818 # number of overall hits -system.cpu.l2cache.overall_hits::total 2497114 # number of overall hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046212 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.169003 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989101 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64846 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7222 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 943511 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1333169 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2348748 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1585586 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1585586 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 314 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 314 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 155047 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 155047 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 64846 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 7222 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 943511 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1488216 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2503795 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 64846 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 7222 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 943511 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1488216 # number of overall hits +system.cpu.l2cache.overall_hits::total 2503795 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16091 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 35754 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 51911 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1443 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1443 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 132547 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 132547 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 16089 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 36006 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 52161 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1462 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1462 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133062 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133062 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16091 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 168301 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 184458 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 16089 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 169068 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 185223 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16091 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 168301 # number of overall misses -system.cpu.l2cache.overall_misses::total 184458 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5633750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 417750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1393223986 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2996305709 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4395581195 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16716837 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 16716837 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9332768700 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9332768700 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5633750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 417750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1393223986 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12329074409 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13728349895 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5633750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 417750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1393223986 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12329074409 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13728349895 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64086 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7321 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 954046 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1368815 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2394268 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1577044 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1577044 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1759 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1759 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 287304 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 287304 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64086 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 7321 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 954046 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1656119 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2681572 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64086 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 7321 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 954046 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1656119 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2681572 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000952 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000683 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016866 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026120 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021681 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.820352 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.820352 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461348 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.461348 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000952 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000683 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016866 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.101624 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.068787 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000952 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000683 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016866 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.101624 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.068787 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 92356.557377 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83550 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86584.052327 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83803.370504 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 84675.332685 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11584.779626 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11584.779626 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70411.014206 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70411.014206 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92356.557377 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83550 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86584.052327 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73256.097165 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74425.342869 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92356.557377 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86584.052327 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73256.097165 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74425.342869 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 16089 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 169068 # number of overall misses +system.cpu.l2cache.overall_misses::total 185223 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5260500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1277797734 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2940044940 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 4223492924 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17900790 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 17900790 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9477459899 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9477459899 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5260500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1277797734 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12417504839 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13700952823 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5260500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1277797734 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12417504839 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13700952823 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64907 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7227 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 959600 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1369175 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2400909 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1585586 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1585586 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1776 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1776 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 288109 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 288109 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64907 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 7227 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 959600 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1657284 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2689018 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64907 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 7227 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 959600 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1657284 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2689018 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000940 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000692 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016766 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026298 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021726 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823198 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823198 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461846 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.461846 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000940 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000692 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016766 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102015 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.068881 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000940 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000692 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016766 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102015 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.068881 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86237.704918 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77950 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79420.581391 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81654.305949 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80970.321198 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12244.042408 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12244.042408 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71225.893937 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71225.893937 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86237.704918 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77950 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79420.581391 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73446.807433 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73970.040562 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86237.704918 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77950 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79420.581391 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73446.807433 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73970.040562 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1465,99 +1490,99 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101658 # number of writebacks -system.cpu.l2cache.writebacks::total 101658 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101920 # number of writebacks +system.cpu.l2cache.writebacks::total 101920 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16089 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35751 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 51906 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1443 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1443 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132547 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 132547 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16087 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36005 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 52158 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1462 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1462 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133062 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133062 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16089 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 168298 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 184453 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16087 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 169067 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 185220 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16089 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 168298 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 184453 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4857750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 353750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1189838014 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2545516291 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3740565805 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15357924 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15357924 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7668131300 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7668131300 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4857750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 353750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1189838014 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10213647591 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11408697105 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4857750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 353750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1189838014 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10213647591 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11408697105 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89250267000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89250267000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2371416000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2371416000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91621683000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91621683000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000952 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000683 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016864 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026118 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021679 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.820352 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.820352 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000952 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000683 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016864 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101622 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.068785 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000952 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000683 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016864 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101622 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.068785 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79635.245902 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73953.509479 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71201.261251 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72064.227739 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10643.051975 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10643.051975 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57852.167910 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57852.167910 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79635.245902 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73953.509479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60687.872649 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61851.512879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79635.245902 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73953.509479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60687.872649 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61851.512879 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16087 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169067 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 185220 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4502000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 326250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075523016 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2491735810 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3572087076 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15586943 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15586943 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7807116101 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7807116101 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4502000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 326250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075523016 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10298851911 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11379203177 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4502000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 326250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075523016 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10298851911 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11379203177 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251387000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251387000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2372677500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2372677500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624064500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624064500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026297 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021724 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823198 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823198 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461846 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461846 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102015 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068880 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102015 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068880 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66856.655436 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69205.271768 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68485.890487 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.383721 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.383721 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58672.769844 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58672.769844 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index e0fd581aa..d95103a1f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,365 +1,323 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.304492 # Number of seconds simulated -sim_ticks 5304492233500 # Number of ticks simulated -final_tick 5304492233500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.303604 # Number of seconds simulated +sim_ticks 5303604289000 # Number of ticks simulated +final_tick 5303604289000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 155930 # Simulator instruction rate (inst/s) -host_op_rate 299191 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7641192165 # Simulator tick rate (ticks/s) -host_mem_usage 831032 # Number of bytes of host memory used -host_seconds 694.20 # Real time elapsed on the host -sim_insts 108246430 # Number of instructions simulated -sim_ops 207697456 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 35104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 136600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 67168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 857797264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 68434149 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 89360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 41152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 170486264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 28476493 # Number of bytes read from this memory -system.physmem.bytes_read::total 1125563554 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 857797264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 170486264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1028283528 # Number of instructions bytes read from this memory +host_inst_rate 170166 # Simulator instruction rate (inst/s) +host_op_rate 326512 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8335943745 # Simulator tick rate (ticks/s) +host_mem_usage 875260 # Number of bytes of host memory used +host_seconds 636.23 # Real time elapsed on the host +sim_insts 108265301 # Number of instructions simulated +sim_ops 207738037 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 35128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 87544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 33280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 839536560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 65163112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 137640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 74624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 188924512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 31786983 # Number of bytes read from this memory +system.physmem.bytes_read::total 1125779383 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 839536560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 188924512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1028461072 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 47724441 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 22209848 # Number of bytes written to this memory -system.physmem.bytes_written::total 72925409 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 17075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 8396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 107224658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 11945854 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 5144 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 21310783 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 4242510 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144766394 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu0.data 45585342 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 24372608 # Number of bytes written to this memory +system.physmem.bytes_written::total 72949070 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 807 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 10943 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4160 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 104942070 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 11447211 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 17205 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 9328 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 23615564 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 4748353 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144795641 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 7033055 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 3067077 # Number of write requests responded to by this memory -system.physmem.num_writes::total 10146870 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 6618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 25752 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 12662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 161711475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12901169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 16846 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 7758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 32139978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5368373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 212190631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 161711475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 32139978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 193851453 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 563881 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu0.data 6738169 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 3365460 # Number of write requests responded to by this memory +system.physmem.num_writes::total 10150367 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 6623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 16507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 6275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 158295475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12286571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 25952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 14070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35621909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5993468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 212266851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 158295475 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35621909 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 193917384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 563976 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 8996986 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 4186989 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13747859 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 570499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 25752 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 12665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 161711475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 21898154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 16846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 7758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 32139978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 9555362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 225938490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 804 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 46736 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 804 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 46736 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 51456 # Total number of bytes read from memory -system.physmem.bytesWritten 2991104 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 35104 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 324 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 128 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 3280 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 3344 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2800 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 3056 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2576 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2704 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2608 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 2960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2816 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3072 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2720 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2944 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2848 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 3008 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 3136 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry -system.physmem.totGap 163206922999 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 292 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 512 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 46736 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 537 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5562.279330 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 3318.964815 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 3321.501933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 31 5.77% 5.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 6 1.12% 6.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4 0.74% 7.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 7 1.30% 8.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 7 1.30% 10.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 2 0.37% 10.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1 0.19% 10.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 2 0.37% 11.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 1 0.19% 11.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 1 0.19% 11.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2 0.37% 11.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1 0.19% 12.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 3 0.56% 12.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1 0.19% 12.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1 0.19% 13.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 62 11.55% 24.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1 0.19% 24.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 1 0.19% 24.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.56% 25.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 2 0.37% 25.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.19% 26.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 16 2.98% 29.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.19% 29.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.19% 29.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 5 0.93% 30.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.19% 30.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.19% 30.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.19% 30.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 1 0.19% 31.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.19% 31.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.19% 31.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 35 6.52% 37.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.19% 38.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 1 0.19% 38.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.19% 38.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 8 1.49% 40.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 1 0.19% 40.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 3 0.56% 40.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.19% 40.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 6 1.12% 42.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.19% 42.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 310 57.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 537 # Bytes accessed per row activation -system.physmem.totQLat 42021352 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 52311352 # Sum of mem lat for all requests -system.physmem.totBusLat 4020000 # Total cycles spent in databus access -system.physmem.totBankLat 6270000 # Total cycles spent in bank access -system.physmem.avgQLat 52265.36 # Average queueing delay per request -system.physmem.avgBankLat 7798.51 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 65063.87 # Average memory access latency -system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.56 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.56 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bw_write::cpu0.data 8595163 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 4595480 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13754622 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 570599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 16507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 6278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 158295475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 20881734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 25952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 14070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 35621909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 10588948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 226021473 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 0 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 0 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 0 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 0 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 0 # Per bank write bursts +system.physmem.perBankRdBursts::1 0 # Per bank write bursts +system.physmem.perBankRdBursts::2 0 # Per bank write bursts +system.physmem.perBankRdBursts::3 0 # Per bank write bursts +system.physmem.perBankRdBursts::4 0 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 0 # Per bank write bursts +system.physmem.perBankRdBursts::7 0 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 0 # Per bank write bursts +system.physmem.perBankRdBursts::10 0 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 0 # Per bank write bursts +system.physmem.perBankRdBursts::13 0 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 0 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 0 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation +system.physmem.totQLat 0 # Total ticks spent queuing +system.physmem.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 0 # Total ticks spent in databus transfers +system.physmem.totBankLat 0 # Total ticks spent accessing banks +system.physmem.avgQLat nan # Average queueing delay per DRAM burst +system.physmem.avgBankLat nan # Average bank access latency per DRAM burst +system.physmem.avgBusLat nan # Average bus latency per DRAM burst +system.physmem.avgMemAccLat nan # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.00 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.00 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 735 # Number of row buffer hits during reads -system.physmem.writeRowHits 46268 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 99.00 # Row buffer hit rate for writes -system.physmem.avgGap 3433044.24 # Average gap between requests -system.piobus.throughput 959190 # Throughput (bytes/s) -system.piobus.trans_dist::ReadReq 865004 # Transaction distribution -system.piobus.trans_dist::ReadResp 865004 # Transaction distribution -system.piobus.trans_dist::WriteReq 86867 # Transaction distribution -system.piobus.trans_dist::WriteResp 86867 # Transaction distribution -system.piobus.trans_dist::MessageReq 2698 # Transaction distribution -system.piobus.trans_dist::MessageResp 2698 # Transaction distribution -system.piobus.pkt_count_system.pc.south_bridge.ide.dma::system.physmem.port 95080 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.pc.south_bridge.ide.dma::total 95080 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 1704 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 1648 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3352 # Packet count per connected master and slave (bytes) +system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 0 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate nan # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap nan # Average gap between requests +system.physmem.pageHitRate nan # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.00 # Percentage of time for which DRAM has all the banks in precharge state +system.piobus.throughput 388759 # Throughput (bytes/s) +system.piobus.trans_dist::ReadReq 864194 # Transaction distribution +system.piobus.trans_dist::ReadResp 864194 # Transaction distribution +system.piobus.trans_dist::WriteReq 40126 # Transaction distribution +system.piobus.trans_dist::WriteResp 40126 # Transaction distribution +system.piobus.trans_dist::MessageReq 2700 # Transaction distribution +system.piobus.trans_dist::MessageResp 2700 # Transaction distribution +system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 1702 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 1644 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3346 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 52 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 7290 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 5756 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 988 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 82 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 46 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 1028 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 1014 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 178 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 20480 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 20120 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 751796 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 751828 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::total 1723300 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 3752 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::total 1721420 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 5240 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 376 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 8 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 33180 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 344 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 340 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 33180 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 6188 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 8322 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::total 85362 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 1020 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.cpu0.interrupts.int_master::total 1020 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 1024 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.cpu1.interrupts.int_master::total 1024 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::total 1909138 # Packet count per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.physmem.port 3026208 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3026208 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 3408 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 3296 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6704 # Cumulative packet size per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 6556 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 8324 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::total 87220 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 1032 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu0.interrupts.int_master::total 1032 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 1022 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu1.interrupts.int_master::total 1022 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::total 1814040 # Packet count per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 3404 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 3288 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6692 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 26 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 4565 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 3669 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 494 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 41 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 23 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 2056 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 2028 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 89 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 10240 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 10060 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 1503586 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 1503650 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::total 1995120 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 2095 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::total 1994078 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 2965 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 188 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 4 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 16590 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 688 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 680 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 16590 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 3094 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 16641 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::total 55896 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 2040 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::total 2040 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 2048 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::total 2048 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::total 5088016 # Cumulative packet size per connected master and slave (bytes) -system.piobus.data_through_bus 5088016 # Total data (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 3278 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 16645 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::total 56948 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 2064 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::total 2064 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 2044 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::total 2044 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::total 2061826 # Cumulative packet size per connected master and slave (bytes) +system.piobus.data_through_bus 2061826 # Total data (bytes) system.piobus.reqLayer0.occupancy 51000 # Layer occupancy (ticks) system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) system.piobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer2.occupancy 10166500 # Layer occupancy (ticks) +system.piobus.reqLayer2.occupancy 10114500 # Layer occupancy (ticks) system.piobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer3.occupancy 152000 # Layer occupancy (ticks) system.piobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer4.occupancy 1062500 # Layer occupancy (ticks) +system.piobus.reqLayer4.occupancy 1060500 # Layer occupancy (ticks) system.piobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer5.occupancy 98500 # Layer occupancy (ticks) system.piobus.reqLayer5.utilization 0.0 # Layer utilization (%) @@ -369,13 +327,13 @@ system.piobus.reqLayer7.occupancy 22149500 # La system.piobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer8.occupancy 586857000 # Layer occupancy (ticks) system.piobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer9.occupancy 1330000 # Layer occupancy (ticks) +system.piobus.reqLayer9.occupancy 1313000 # Layer occupancy (ticks) system.piobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer10.occupancy 41670000 # Layer occupancy (ticks) system.piobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks) system.piobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer12.occupancy 23281000 # Layer occupancy (ticks) +system.piobus.reqLayer12.occupancy 23288000 # Layer occupancy (ticks) system.piobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.piobus.reqLayer13.utilization 0.0 # Layer utilization (%) @@ -385,36 +343,32 @@ system.piobus.reqLayer15.occupancy 10500 # La system.piobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) system.piobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer17.occupancy 473785500 # Layer occupancy (ticks) +system.piobus.reqLayer17.occupancy 473822500 # Layer occupancy (ticks) system.piobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer18.occupancy 3210816 # Layer occupancy (ticks) +system.piobus.reqLayer18.occupancy 3230956 # Layer occupancy (ticks) system.piobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer19.occupancy 8819500 # Layer occupancy (ticks) +system.piobus.reqLayer19.occupancy 8830000 # Layer occupancy (ticks) system.piobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer20.occupancy 3135584 # Layer occupancy (ticks) +system.piobus.reqLayer20.occupancy 3180944 # Layer occupancy (ticks) system.piobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer21.occupancy 421722676 # Layer occupancy (ticks) -system.piobus.reqLayer21.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer22.occupancy 1069500 # Layer occupancy (ticks) system.piobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer0.occupancy 52207182 # Layer occupancy (ticks) +system.piobus.respLayer0.occupancy 2420900 # Layer occupancy (ticks) system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer1.occupancy 2368900 # Layer occupancy (ticks) +system.piobus.respLayer1.occupancy 1925709500 # Layer occupancy (ticks) system.piobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer2.occupancy 1927202500 # Layer occupancy (ticks) +system.piobus.respLayer2.occupancy 68943500 # Layer occupancy (ticks) system.piobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer3.occupancy 67468000 # Layer occupancy (ticks) +system.piobus.respLayer3.occupancy 649000 # Layer occupancy (ticks) system.piobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer4.occupancy 641000 # Layer occupancy (ticks) +system.piobus.respLayer4.occupancy 642000 # Layer occupancy (ticks) system.piobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer5.occupancy 638500 # Layer occupancy (ticks) -system.piobus.respLayer5.utilization 0.0 # Layer utilization (%) -system.ruby.l1_cntrl0.L1Dcache.demand_hits 17400971 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 1603411 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 19004382 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 106716418 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 508240 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 107224658 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 16641315 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 1559170 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 18200485 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 104473354 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 468716 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 104942070 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -424,12 +378,12 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl1.L1Dcache.demand_hits 7028238 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 297663 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 7325901 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 21021438 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 289345 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 21310783 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 7796271 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 344075 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 8140346 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 23285981 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 329583 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 23615564 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -439,514 +393,580 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l2_cntrl0.L2cache.demand_hits 2449214 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 249445 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2698659 # Number of cache demand accesses -system.ruby.network.routers0.percent_links_utilized 0.088789 -system.ruby.network.routers0.msg_count.Control::0 2111651 -system.ruby.network.routers0.msg_count.Request_Control::0 68326 -system.ruby.network.routers0.msg_count.Response_Data::1 2154834 -system.ruby.network.routers0.msg_count.Response_Control::1 1565369 -system.ruby.network.routers0.msg_count.Response_Control::2 1557069 -system.ruby.network.routers0.msg_count.Writeback_Data::0 1435847 -system.ruby.network.routers0.msg_count.Writeback_Data::1 52 -system.ruby.network.routers0.msg_count.Writeback_Control::0 59460 -system.ruby.network.routers0.msg_bytes.Control::0 16893208 -system.ruby.network.routers0.msg_bytes.Request_Control::0 546608 -system.ruby.network.routers0.msg_bytes.Response_Data::1 155148048 -system.ruby.network.routers0.msg_bytes.Response_Control::1 12522952 -system.ruby.network.routers0.msg_bytes.Response_Control::2 12456552 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 103380984 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 3744 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 475680 -system.ruby.network.routers1.percent_links_utilized 0.020109 -system.ruby.network.routers1.msg_count.Control::0 587008 -system.ruby.network.routers1.msg_count.Request_Control::0 61976 -system.ruby.network.routers1.msg_count.Response_Data::1 624789 -system.ruby.network.routers1.msg_count.Response_Control::1 278706 -system.ruby.network.routers1.msg_count.Response_Control::2 271876 -system.ruby.network.routers1.msg_count.Writeback_Data::0 187266 -system.ruby.network.routers1.msg_count.Writeback_Data::1 273 -system.ruby.network.routers1.msg_count.Writeback_Control::0 22758 -system.ruby.network.routers1.msg_bytes.Control::0 4696064 -system.ruby.network.routers1.msg_bytes.Request_Control::0 495808 -system.ruby.network.routers1.msg_bytes.Response_Data::1 44984808 -system.ruby.network.routers1.msg_bytes.Response_Control::1 2229648 -system.ruby.network.routers1.msg_bytes.Response_Control::2 2175008 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 13483152 -system.ruby.network.routers1.msg_bytes.Writeback_Data::1 19656 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 182064 -system.ruby.network.routers2.percent_links_utilized 0.111786 -system.ruby.network.routers2.msg_count.Control::0 2871394 -system.ruby.network.routers2.msg_count.Request_Control::0 128339 -system.ruby.network.routers2.msg_count.Response_Data::1 2893297 -system.ruby.network.routers2.msg_count.Response_Control::1 1875820 -system.ruby.network.routers2.msg_count.Response_Control::2 1828945 -system.ruby.network.routers2.msg_count.Writeback_Data::0 1623113 -system.ruby.network.routers2.msg_count.Writeback_Data::1 325 -system.ruby.network.routers2.msg_count.Writeback_Control::0 82218 -system.ruby.network.routers2.msg_bytes.Control::0 22971152 -system.ruby.network.routers2.msg_bytes.Request_Control::0 1026712 -system.ruby.network.routers2.msg_bytes.Response_Data::1 208317384 -system.ruby.network.routers2.msg_bytes.Response_Control::1 15006560 -system.ruby.network.routers2.msg_bytes.Response_Control::2 14631560 -system.ruby.network.routers2.msg_bytes.Writeback_Data::0 116864136 -system.ruby.network.routers2.msg_bytes.Writeback_Data::1 23400 -system.ruby.network.routers2.msg_bytes.Writeback_Control::0 657744 -system.ruby.dir_cntrl0.memBuffer.memReq 267094 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 172735 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 94359 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 684452 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 920715 # Delay stalled at the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.memInputQ 18 # Delay in the input queue -system.ruby.dir_cntrl0.memBuffer.memBankQ 5950 # Delay behind the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 926683 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 3.469501 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 909950 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 7902 # memory stalls due to busy bus -system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 10 # memory stalls due to read write turnaround +system.ruby.l2_cntrl0.L2cache.demand_hits 2450353 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 251191 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2701544 # Number of cache demand accesses +system.ruby.network.routers0.percent_links_utilized 0.085942 +system.ruby.network.routers0.msg_count.Control::0 2027886 +system.ruby.network.routers0.msg_count.Request_Control::0 68787 +system.ruby.network.routers0.msg_count.Response_Data::1 2071049 +system.ruby.network.routers0.msg_count.Response_Control::1 1525279 +system.ruby.network.routers0.msg_count.Response_Control::2 1517023 +system.ruby.network.routers0.msg_count.Writeback_Data::0 1403655 +system.ruby.network.routers0.msg_count.Writeback_Data::1 171 +system.ruby.network.routers0.msg_count.Writeback_Control::0 51157 +system.ruby.network.routers0.msg_bytes.Control::0 16223088 +system.ruby.network.routers0.msg_bytes.Request_Control::0 550296 +system.ruby.network.routers0.msg_bytes.Response_Data::1 149115528 +system.ruby.network.routers0.msg_bytes.Response_Control::1 12202232 +system.ruby.network.routers0.msg_bytes.Response_Control::2 12136184 +system.ruby.network.routers0.msg_bytes.Writeback_Data::0 101063160 +system.ruby.network.routers0.msg_bytes.Writeback_Data::1 12312 +system.ruby.network.routers0.msg_bytes.Writeback_Control::0 409256 +system.ruby.network.routers1.percent_links_utilized 0.023064 +system.ruby.network.routers1.msg_count.Control::0 673658 +system.ruby.network.routers1.msg_count.Request_Control::0 62763 +system.ruby.network.routers1.msg_count.Response_Data::1 711847 +system.ruby.network.routers1.msg_count.Response_Control::1 320652 +system.ruby.network.routers1.msg_count.Response_Control::2 313476 +system.ruby.network.routers1.msg_count.Writeback_Data::0 219226 +system.ruby.network.routers1.msg_count.Writeback_Data::1 383 +system.ruby.network.routers1.msg_count.Writeback_Control::0 32004 +system.ruby.network.routers1.msg_bytes.Control::0 5389264 +system.ruby.network.routers1.msg_bytes.Request_Control::0 502104 +system.ruby.network.routers1.msg_bytes.Response_Data::1 51252984 +system.ruby.network.routers1.msg_bytes.Response_Control::1 2565216 +system.ruby.network.routers1.msg_bytes.Response_Control::2 2507808 +system.ruby.network.routers1.msg_bytes.Writeback_Data::0 15784272 +system.ruby.network.routers1.msg_bytes.Writeback_Data::1 27576 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 256032 +system.ruby.network.routers2.percent_links_utilized 0.111968 +system.ruby.network.routers2.msg_count.Control::0 2875657 +system.ruby.network.routers2.msg_count.Request_Control::0 129481 +system.ruby.network.routers2.msg_count.Response_Data::1 2899412 +system.ruby.network.routers2.msg_count.Response_Control::1 1882104 +system.ruby.network.routers2.msg_count.Response_Control::2 1830499 +system.ruby.network.routers2.msg_count.Writeback_Data::0 1622881 +system.ruby.network.routers2.msg_count.Writeback_Data::1 554 +system.ruby.network.routers2.msg_count.Writeback_Control::0 83161 +system.ruby.network.routers2.msg_bytes.Control::0 23005256 +system.ruby.network.routers2.msg_bytes.Request_Control::0 1035848 +system.ruby.network.routers2.msg_bytes.Response_Data::1 208757664 +system.ruby.network.routers2.msg_bytes.Response_Control::1 15056832 +system.ruby.network.routers2.msg_bytes.Response_Control::2 14643992 +system.ruby.network.routers2.msg_bytes.Writeback_Data::0 116847432 +system.ruby.network.routers2.msg_bytes.Writeback_Data::1 39888 +system.ruby.network.routers2.msg_bytes.Writeback_Control::0 665288 +system.ruby.dir_cntrl0.memBuffer.memReq 315825 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 174561 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 141264 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 718428 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 922537 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 46 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 6012 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 928595 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 2.940220 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 911376 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 8161 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 74 # memory stalls due to read write turnaround system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 8 # memory stalls due to read read turnaround -system.ruby.dir_cntrl0.memBuffer.memArbWait 2845 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memBankCount | 8698 3.26% 3.26% | 8135 3.05% 6.30% | 8180 3.06% 9.36% | 8226 3.08% 12.44% | 8503 3.18% 15.63% | 8270 3.10% 18.72% | 8182 3.06% 21.79% | 8201 3.07% 24.86% | 8425 3.15% 28.01% | 8229 3.08% 31.09% | 8315 3.11% 34.21% | 8269 3.10% 37.30% | 8279 3.10% 40.40% | 8033 3.01% 43.41% | 8159 3.05% 46.46% | 7316 2.74% 49.20% | 8194 3.07% 52.27% | 8382 3.14% 55.41% | 8204 3.07% 58.48% | 8117 3.04% 61.52% | 8878 3.32% 64.84% | 8321 3.12% 67.96% | 8274 3.10% 71.06% | 8202 3.07% 74.13% | 8422 3.15% 77.28% | 8239 3.08% 80.37% | 8482 3.18% 83.54% | 9065 3.39% 86.94% | 8995 3.37% 90.30% | 8927 3.34% 93.65% | 8865 3.32% 96.96% | 8107 3.04% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 267094 # Number of accesses per bank - -system.ruby.network.routers3.percent_links_utilized 0.006355 -system.ruby.network.routers3.msg_count.Control::0 172735 -system.ruby.network.routers3.msg_count.Response_Data::1 267094 -system.ruby.network.routers3.msg_count.Response_Control::1 120099 -system.ruby.network.routers3.msg_bytes.Control::0 1381880 -system.ruby.network.routers3.msg_bytes.Response_Data::1 19230768 -system.ruby.network.routers3.msg_bytes.Response_Control::1 960792 -system.ruby.network.routers4.percent_links_utilized 0 -system.ruby.network.routers5.percent_links_utilized 0.045409 -system.ruby.network.routers5.msg_count.Control::0 2871394 -system.ruby.network.routers5.msg_count.Request_Control::0 130302 -system.ruby.network.routers5.msg_count.Response_Data::1 2970007 -system.ruby.network.routers5.msg_count.Response_Control::1 1919997 -system.ruby.network.routers5.msg_count.Response_Control::2 1828945 -system.ruby.network.routers5.msg_count.Writeback_Data::0 1623113 -system.ruby.network.routers5.msg_count.Writeback_Data::1 325 -system.ruby.network.routers5.msg_count.Writeback_Control::0 82218 -system.ruby.network.routers5.msg_bytes.Control::0 22971152 -system.ruby.network.routers5.msg_bytes.Request_Control::0 1042416 -system.ruby.network.routers5.msg_bytes.Response_Data::1 213840504 -system.ruby.network.routers5.msg_bytes.Response_Control::1 15359976 -system.ruby.network.routers5.msg_bytes.Response_Control::2 14631560 -system.ruby.network.routers5.msg_bytes.Writeback_Data::0 116864136 -system.ruby.network.routers5.msg_bytes.Writeback_Data::1 23400 -system.ruby.network.routers5.msg_bytes.Writeback_Control::0 657744 -system.ruby.network.msg_count.Control 8614182 -system.ruby.network.msg_count.Request_Control 388943 -system.ruby.network.msg_count.Response_Data 8910021 -system.ruby.network.msg_count.Response_Control 11246826 -system.ruby.network.msg_count.Writeback_Data 4870314 -system.ruby.network.msg_count.Writeback_Control 246654 -system.ruby.network.msg_byte.Control 68913456 -system.ruby.network.msg_byte.Request_Control 3111544 -system.ruby.network.msg_byte.Response_Data 641521512 -system.ruby.network.msg_byte.Response_Control 89974608 -system.ruby.network.msg_byte.Writeback_Data 350662608 -system.ruby.network.msg_byte.Writeback_Control 1973232 +system.ruby.dir_cntrl0.memBuffer.memArbWait 2918 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 10778 3.41% 3.41% | 9652 3.06% 6.47% | 9746 3.09% 9.55% | 9756 3.09% 12.64% | 10001 3.17% 15.81% | 9844 3.12% 18.93% | 9739 3.08% 22.01% | 9701 3.07% 25.08% | 9912 3.14% 28.22% | 9771 3.09% 31.31% | 9821 3.11% 34.42% | 9856 3.12% 37.55% | 9814 3.11% 40.65% | 9541 3.02% 43.67% | 9708 3.07% 46.75% | 8720 2.76% 49.51% | 9704 3.07% 52.58% | 9910 3.14% 55.72% | 9720 3.08% 58.80% | 9615 3.04% 61.84% | 10345 3.28% 65.12% | 9799 3.10% 68.22% | 9732 3.08% 71.30% | 9663 3.06% 74.36% | 9975 3.16% 77.52% | 9775 3.10% 80.61% | 9975 3.16% 83.77% | 10515 3.33% 87.10% | 10479 3.32% 90.42% | 10356 3.28% 93.70% | 10312 3.27% 96.96% | 9590 3.04% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 315825 # Number of accesses per bank + +system.ruby.network.routers3.percent_links_utilized 0.006686 +system.ruby.network.routers3.msg_count.Control::0 174113 +system.ruby.network.routers3.msg_count.Response_Data::1 271479 +system.ruby.network.routers3.msg_count.Response_Control::1 125011 +system.ruby.network.routers3.msg_count.Writeback_Control::0 47543 +system.ruby.network.routers3.msg_count.Writeback_Control::1 46736 +system.ruby.network.routers3.msg_bytes.Control::0 1392904 +system.ruby.network.routers3.msg_bytes.Response_Data::1 19546488 +system.ruby.network.routers3.msg_bytes.Response_Control::1 1000088 +system.ruby.network.routers3.msg_bytes.Writeback_Control::0 380344 +system.ruby.network.routers3.msg_bytes.Writeback_Control::1 373888 +system.ruby.network.routers4.percent_links_utilized 0.000239 +system.ruby.network.routers4.msg_count.Response_Data::1 807 +system.ruby.network.routers4.msg_count.Writeback_Control::0 47543 +system.ruby.network.routers4.msg_count.Writeback_Control::1 46736 +system.ruby.network.routers4.msg_bytes.Response_Data::1 58104 +system.ruby.network.routers4.msg_bytes.Writeback_Control::0 380344 +system.ruby.network.routers4.msg_bytes.Writeback_Control::1 373888 +system.ruby.network.routers5.percent_links_utilized 0.045581 +system.ruby.network.routers5.msg_count.Control::0 2875657 +system.ruby.network.routers5.msg_count.Request_Control::0 131550 +system.ruby.network.routers5.msg_count.Response_Data::1 2977297 +system.ruby.network.routers5.msg_count.Response_Control::1 1926523 +system.ruby.network.routers5.msg_count.Response_Control::2 1830499 +system.ruby.network.routers5.msg_count.Writeback_Data::0 1622881 +system.ruby.network.routers5.msg_count.Writeback_Data::1 554 +system.ruby.network.routers5.msg_count.Writeback_Control::0 130704 +system.ruby.network.routers5.msg_count.Writeback_Control::1 46736 +system.ruby.network.routers5.msg_bytes.Control::0 23005256 +system.ruby.network.routers5.msg_bytes.Request_Control::0 1052400 +system.ruby.network.routers5.msg_bytes.Response_Data::1 214365384 +system.ruby.network.routers5.msg_bytes.Response_Control::1 15412184 +system.ruby.network.routers5.msg_bytes.Response_Control::2 14643992 +system.ruby.network.routers5.msg_bytes.Writeback_Data::0 116847432 +system.ruby.network.routers5.msg_bytes.Writeback_Data::1 39888 +system.ruby.network.routers5.msg_bytes.Writeback_Control::0 1045632 +system.ruby.network.routers5.msg_bytes.Writeback_Control::1 373888 +system.ruby.network.msg_count.Control 8626971 +system.ruby.network.msg_count.Request_Control 392581 +system.ruby.network.msg_count.Response_Data 8931891 +system.ruby.network.msg_count.Response_Control 11271066 +system.ruby.network.msg_count.Writeback_Data 4870305 +system.ruby.network.msg_count.Writeback_Control 532320 +system.ruby.network.msg_byte.Control 69015768 +system.ruby.network.msg_byte.Request_Control 3140648 +system.ruby.network.msg_byte.Response_Data 643096152 +system.ruby.network.msg_byte.Response_Control 90168528 +system.ruby.network.msg_byte.Writeback_Data 350661960 +system.ruby.network.msg_byte.Writeback_Control 4258560 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2987008 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 813 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.numCycles 10606783749 # number of cpu cycles simulated +system.cpu0.numCycles 10606043496 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 91841555 # Number of instructions committed -system.cpu0.committedOps 177241434 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 167144917 # Number of integer alu accesses +system.cpu0.committedInsts 90093236 # Number of instructions committed +system.cpu0.committedOps 174126687 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 164075837 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 2106041 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 16306998 # number of instructions that are conditional controls -system.cpu0.num_int_insts 167144917 # number of integer instructions +system.cpu0.num_func_calls 2042485 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 16069367 # number of instructions that are conditional controls +system.cpu0.num_int_insts 164075837 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315702148 # number of times the integer registers were read -system.cpu0.num_int_register_writes 141403252 # number of times the integer registers were written +system.cpu0.num_int_register_reads 309321057 # number of times the integer registers were read +system.cpu0.num_int_register_writes 138932000 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 97172274 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 67502160 # number of times the CC registers were written -system.cpu0.num_mem_refs 19838885 # number of memory refs -system.cpu0.num_load_insts 12792113 # Number of load instructions -system.cpu0.num_store_insts 7046772 # Number of store instructions -system.cpu0.num_idle_cycles 9879393312.871359 # Number of idle cycles -system.cpu0.num_busy_cycles 727390436.128641 # Number of busy cycles -system.cpu0.not_idle_fraction 0.068578 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.931422 # Percentage of idle cycles +system.cpu0.num_cc_register_reads 95439290 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 66446258 # number of times the CC registers were written +system.cpu0.num_mem_refs 19043793 # number of memory refs +system.cpu0.num_load_insts 12292919 # Number of load instructions +system.cpu0.num_store_insts 6750874 # Number of store instructions +system.cpu0.num_idle_cycles 9893327113.048590 # Number of idle cycles +system.cpu0.num_busy_cycles 712716382.951410 # Number of busy cycles +system.cpu0.not_idle_fraction 0.067199 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.932801 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.numCycles 10608984467 # number of cpu cycles simulated +system.cpu1.numCycles 10607208578 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 16404875 # Number of instructions committed -system.cpu1.committedOps 30456022 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 29781645 # Number of integer alu accesses +system.cpu1.committedInsts 18172065 # Number of instructions committed +system.cpu1.committedOps 33611350 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 32888204 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 684501 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2123636 # number of instructions that are conditional controls -system.cpu1.num_int_insts 29781645 # number of integer instructions +system.cpu1.num_func_calls 748563 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2364634 # number of instructions that are conditional controls +system.cpu1.num_int_insts 32888204 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 60931294 # number of times the integer registers were read -system.cpu1.num_int_register_writes 23868275 # number of times the integer registers were written +system.cpu1.num_int_register_reads 67386533 # number of times the integer registers were read +system.cpu1.num_int_register_writes 26370518 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 16456023 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 10042488 # number of times the CC registers were written -system.cpu1.num_mem_refs 7344657 # number of memory refs -system.cpu1.num_load_insts 4252428 # Number of load instructions -system.cpu1.num_store_insts 3092229 # Number of store instructions -system.cpu1.num_idle_cycles 10473305727.446026 # Number of idle cycles -system.cpu1.num_busy_cycles 135678739.553974 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012789 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987211 # Percentage of idle cycles +system.cpu1.num_cc_register_reads 18215408 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 11108428 # number of times the CC registers were written +system.cpu1.num_mem_refs 8150413 # number of memory refs +system.cpu1.num_load_insts 4758811 # Number of load instructions +system.cpu1.num_store_insts 3391602 # Number of store instructions +system.cpu1.num_idle_cycles 10456532847.286028 # Number of idle cycles +system.cpu1.num_busy_cycles 150675730.713972 # Number of busy cycles +system.cpu1.not_idle_fraction 0.014205 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.985795 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.ruby.network.routers0.throttle0.link_utilization 0.096297 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 68326 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 2091943 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 1536429 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::0 546608 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 150619896 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 12291432 -system.ruby.network.routers0.throttle1.link_utilization 0.081281 -system.ruby.network.routers0.throttle1.msg_count.Control::0 2111651 -system.ruby.network.routers0.throttle1.msg_count.Response_Data::1 62891 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 28940 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 1557069 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 1435847 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 52 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 59460 -system.ruby.network.routers0.throttle1.msg_bytes.Control::0 16893208 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1 4528152 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 231520 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 12456552 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 103380984 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 3744 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 475680 -system.ruby.network.routers1.throttle0.link_utilization 0.025474 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 61976 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 565416 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 254379 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 495808 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 40709952 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 2035032 -system.ruby.network.routers1.throttle1.link_utilization 0.014743 -system.ruby.network.routers1.throttle1.msg_count.Control::0 587008 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 59373 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 24327 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::2 271876 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0 187266 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1 273 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 22758 -system.ruby.network.routers1.throttle1.msg_bytes.Control::0 4696064 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 4274856 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 194616 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2 2175008 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0 13483152 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1 19656 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 182064 -system.ruby.network.routers2.throttle0.link_utilization 0.100395 -system.ruby.network.routers2.throttle0.msg_count.Control::0 2698659 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 218289 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 116319 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::2 1828945 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0 1623113 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1 325 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0 82218 -system.ruby.network.routers2.throttle0.msg_bytes.Control::0 21589272 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 15716808 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 930552 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2 14631560 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0 116864136 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1 23400 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0 657744 -system.ruby.network.routers2.throttle1.link_utilization 0.123177 -system.ruby.network.routers2.throttle1.msg_count.Control::0 172735 -system.ruby.network.routers2.throttle1.msg_count.Request_Control::0 128339 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 2675008 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1759501 -system.ruby.network.routers2.throttle1.msg_bytes.Control::0 1381880 -system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::0 1026712 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 192600576 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 14076008 -system.ruby.network.routers3.throttle0.link_utilization 0.004877 -system.ruby.network.routers3.throttle0.msg_count.Control::0 172735 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 94359 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 12870 -system.ruby.network.routers3.throttle0.msg_bytes.Control::0 1381880 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 6793848 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 102960 -system.ruby.network.routers3.throttle1.link_utilization 0.007832 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 172735 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 107229 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 12436920 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 857832 -system.ruby.network.routers4.throttle0.link_utilization 0 -system.ruby.network.routers4.throttle1.link_utilization 0 -system.ruby.network.routers5.throttle0.link_utilization 0.096297 -system.ruby.network.routers5.throttle0.msg_count.Request_Control::0 68326 -system.ruby.network.routers5.throttle0.msg_count.Response_Data::1 2091943 -system.ruby.network.routers5.throttle0.msg_count.Response_Control::1 1536429 -system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::0 546608 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::1 150619896 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::1 12291432 -system.ruby.network.routers5.throttle1.link_utilization 0.025474 -system.ruby.network.routers5.throttle1.msg_count.Request_Control::0 61976 -system.ruby.network.routers5.throttle1.msg_count.Response_Data::1 565416 -system.ruby.network.routers5.throttle1.msg_count.Response_Control::1 254379 -system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::0 495808 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::1 40709952 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::1 2035032 -system.ruby.network.routers5.throttle2.link_utilization 0.100395 -system.ruby.network.routers5.throttle2.msg_count.Control::0 2698659 -system.ruby.network.routers5.throttle2.msg_count.Response_Data::1 218289 -system.ruby.network.routers5.throttle2.msg_count.Response_Control::1 116319 -system.ruby.network.routers5.throttle2.msg_count.Response_Control::2 1828945 -system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::0 1623113 -system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::1 325 -system.ruby.network.routers5.throttle2.msg_count.Writeback_Control::0 82218 -system.ruby.network.routers5.throttle2.msg_bytes.Control::0 21589272 -system.ruby.network.routers5.throttle2.msg_bytes.Response_Data::1 15716808 -system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::1 930552 -system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::2 14631560 -system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::0 116864136 -system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::1 23400 -system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Control::0 657744 -system.ruby.network.routers5.throttle3.link_utilization 0.004877 -system.ruby.network.routers5.throttle3.msg_count.Control::0 172735 -system.ruby.network.routers5.throttle3.msg_count.Response_Data::1 94359 -system.ruby.network.routers5.throttle3.msg_count.Response_Control::1 12870 -system.ruby.network.routers5.throttle3.msg_bytes.Control::0 1381880 -system.ruby.network.routers5.throttle3.msg_bytes.Response_Data::1 6793848 -system.ruby.network.routers5.throttle3.msg_bytes.Response_Control::1 102960 -system.ruby.network.routers5.throttle4.link_utilization 0 -system.ruby.l1_cntrl0.Load | 11423199 74.37% 74.37% | 3936524 25.63% 100.00% -system.ruby.l1_cntrl0.Load::total 15359723 - -system.ruby.l1_cntrl0.Ifetch | 107224661 83.42% 83.42% | 21310786 16.58% 100.00% -system.ruby.l1_cntrl0.Ifetch::total 128535447 - -system.ruby.l1_cntrl0.Store | 7581183 69.10% 69.10% | 3389377 30.90% 100.00% -system.ruby.l1_cntrl0.Store::total 10970560 - -system.ruby.l1_cntrl0.Inv | 28992 54.10% 54.10% | 24600 45.90% 100.00% -system.ruby.l1_cntrl0.Inv::total 53592 - -system.ruby.l1_cntrl0.L1_Replacement | 2066674 79.29% 79.29% | 539794 20.71% 100.00% -system.ruby.l1_cntrl0.L1_Replacement::total 2606468 - -system.ruby.l1_cntrl0.Fwd_GETX | 15777 50.64% 50.64% | 15379 49.36% 100.00% -system.ruby.l1_cntrl0.Fwd_GETX::total 31156 - -system.ruby.l1_cntrl0.Fwd_GETS | 23553 51.71% 51.71% | 21997 48.29% 100.00% -system.ruby.l1_cntrl0.Fwd_GETS::total 45550 - -system.ruby.l1_cntrl0.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.l1_cntrl0.Fwd_GET_INSTR::total 4 - -system.ruby.l1_cntrl0.Data | 1706 59.30% 59.30% | 1171 40.70% 100.00% -system.ruby.l1_cntrl0.Data::total 2877 - -system.ruby.l1_cntrl0.Data_Exclusive | 1216870 92.56% 92.56% | 97821 7.44% 100.00% -system.ruby.l1_cntrl0.Data_Exclusive::total 1314691 - -system.ruby.l1_cntrl0.DataS_fromL1 | 21997 48.29% 48.29% | 23557 51.71% 100.00% -system.ruby.l1_cntrl0.DataS_fromL1::total 45554 - -system.ruby.l1_cntrl0.Data_all_Acks | 851370 65.78% 65.78% | 442867 34.22% 100.00% -system.ruby.l1_cntrl0.Data_all_Acks::total 1294237 - -system.ruby.l1_cntrl0.Ack | 19708 47.72% 47.72% | 21592 52.28% 100.00% -system.ruby.l1_cntrl0.Ack::total 41300 - -system.ruby.l1_cntrl0.Ack_all | 21414 48.47% 48.47% | 22763 51.53% 100.00% -system.ruby.l1_cntrl0.Ack_all::total 44177 - -system.ruby.l1_cntrl0.WB_Ack | 1495307 87.68% 87.68% | 210024 12.32% 100.00% -system.ruby.l1_cntrl0.WB_Ack::total 1705331 - -system.ruby.l1_cntrl0.NP.Load | 1269187 90.60% 90.60% | 131722 9.40% 100.00% -system.ruby.l1_cntrl0.NP.Load::total 1400909 - -system.ruby.l1_cntrl0.NP.Ifetch | 507807 63.72% 63.72% | 289135 36.28% 100.00% -system.ruby.l1_cntrl0.NP.Ifetch::total 796942 - -system.ruby.l1_cntrl0.NP.Store | 290704 70.79% 70.79% | 119960 29.21% 100.00% -system.ruby.l1_cntrl0.NP.Store::total 410664 - -system.ruby.l1_cntrl0.NP.Inv | 6486 66.07% 66.07% | 3331 33.93% 100.00% -system.ruby.l1_cntrl0.NP.Inv::total 9817 - -system.ruby.l1_cntrl0.I.Load | 16022 50.92% 50.92% | 15443 49.08% 100.00% -system.ruby.l1_cntrl0.I.Load::total 31465 +system.ruby.network.routers0.throttle0.link_utilization 0.092567 +system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 68787 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 2008081 +system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 1496069 +system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::0 550296 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 144581832 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 11968552 +system.ruby.network.routers0.throttle1.link_utilization 0.079316 +system.ruby.network.routers0.throttle1.msg_count.Control::0 2027886 +system.ruby.network.routers0.throttle1.msg_count.Response_Data::1 62968 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 29210 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 1517023 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 1403655 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 171 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 51157 +system.ruby.network.routers0.throttle1.msg_bytes.Control::0 16223088 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1 4533696 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 233680 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 12136184 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 101063160 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 12312 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 409256 +system.ruby.network.routers1.throttle0.link_utilization 0.029348 +system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 62763 +system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 651911 +system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 295944 +system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 502104 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 46937592 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 2367552 +system.ruby.network.routers1.throttle1.link_utilization 0.016780 +system.ruby.network.routers1.throttle1.msg_count.Control::0 673658 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 59936 +system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 24708 +system.ruby.network.routers1.throttle1.msg_count.Response_Control::2 313476 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0 219226 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1 383 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 32004 +system.ruby.network.routers1.throttle1.msg_bytes.Control::0 5389264 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 4315392 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 197664 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2 2507808 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0 15784272 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1 27576 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 256032 +system.ruby.network.routers2.throttle0.link_utilization 0.100531 +system.ruby.network.routers2.throttle0.msg_count.Control::0 2701544 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 219939 +system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 121479 +system.ruby.network.routers2.throttle0.msg_count.Response_Control::2 1830499 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0 1622881 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1 554 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0 83161 +system.ruby.network.routers2.throttle0.msg_bytes.Control::0 21612352 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 15835608 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 971832 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2 14643992 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0 116847432 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1 39888 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0 665288 +system.ruby.network.routers2.throttle1.link_utilization 0.123404 +system.ruby.network.routers2.throttle1.msg_count.Control::0 174113 +system.ruby.network.routers2.throttle1.msg_count.Request_Control::0 129481 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 2679473 +system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1760625 +system.ruby.network.routers2.throttle1.msg_bytes.Control::0 1392904 +system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::0 1035848 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 192922056 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 14085000 +system.ruby.network.routers3.throttle0.link_utilization 0.005203 +system.ruby.network.routers3.throttle0.msg_count.Control::0 174113 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 96559 +system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 13031 +system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 47543 +system.ruby.network.routers3.throttle0.msg_bytes.Control::0 1392904 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 6952248 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 104248 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 380344 +system.ruby.network.routers3.throttle1.link_utilization 0.008169 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 174920 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 111980 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 46736 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 12594240 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 895840 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 373888 +system.ruby.network.routers4.throttle0.link_utilization 0.000255 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 807 +system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1 46736 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58104 +system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1 373888 +system.ruby.network.routers4.throttle1.link_utilization 0.000224 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47543 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380344 +system.ruby.network.routers5.throttle0.link_utilization 0.092567 +system.ruby.network.routers5.throttle0.msg_count.Request_Control::0 68787 +system.ruby.network.routers5.throttle0.msg_count.Response_Data::1 2008081 +system.ruby.network.routers5.throttle0.msg_count.Response_Control::1 1496069 +system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::0 550296 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::1 144581832 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::1 11968552 +system.ruby.network.routers5.throttle1.link_utilization 0.029348 +system.ruby.network.routers5.throttle1.msg_count.Request_Control::0 62763 +system.ruby.network.routers5.throttle1.msg_count.Response_Data::1 651911 +system.ruby.network.routers5.throttle1.msg_count.Response_Control::1 295944 +system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::0 502104 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::1 46937592 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::1 2367552 +system.ruby.network.routers5.throttle2.link_utilization 0.100531 +system.ruby.network.routers5.throttle2.msg_count.Control::0 2701544 +system.ruby.network.routers5.throttle2.msg_count.Response_Data::1 219939 +system.ruby.network.routers5.throttle2.msg_count.Response_Control::1 121479 +system.ruby.network.routers5.throttle2.msg_count.Response_Control::2 1830499 +system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::0 1622881 +system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::1 554 +system.ruby.network.routers5.throttle2.msg_count.Writeback_Control::0 83161 +system.ruby.network.routers5.throttle2.msg_bytes.Control::0 21612352 +system.ruby.network.routers5.throttle2.msg_bytes.Response_Data::1 15835608 +system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::1 971832 +system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::2 14643992 +system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::0 116847432 +system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::1 39888 +system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Control::0 665288 +system.ruby.network.routers5.throttle3.link_utilization 0.005203 +system.ruby.network.routers5.throttle3.msg_count.Control::0 174113 +system.ruby.network.routers5.throttle3.msg_count.Response_Data::1 96559 +system.ruby.network.routers5.throttle3.msg_count.Response_Control::1 13031 +system.ruby.network.routers5.throttle3.msg_count.Writeback_Control::0 47543 +system.ruby.network.routers5.throttle3.msg_bytes.Control::0 1392904 +system.ruby.network.routers5.throttle3.msg_bytes.Response_Data::1 6952248 +system.ruby.network.routers5.throttle3.msg_bytes.Response_Control::1 104248 +system.ruby.network.routers5.throttle3.msg_bytes.Writeback_Control::0 380344 +system.ruby.network.routers5.throttle4.link_utilization 0.000255 +system.ruby.network.routers5.throttle4.msg_count.Response_Data::1 807 +system.ruby.network.routers5.throttle4.msg_count.Writeback_Control::1 46736 +system.ruby.network.routers5.throttle4.msg_bytes.Response_Data::1 58104 +system.ruby.network.routers5.throttle4.msg_bytes.Writeback_Control::1 373888 +system.ruby.l1_cntrl0.Load | 10937660 71.18% 71.18% | 4428777 28.82% 100.00% +system.ruby.l1_cntrl0.Load::total 15366437 + +system.ruby.l1_cntrl0.Ifetch | 104942071 81.63% 81.63% | 23615568 18.37% 100.00% +system.ruby.l1_cntrl0.Ifetch::total 128557639 + +system.ruby.l1_cntrl0.Store | 7262825 66.18% 66.18% | 3711569 33.82% 100.00% +system.ruby.l1_cntrl0.Store::total 10974394 + +system.ruby.l1_cntrl0.Inv | 29381 53.94% 53.94% | 25091 46.06% 100.00% +system.ruby.l1_cntrl0.Inv::total 54472 + +system.ruby.l1_cntrl0.L1_Replacement | 1982628 75.99% 75.99% | 626364 24.01% 100.00% +system.ruby.l1_cntrl0.L1_Replacement::total 2608992 + +system.ruby.l1_cntrl0.Fwd_GETX | 15844 50.70% 50.70% | 15408 49.30% 100.00% +system.ruby.l1_cntrl0.Fwd_GETX::total 31252 + +system.ruby.l1_cntrl0.Fwd_GETS | 23557 51.41% 51.41% | 22264 48.59% 100.00% +system.ruby.l1_cntrl0.Fwd_GETS::total 45821 + +system.ruby.l1_cntrl0.Fwd_GET_INSTR | 5 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.l1_cntrl0.Fwd_GET_INSTR::total 5 + +system.ruby.l1_cntrl0.Data | 1647 57.45% 57.45% | 1220 42.55% 100.00% +system.ruby.l1_cntrl0.Data::total 2867 + +system.ruby.l1_cntrl0.Data_Exclusive | 1191679 90.64% 90.64% | 123071 9.36% 100.00% +system.ruby.l1_cntrl0.Data_Exclusive::total 1314750 + +system.ruby.l1_cntrl0.DataS_fromL1 | 22264 48.58% 48.58% | 23562 51.42% 100.00% +system.ruby.l1_cntrl0.DataS_fromL1::total 45826 + +system.ruby.l1_cntrl0.Data_all_Acks | 792491 61.12% 61.12% | 504058 38.88% 100.00% +system.ruby.l1_cntrl0.Data_all_Acks::total 1296549 + +system.ruby.l1_cntrl0.Ack | 19805 47.66% 47.66% | 21747 52.34% 100.00% +system.ruby.l1_cntrl0.Ack::total 41552 + +system.ruby.l1_cntrl0.Ack_all | 21452 48.29% 48.29% | 22967 51.71% 100.00% +system.ruby.l1_cntrl0.Ack_all::total 44419 + +system.ruby.l1_cntrl0.WB_Ack | 1454812 85.27% 85.27% | 251230 14.73% 100.00% +system.ruby.l1_cntrl0.WB_Ack::total 1706042 + +system.ruby.l1_cntrl0.NP.Load | 1239865 88.45% 88.45% | 161879 11.55% 100.00% +system.ruby.l1_cntrl0.NP.Load::total 1401744 + +system.ruby.l1_cntrl0.NP.Ifetch | 468275 58.71% 58.71% | 329378 41.29% 100.00% +system.ruby.l1_cntrl0.NP.Ifetch::total 797653 + +system.ruby.l1_cntrl0.NP.Store | 275512 66.93% 66.93% | 136131 33.07% 100.00% +system.ruby.l1_cntrl0.NP.Store::total 411643 + +system.ruby.l1_cntrl0.NP.Inv | 6534 64.01% 64.01% | 3673 35.99% 100.00% +system.ruby.l1_cntrl0.NP.Inv::total 10207 -system.ruby.l1_cntrl0.I.Ifetch | 433 67.34% 67.34% | 210 32.66% 100.00% -system.ruby.l1_cntrl0.I.Ifetch::total 643 +system.ruby.l1_cntrl0.I.Load | 16225 51.38% 51.38% | 15353 48.62% 100.00% +system.ruby.l1_cntrl0.I.Load::total 31578 -system.ruby.l1_cntrl0.I.Store | 7790 46.55% 46.55% | 8946 53.45% 100.00% -system.ruby.l1_cntrl0.I.Store::total 16736 +system.ruby.l1_cntrl0.I.Ifetch | 441 68.27% 68.27% | 205 31.73% 100.00% +system.ruby.l1_cntrl0.I.Ifetch::total 646 -system.ruby.l1_cntrl0.I.L1_Replacement | 13955 53.66% 53.66% | 12049 46.34% 100.00% -system.ruby.l1_cntrl0.I.L1_Replacement::total 26004 +system.ruby.l1_cntrl0.I.Store | 7763 46.41% 46.41% | 8965 53.59% 100.00% +system.ruby.l1_cntrl0.I.Store::total 16728 -system.ruby.l1_cntrl0.S.Load | 738807 59.22% 59.22% | 508786 40.78% 100.00% -system.ruby.l1_cntrl0.S.Load::total 1247593 +system.ruby.l1_cntrl0.I.L1_Replacement | 14196 53.57% 53.57% | 12303 46.43% 100.00% +system.ruby.l1_cntrl0.I.L1_Replacement::total 26499 -system.ruby.l1_cntrl0.S.Ifetch | 106716418 83.54% 83.54% | 21021438 16.46% 100.00% -system.ruby.l1_cntrl0.S.Ifetch::total 127737856 +system.ruby.l1_cntrl0.S.Load | 716363 57.80% 57.80% | 523017 42.20% 100.00% +system.ruby.l1_cntrl0.S.Load::total 1239380 -system.ruby.l1_cntrl0.S.Store | 19708 47.72% 47.72% | 21592 52.28% 100.00% -system.ruby.l1_cntrl0.S.Store::total 41300 +system.ruby.l1_cntrl0.S.Ifetch | 104473354 81.77% 81.77% | 23285981 18.23% 100.00% +system.ruby.l1_cntrl0.S.Ifetch::total 127759335 -system.ruby.l1_cntrl0.S.Inv | 22433 51.85% 51.85% | 20836 48.15% 100.00% -system.ruby.l1_cntrl0.S.Inv::total 43269 +system.ruby.l1_cntrl0.S.Store | 19805 47.66% 47.66% | 21747 52.34% 100.00% +system.ruby.l1_cntrl0.S.Store::total 41552 -system.ruby.l1_cntrl0.S.L1_Replacement | 557412 63.69% 63.69% | 317721 36.31% 100.00% -system.ruby.l1_cntrl0.S.L1_Replacement::total 875133 +system.ruby.l1_cntrl0.S.Inv | 22660 52.04% 52.04% | 20885 47.96% 100.00% +system.ruby.l1_cntrl0.S.Inv::total 43545 -system.ruby.l1_cntrl0.E.Load | 3045109 82.70% 82.70% | 636901 17.30% 100.00% -system.ruby.l1_cntrl0.E.Load::total 3682010 +system.ruby.l1_cntrl0.S.L1_Replacement | 513620 58.60% 58.60% | 362831 41.40% 100.00% +system.ruby.l1_cntrl0.S.L1_Replacement::total 876451 -system.ruby.l1_cntrl0.E.Store | 119075 77.49% 77.49% | 34591 22.51% 100.00% -system.ruby.l1_cntrl0.E.Store::total 153666 +system.ruby.l1_cntrl0.E.Load | 2877485 78.07% 78.07% | 808285 21.93% 100.00% +system.ruby.l1_cntrl0.E.Load::total 3685770 -system.ruby.l1_cntrl0.E.Inv | 21 11.60% 11.60% | 160 88.40% 100.00% -system.ruby.l1_cntrl0.E.Inv::total 181 +system.ruby.l1_cntrl0.E.Store | 114491 74.50% 74.50% | 39180 25.50% 100.00% +system.ruby.l1_cntrl0.E.Store::total 153671 -system.ruby.l1_cntrl0.E.L1_Replacement | 1096110 94.67% 94.67% | 61694 5.33% 100.00% -system.ruby.l1_cntrl0.E.L1_Replacement::total 1157804 +system.ruby.l1_cntrl0.E.Inv | 16 9.64% 9.64% | 150 90.36% 100.00% +system.ruby.l1_cntrl0.E.Inv::total 166 -system.ruby.l1_cntrl0.E.Fwd_GETX | 178 53.13% 53.13% | 157 46.87% 100.00% -system.ruby.l1_cntrl0.E.Fwd_GETX::total 335 +system.ruby.l1_cntrl0.E.L1_Replacement | 1075597 92.92% 92.92% | 82009 7.08% 100.00% +system.ruby.l1_cntrl0.E.L1_Replacement::total 1157606 -system.ruby.l1_cntrl0.E.Fwd_GETS | 1386 57.01% 57.01% | 1045 42.99% 100.00% -system.ruby.l1_cntrl0.E.Fwd_GETS::total 2431 +system.ruby.l1_cntrl0.E.Fwd_GETX | 157 36.77% 36.77% | 270 63.23% 100.00% +system.ruby.l1_cntrl0.E.Fwd_GETX::total 427 -system.ruby.l1_cntrl0.M.Load | 6354074 70.62% 70.62% | 2643672 29.38% 100.00% -system.ruby.l1_cntrl0.M.Load::total 8997746 +system.ruby.l1_cntrl0.E.Fwd_GETS | 1309 50.17% 50.17% | 1300 49.83% 100.00% +system.ruby.l1_cntrl0.E.Fwd_GETS::total 2609 -system.ruby.l1_cntrl0.M.Store | 7143906 69.04% 69.04% | 3204288 30.96% 100.00% -system.ruby.l1_cntrl0.M.Store::total 10348194 +system.ruby.l1_cntrl0.E.Fwd_GET_INSTR | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.l1_cntrl0.E.Fwd_GET_INSTR::total 1 -system.ruby.l1_cntrl0.M.Inv | 52 16.00% 16.00% | 273 84.00% 100.00% -system.ruby.l1_cntrl0.M.Inv::total 325 +system.ruby.l1_cntrl0.M.Load | 6087722 67.58% 67.58% | 2920243 32.42% 100.00% +system.ruby.l1_cntrl0.M.Load::total 9007965 -system.ruby.l1_cntrl0.M.L1_Replacement | 399197 72.91% 72.91% | 148330 27.09% 100.00% -system.ruby.l1_cntrl0.M.L1_Replacement::total 547527 +system.ruby.l1_cntrl0.M.Store | 6845254 66.13% 66.13% | 3505546 33.87% 100.00% +system.ruby.l1_cntrl0.M.Store::total 10350800 -system.ruby.l1_cntrl0.M.Fwd_GETX | 15599 50.61% 50.61% | 15222 49.39% 100.00% -system.ruby.l1_cntrl0.M.Fwd_GETX::total 30821 +system.ruby.l1_cntrl0.M.Inv | 171 30.87% 30.87% | 383 69.13% 100.00% +system.ruby.l1_cntrl0.M.Inv::total 554 -system.ruby.l1_cntrl0.M.Fwd_GETS | 22167 51.41% 51.41% | 20952 48.59% 100.00% -system.ruby.l1_cntrl0.M.Fwd_GETS::total 43119 +system.ruby.l1_cntrl0.M.L1_Replacement | 379215 69.14% 69.14% | 169221 30.86% 100.00% +system.ruby.l1_cntrl0.M.L1_Replacement::total 548436 + +system.ruby.l1_cntrl0.M.Fwd_GETX | 15687 50.89% 50.89% | 15138 49.11% 100.00% +system.ruby.l1_cntrl0.M.Fwd_GETX::total 30825 + +system.ruby.l1_cntrl0.M.Fwd_GETS | 22248 51.49% 51.49% | 20963 48.51% 100.00% +system.ruby.l1_cntrl0.M.Fwd_GETS::total 43211 system.ruby.l1_cntrl0.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.l1_cntrl0.M.Fwd_GET_INSTR::total 4 -system.ruby.l1_cntrl0.IS.Data_Exclusive | 1216870 92.56% 92.56% | 97821 7.44% 100.00% -system.ruby.l1_cntrl0.IS.Data_Exclusive::total 1314691 - -system.ruby.l1_cntrl0.IS.DataS_fromL1 | 21997 48.29% 48.29% | 23557 51.71% 100.00% -system.ruby.l1_cntrl0.IS.DataS_fromL1::total 45554 - -system.ruby.l1_cntrl0.IS.Data_all_Acks | 554582 63.77% 63.77% | 315132 36.23% 100.00% -system.ruby.l1_cntrl0.IS.Data_all_Acks::total 869714 - -system.ruby.l1_cntrl0.IM.Data | 1706 59.30% 59.30% | 1171 40.70% 100.00% -system.ruby.l1_cntrl0.IM.Data::total 2877 - -system.ruby.l1_cntrl0.IM.Data_all_Acks | 296788 69.91% 69.91% | 127735 30.09% 100.00% -system.ruby.l1_cntrl0.IM.Data_all_Acks::total 424523 - -system.ruby.l1_cntrl0.SM.Ack | 19708 47.72% 47.72% | 21592 52.28% 100.00% -system.ruby.l1_cntrl0.SM.Ack::total 41300 - -system.ruby.l1_cntrl0.SM.Ack_all | 21414 48.47% 48.47% | 22763 51.53% 100.00% -system.ruby.l1_cntrl0.SM.Ack_all::total 44177 - -system.ruby.l1_cntrl0.M_I.Ifetch | 3 50.00% 50.00% | 3 50.00% 100.00% -system.ruby.l1_cntrl0.M_I.Ifetch::total 6 - -system.ruby.l1_cntrl0.M_I.WB_Ack | 1495307 87.68% 87.68% | 210024 12.32% 100.00% -system.ruby.l1_cntrl0.M_I.WB_Ack::total 1705331 - -system.ruby.l2_cntrl0.L1_GET_INSTR 797586 0.00% 0.00% -system.ruby.l2_cntrl0.L1_GETS 1432569 0.00% 0.00% -system.ruby.l2_cntrl0.L1_GETX 427401 0.00% 0.00% -system.ruby.l2_cntrl0.L1_UPGRADE 41300 0.00% 0.00% -system.ruby.l2_cntrl0.L1_PUTX 1705331 0.00% 0.00% -system.ruby.l2_cntrl0.L2_Replacement 94194 0.00% 0.00% -system.ruby.l2_cntrl0.L2_Replacement_clean 13035 0.00% 0.00% -system.ruby.l2_cntrl0.Mem_Data 172735 0.00% 0.00% -system.ruby.l2_cntrl0.Mem_Ack 107229 0.00% 0.00% -system.ruby.l2_cntrl0.WB_Data 45318 0.00% 0.00% -system.ruby.l2_cntrl0.WB_Data_clean 561 0.00% 0.00% -system.ruby.l2_cntrl0.Ack 1963 0.00% 0.00% -system.ruby.l2_cntrl0.Ack_all 7127 0.00% 0.00% -system.ruby.l2_cntrl0.Unblock 45554 0.00% 0.00% -system.ruby.l2_cntrl0.Exclusive_Unblock 1783391 0.00% 0.00% -system.ruby.l2_cntrl0.NP.L1_GET_INSTR 15440 0.00% 0.00% -system.ruby.l2_cntrl0.NP.L1_GETS 31271 0.00% 0.00% -system.ruby.l2_cntrl0.NP.L1_GETX 126024 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L1_GET_INSTR 781852 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L1_GETS 72133 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L1_GETX 3021 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L1_UPGRADE 41300 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L2_Replacement 241 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L2_Replacement_clean 6705 0.00% 0.00% -system.ruby.l2_cntrl0.M.L1_GET_INSTR 289 0.00% 0.00% -system.ruby.l2_cntrl0.M.L1_GETS 1283420 0.00% 0.00% -system.ruby.l2_cntrl0.M.L1_GETX 267199 0.00% 0.00% -system.ruby.l2_cntrl0.M.L2_Replacement 93756 0.00% 0.00% -system.ruby.l2_cntrl0.M.L2_Replacement_clean 6021 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L1_GET_INSTR 4 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L1_GETS 45550 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L1_GETX 31156 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L1_PUTX 1705331 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L2_Replacement 197 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L2_Replacement_clean 309 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_Exclusive | 1191679 90.64% 90.64% | 123071 9.36% 100.00% +system.ruby.l1_cntrl0.IS.Data_Exclusive::total 1314750 + +system.ruby.l1_cntrl0.IS.DataS_fromL1 | 22264 48.58% 48.58% | 23562 51.42% 100.00% +system.ruby.l1_cntrl0.IS.DataS_fromL1::total 45826 + +system.ruby.l1_cntrl0.IS.Data_all_Acks | 510863 58.65% 58.65% | 360182 41.35% 100.00% +system.ruby.l1_cntrl0.IS.Data_all_Acks::total 871045 + +system.ruby.l1_cntrl0.IM.Data | 1647 57.45% 57.45% | 1220 42.55% 100.00% +system.ruby.l1_cntrl0.IM.Data::total 2867 + +system.ruby.l1_cntrl0.IM.Data_all_Acks | 281628 66.19% 66.19% | 143876 33.81% 100.00% +system.ruby.l1_cntrl0.IM.Data_all_Acks::total 425504 + +system.ruby.l1_cntrl0.SM.Ack | 19805 47.66% 47.66% | 21747 52.34% 100.00% +system.ruby.l1_cntrl0.SM.Ack::total 41552 + +system.ruby.l1_cntrl0.SM.Ack_all | 21452 48.29% 48.29% | 22967 51.71% 100.00% +system.ruby.l1_cntrl0.SM.Ack_all::total 44419 + +system.ruby.l1_cntrl0.M_I.Ifetch | 1 20.00% 20.00% | 4 80.00% 100.00% +system.ruby.l1_cntrl0.M_I.Ifetch::total 5 + +system.ruby.l1_cntrl0.M_I.Fwd_GETS | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.l1_cntrl0.M_I.Fwd_GETS::total 1 + +system.ruby.l1_cntrl0.M_I.WB_Ack | 1454812 85.27% 85.27% | 251229 14.73% 100.00% +system.ruby.l1_cntrl0.M_I.WB_Ack::total 1706041 + +system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack::total 1 + +system.ruby.l2_cntrl0.L1_GET_INSTR 798300 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETS 1433505 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETX 428371 0.00% 0.00% +system.ruby.l2_cntrl0.L1_UPGRADE 41552 0.00% 0.00% +system.ruby.l2_cntrl0.L1_PUTX 1706043 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement 93999 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement_clean 13201 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Data 174113 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Ack 109590 0.00% 0.00% +system.ruby.l2_cntrl0.WB_Data 45725 0.00% 0.00% +system.ruby.l2_cntrl0.WB_Data_clean 655 0.00% 0.00% +system.ruby.l2_cntrl0.Ack 2069 0.00% 0.00% +system.ruby.l2_cntrl0.Ack_all 7430 0.00% 0.00% +system.ruby.l2_cntrl0.Unblock 45826 0.00% 0.00% +system.ruby.l2_cntrl0.Exclusive_Unblock 1784673 0.00% 0.00% +system.ruby.l2_cntrl0.MEM_Inv 4780 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GET_INSTR 15882 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETS 31693 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETX 126538 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GET_INSTR 782387 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GETS 72751 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GETX 3011 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_UPGRADE 41552 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_PUTX 1 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L2_Replacement 271 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L2_Replacement_clean 6989 0.00% 0.00% +system.ruby.l2_cntrl0.SS.MEM_Inv 4 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GET_INSTR 25 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETS 1283057 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETX 267570 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement 93550 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement_clean 5909 0.00% 0.00% +system.ruby.l2_cntrl0.M.MEM_Inv 2147 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_GET_INSTR 5 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_GETS 45821 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_GETX 31252 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_PUTX 1706041 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L2_Replacement 178 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L2_Replacement_clean 303 0.00% 0.00% +system.ruby.l2_cntrl0.MT.MEM_Inv 239 0.00% 0.00% system.ruby.l2_cntrl0.M_I.L1_GET_INSTR 1 0.00% 0.00% -system.ruby.l2_cntrl0.M_I.Mem_Ack 107229 0.00% 0.00% -system.ruby.l2_cntrl0.MT_I.WB_Data 160 0.00% 0.00% -system.ruby.l2_cntrl0.MT_I.Ack_all 37 0.00% 0.00% -system.ruby.l2_cntrl0.MCT_I.WB_Data 165 0.00% 0.00% -system.ruby.l2_cntrl0.MCT_I.Ack_all 144 0.00% 0.00% -system.ruby.l2_cntrl0.I_I.Ack 1732 0.00% 0.00% -system.ruby.l2_cntrl0.I_I.Ack_all 6705 0.00% 0.00% -system.ruby.l2_cntrl0.S_I.Ack 231 0.00% 0.00% -system.ruby.l2_cntrl0.S_I.Ack_all 241 0.00% 0.00% -system.ruby.l2_cntrl0.ISS.Mem_Data 31271 0.00% 0.00% -system.ruby.l2_cntrl0.IS.Mem_Data 15440 0.00% 0.00% -system.ruby.l2_cntrl0.IM.Mem_Data 126024 0.00% 0.00% -system.ruby.l2_cntrl0.SS_MB.L1_GETS 136 0.00% 0.00% -system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 44321 0.00% 0.00% -system.ruby.l2_cntrl0.MT_MB.L1_GETS 59 0.00% 0.00% -system.ruby.l2_cntrl0.MT_MB.L1_GETX 1 0.00% 0.00% -system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 1739070 0.00% 0.00% -system.ruby.l2_cntrl0.MT_IIB.WB_Data 44897 0.00% 0.00% -system.ruby.l2_cntrl0.MT_IIB.WB_Data_clean 561 0.00% 0.00% -system.ruby.l2_cntrl0.MT_IIB.Unblock 96 0.00% 0.00% -system.ruby.l2_cntrl0.MT_IB.WB_Data 96 0.00% 0.00% -system.ruby.l2_cntrl0.MT_SB.Unblock 45458 0.00% 0.00% -system.ruby.dir_cntrl0.Fetch 172735 0.00% 0.00% -system.ruby.dir_cntrl0.Data 94359 0.00% 0.00% -system.ruby.dir_cntrl0.Memory_Data 172735 0.00% 0.00% -system.ruby.dir_cntrl0.Memory_Ack 94359 0.00% 0.00% -system.ruby.dir_cntrl0.CleanReplacement 12870 0.00% 0.00% -system.ruby.dir_cntrl0.I.Fetch 172735 0.00% 0.00% -system.ruby.dir_cntrl0.M.Data 94359 0.00% 0.00% -system.ruby.dir_cntrl0.M.CleanReplacement 12870 0.00% 0.00% -system.ruby.dir_cntrl0.IM.Memory_Data 172735 0.00% 0.00% -system.ruby.dir_cntrl0.MI.Memory_Ack 94359 0.00% 0.00% +system.ruby.l2_cntrl0.M_I.Mem_Ack 109590 0.00% 0.00% +system.ruby.l2_cntrl0.M_I.MEM_Inv 2147 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.WB_Data 384 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.Ack_all 33 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.MEM_Inv 239 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.WB_Data 170 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.Ack_all 133 0.00% 0.00% +system.ruby.l2_cntrl0.I_I.Ack 1795 0.00% 0.00% +system.ruby.l2_cntrl0.I_I.Ack_all 6989 0.00% 0.00% +system.ruby.l2_cntrl0.S_I.Ack 274 0.00% 0.00% +system.ruby.l2_cntrl0.S_I.Ack_all 275 0.00% 0.00% +system.ruby.l2_cntrl0.S_I.MEM_Inv 4 0.00% 0.00% +system.ruby.l2_cntrl0.ISS.Mem_Data 31693 0.00% 0.00% +system.ruby.l2_cntrl0.IS.Mem_Data 15882 0.00% 0.00% +system.ruby.l2_cntrl0.IM.Mem_Data 126538 0.00% 0.00% +system.ruby.l2_cntrl0.SS_MB.L1_GETS 134 0.00% 0.00% +system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 44563 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.L1_GETS 49 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 1740110 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IIB.L1_PUTX 1 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IIB.WB_Data 45078 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IIB.WB_Data_clean 654 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IIB.Unblock 94 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IB.WB_Data 93 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IB.WB_Data_clean 1 0.00% 0.00% +system.ruby.l2_cntrl0.MT_SB.Unblock 45732 0.00% 0.00% +system.ruby.dma_cntrl0.ReadRequest 807 0.00% 0.00% +system.ruby.dma_cntrl0.WriteRequest 46736 0.00% 0.00% +system.ruby.dma_cntrl0.Data 807 0.00% 0.00% +system.ruby.dma_cntrl0.Ack 46736 0.00% 0.00% +system.ruby.dma_cntrl0.READY.ReadRequest 807 0.00% 0.00% +system.ruby.dma_cntrl0.READY.WriteRequest 46736 0.00% 0.00% +system.ruby.dma_cntrl0.BUSY_RD.Data 807 0.00% 0.00% +system.ruby.dma_cntrl0.BUSY_WR.Ack 46736 0.00% 0.00% +system.ruby.dir_cntrl0.Fetch 174113 0.00% 0.00% +system.ruby.dir_cntrl0.Data 96559 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 174561 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 141264 0.00% 0.00% +system.ruby.dir_cntrl0.DMA_READ 807 0.00% 0.00% +system.ruby.dir_cntrl0.DMA_WRITE 46736 0.00% 0.00% +system.ruby.dir_cntrl0.CleanReplacement 13031 0.00% 0.00% +system.ruby.dir_cntrl0.I.Fetch 174113 0.00% 0.00% +system.ruby.dir_cntrl0.I.DMA_READ 448 0.00% 0.00% +system.ruby.dir_cntrl0.I.DMA_WRITE 44705 0.00% 0.00% +system.ruby.dir_cntrl0.ID.Memory_Data 448 0.00% 0.00% +system.ruby.dir_cntrl0.ID_W.Memory_Ack 44705 0.00% 0.00% +system.ruby.dir_cntrl0.M.Data 94169 0.00% 0.00% +system.ruby.dir_cntrl0.M.DMA_READ 359 0.00% 0.00% +system.ruby.dir_cntrl0.M.DMA_WRITE 2031 0.00% 0.00% +system.ruby.dir_cntrl0.M.CleanReplacement 13031 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 174113 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 94169 0.00% 0.00% +system.ruby.dir_cntrl0.M_DRD.Data 359 0.00% 0.00% +system.ruby.dir_cntrl0.M_DRDI.Memory_Ack 359 0.00% 0.00% +system.ruby.dir_cntrl0.M_DWR.Data 2031 0.00% 0.00% +system.ruby.dir_cntrl0.M_DWRI.Memory_Ack 2031 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index f1500ba2f..e884e1c2d 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,155 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.137889 # Number of seconds simulated -sim_ticks 5137889173500 # Number of ticks simulated -final_tick 5137889173500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.137942 # Number of seconds simulated +sim_ticks 5137941673500 # Number of ticks simulated +final_tick 5137941673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239672 # Simulator instruction rate (inst/s) -host_op_rate 476391 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5046842796 # Simulator tick rate (ticks/s) -host_mem_usage 957396 # Number of bytes of host memory used -host_seconds 1018.04 # Real time elapsed on the host -sim_insts 243995320 # Number of instructions simulated -sim_ops 484985266 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2475904 # Number of bytes read from this memory +host_inst_rate 248874 # Simulator instruction rate (inst/s) +host_op_rate 494699 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5246911955 # Simulator tick rate (ticks/s) +host_mem_usage 994832 # Number of bytes of host memory used +host_seconds 979.23 # Real time elapsed on the host +sim_insts 243705182 # Number of instructions simulated +sim_ops 484425104 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2466368 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 403712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5648960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 122048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1730432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 426944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5894144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1789248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1408 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 439808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2919040 # Number of bytes read from this memory -system.physmem.bytes_read::total 13741824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 403712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 122048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 439808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 965568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9081216 # Number of bytes written to this memory -system.physmem.bytes_written::total 9081216 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38686 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu2.inst 385728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2633280 # Number of bytes read from this memory +system.physmem.bytes_read::total 13744640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 426944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 385728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 959872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9091584 # Number of bytes written to this memory +system.physmem.bytes_written::total 9091584 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38537 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6308 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 88265 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1907 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 27038 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 25 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6671 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 92096 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2300 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 27957 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 22 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6872 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 45610 # Number of read requests responded to by this memory -system.physmem.num_reads::total 214716 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141894 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141894 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 481891 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.inst 6027 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41145 # Number of read requests responded to by this memory +system.physmem.num_reads::total 214760 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 142056 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142056 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 480030 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 78575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1099471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 23755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 336798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 311 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 83096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1147180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 28650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 348242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 274 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 85601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 568140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2674605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 78575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 23755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 85601 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 187931 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1767499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1767499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1767499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 481891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 75074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 512517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2675126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 83096 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 28650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 75074 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 186820 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1769499 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1769499 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1769499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 480030 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 78575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1099471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 23755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 336798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 83096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1147180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 28650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 348242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 274 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 85601 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 568140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4442104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 101962 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 77214 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 101962 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 77214 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 6525568 # Total number of bytes read from memory -system.physmem.bytesWritten 4941696 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 6525568 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 4941696 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 66 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 761 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6400 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6366 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 5890 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6159 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 5804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6034 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 5639 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6376 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 6508 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6377 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6998 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6828 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5214 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4748 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5235 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5043 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4974 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4413 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4576 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4071 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4483 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4133 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4579 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5113 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5461 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5171 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry -system.physmem.totGap 5136889044500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 101962 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 77214 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 78859 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1511 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1094 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 669 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 498 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 509 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 487 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.bw_total::cpu2.inst 75074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 512517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4444625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 100936 # Number of read requests accepted +system.physmem.writeReqs 78380 # Number of write requests accepted +system.physmem.readBursts 100936 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 78380 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6458816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1088 # Total number of bytes read from write queue +system.physmem.bytesWritten 5015040 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6459904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5016320 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 17 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 699 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5898 # Per bank write bursts +system.physmem.perBankRdBursts::1 6403 # Per bank write bursts +system.physmem.perBankRdBursts::2 6411 # Per bank write bursts +system.physmem.perBankRdBursts::3 6523 # Per bank write bursts +system.physmem.perBankRdBursts::4 6306 # Per bank write bursts +system.physmem.perBankRdBursts::5 6840 # Per bank write bursts +system.physmem.perBankRdBursts::6 6199 # Per bank write bursts +system.physmem.perBankRdBursts::7 6896 # Per bank write bursts +system.physmem.perBankRdBursts::8 5528 # Per bank write bursts +system.physmem.perBankRdBursts::9 5898 # Per bank write bursts +system.physmem.perBankRdBursts::10 6128 # Per bank write bursts +system.physmem.perBankRdBursts::11 6570 # Per bank write bursts +system.physmem.perBankRdBursts::12 6317 # Per bank write bursts +system.physmem.perBankRdBursts::13 6334 # Per bank write bursts +system.physmem.perBankRdBursts::14 6542 # Per bank write bursts +system.physmem.perBankRdBursts::15 6126 # Per bank write bursts +system.physmem.perBankWrBursts::0 4721 # Per bank write bursts +system.physmem.perBankWrBursts::1 4902 # Per bank write bursts +system.physmem.perBankWrBursts::2 4923 # Per bank write bursts +system.physmem.perBankWrBursts::3 5159 # Per bank write bursts +system.physmem.perBankWrBursts::4 5192 # Per bank write bursts +system.physmem.perBankWrBursts::5 5457 # Per bank write bursts +system.physmem.perBankWrBursts::6 4843 # Per bank write bursts +system.physmem.perBankWrBursts::7 5797 # Per bank write bursts +system.physmem.perBankWrBursts::8 4085 # Per bank write bursts +system.physmem.perBankWrBursts::9 4367 # Per bank write bursts +system.physmem.perBankWrBursts::10 4807 # Per bank write bursts +system.physmem.perBankWrBursts::11 4903 # Per bank write bursts +system.physmem.perBankWrBursts::12 4884 # Per bank write bursts +system.physmem.perBankWrBursts::13 4699 # Per bank write bursts +system.physmem.perBankWrBursts::14 5116 # Per bank write bursts +system.physmem.perBankWrBursts::15 4505 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 5136941479000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 100936 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 78380 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 75816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1647 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 976 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 667 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 539 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 430 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -161,534 +163,549 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 32753 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 349.964889 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.240831 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1180.348858 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14687 44.84% 44.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5019 15.32% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3032 9.26% 69.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2021 6.17% 75.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1281 3.91% 79.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1132 3.46% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 832 2.54% 85.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 693 2.12% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 503 1.54% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 527 1.61% 90.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 287 0.88% 91.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 266 0.81% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 203 0.62% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 195 0.60% 93.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 197 0.60% 94.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 238 0.73% 94.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 149 0.45% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 112 0.34% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 86 0.26% 96.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 79 0.24% 96.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 89 0.27% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 70 0.21% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 290 0.89% 97.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 98 0.30% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 63 0.19% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 48 0.15% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 49 0.15% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 27 0.08% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 22 0.07% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 16 0.05% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 16 0.05% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 11 0.03% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 5 0.02% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 13 0.04% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 5 0.02% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 10 0.03% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 7 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 5 0.02% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 7 0.02% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 3 0.01% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 3 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 3 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 3 0.01% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.02% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.01% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 2 0.01% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 4 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 3 0.01% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 4 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 4 0.01% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 7 0.02% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 4 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 6 0.02% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 2 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 5 0.02% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 2 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 9 0.03% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 3 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 2 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 2 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 2 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 2 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 3 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 2 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 5 0.02% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 2 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 3 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 4 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 3 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 2 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 48 0.15% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 2 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 2 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 2 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 13 0.04% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 3 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 7 0.02% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 2 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 3 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 3 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 3 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 3 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 2 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 3 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 9 0.03% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 10 0.03% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 15 0.05% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 34 0.10% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17667 2 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 32753 # Bytes accessed per row activation -system.physmem.totQLat 1954361749 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 3940385499 # Sum of mem lat for all requests -system.physmem.totBusLat 509480000 # Total cycles spent in databus access -system.physmem.totBankLat 1476543750 # Total cycles spent in bank access -system.physmem.avgQLat 19179.97 # Average queueing delay per request -system.physmem.avgBankLat 14490.69 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38670.66 # Average memory access latency -system.physmem.avgRdBW 1.27 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.96 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1.27 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.96 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 3240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 35607 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.217991 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.094116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1121.662575 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 16547 46.47% 46.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5535 15.54% 62.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3551 9.97% 71.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2213 6.22% 78.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1334 3.75% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1101 3.09% 85.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 807 2.27% 87.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 584 1.64% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 515 1.45% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 517 1.45% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 309 0.87% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 309 0.87% 93.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 205 0.58% 94.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 200 0.56% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 177 0.50% 95.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 272 0.76% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 139 0.39% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 84 0.24% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 95 0.27% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 94 0.26% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 81 0.23% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 178 0.50% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 83 0.23% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 58 0.16% 98.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 45 0.13% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 38 0.11% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 29 0.08% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 19 0.05% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 15 0.04% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 14 0.04% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 11 0.03% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 10 0.03% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 8 0.02% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 10 0.03% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 8 0.02% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 6 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 6 0.02% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 5 0.01% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 6 0.02% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 3 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 5 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 4 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 4 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 6 0.02% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 5 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 2 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 8 0.02% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 5 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 2 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 3 0.01% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 8 0.02% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 3 0.01% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 4 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 5 0.01% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 6 0.02% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 10 0.03% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 6 0.02% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 3 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 4 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 4 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 4 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 2 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 2 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 3 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 3 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 2 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 2 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 4 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 2 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 3 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 2 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 3 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 3 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 20 0.06% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 2 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 2 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 4 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 2 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 6 0.02% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 2 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 2 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 2 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 2 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 3 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 2 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 2 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 2 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 2 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 2 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 3 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 2 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 2 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 2 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 3 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 2 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 2 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 3 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 12 0.03% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 3 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 7 0.02% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 2 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 6 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 10 0.03% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 5 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 3 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 4 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 3 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 5 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 9 0.03% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 8 0.02% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 29 0.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 35607 # Bytes accessed per row activation +system.physmem.totQLat 2741683498 # Total ticks spent queuing +system.physmem.totMemAccLat 4643457248 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 504595000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1397178750 # Total ticks spent accessing banks +system.physmem.avgQLat 27167.17 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13844.56 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 46011.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.98 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.12 # Average write queue length over time -system.physmem.readRowHits 89443 # Number of row buffer hits during reads -system.physmem.writeRowHits 56909 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.70 # Row buffer hit rate for writes -system.physmem.avgGap 28669515.14 # Average gap between requests -system.membus.throughput 6421183 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 424471 # Transaction distribution -system.membus.trans_dist::ReadResp 424470 # Transaction distribution -system.membus.trans_dist::WriteReq 6959 # Transaction distribution -system.membus.trans_dist::WriteResp 6959 # Transaction distribution -system.membus.trans_dist::Writeback 77214 # Transaction distribution -system.membus.trans_dist::UpgradeReq 768 # Transaction distribution -system.membus.trans_dist::UpgradeResp 768 # Transaction distribution -system.membus.trans_dist::ReadExReq 79729 # Transaction distribution -system.membus.trans_dist::ReadExResp 79729 # Transaction distribution -system.membus.trans_dist::MessageReq 903 # Transaction distribution -system.membus.trans_dist::MessageResp 903 # Transaction distribution +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.11 # Average write queue length when enqueuing +system.physmem.readRowHits 85240 # Number of row buffer hits during reads +system.physmem.writeRowHits 58432 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.46 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.55 # Row buffer hit rate for writes +system.physmem.avgGap 28647423.98 # Average gap between requests +system.physmem.pageHitRate 80.13 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.12 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6427951 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 423177 # Transaction distribution +system.membus.trans_dist::ReadResp 423176 # Transaction distribution +system.membus.trans_dist::WriteReq 6474 # Transaction distribution +system.membus.trans_dist::WriteResp 6474 # Transaction distribution +system.membus.trans_dist::Writeback 78380 # Transaction distribution +system.membus.trans_dist::UpgradeReq 714 # Transaction distribution +system.membus.trans_dist::UpgradeResp 714 # Transaction distribution +system.membus.trans_dist::ReadExReq 80216 # Transaction distribution +system.membus.trans_dist::ReadExResp 80216 # Transaction distribution +system.membus.trans_dist::MessageReq 892 # Transaction distribution +system.membus.trans_dist::MessageResp 892 # Transaction distribution system.membus.trans_dist::BadAddressError 1 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1806 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 1806 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312334 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497960 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 218608 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1784 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 1784 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 310648 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497624 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 207711 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1028904 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 68108 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 68108 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1098818 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3612 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 3612 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 160445 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995917 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8655808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9812170 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2811456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2811456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 12627238 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32732190 # Total data (bytes) -system.membus.snoop_data_through_bus 259136 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 164966500 # Layer occupancy (ticks) +system.membus.pkt_count_system.l2c.mem_side::total 1015985 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 78748 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 78748 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1096517 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 3568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159467 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995245 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8228608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9383320 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 3247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 12634504 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32719620 # Total data (bytes) +system.membus.snoop_data_through_bus 306816 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 163512000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315386000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315210000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1806000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1784000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 820026249 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 830204748 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 903000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 892000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1636763940 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1595294481 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 218001500 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 252511249 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 103793 # number of replacements -system.l2c.tags.tagsinuse 64823.461690 # Cycle average of tags in use -system.l2c.tags.total_refs 3658744 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167885 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.793156 # Average number of references to valid blocks. +system.l2c.tags.replacements 103855 # number of replacements +system.l2c.tags.tagsinuse 64822.347448 # Cycle average of tags in use +system.l2c.tags.total_refs 3646219 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 167877 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.719586 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51284.674060 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121869 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1299.911935 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4544.856644 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 221.437918 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1509.586927 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.216404 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003202 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1337.967786 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4616.684944 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.782542 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51292.264352 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121895 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1278.615227 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4499.945934 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 292.458405 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1505.357985 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.212632 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003182 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1370.507166 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4576.860668 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.782658 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.019835 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.069349 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003379 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023034 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000125 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.019510 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.068664 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004463 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.022970 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000095 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.020416 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.070445 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989128 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 22091 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 11658 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 334413 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 510225 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10171 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5452 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 152259 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 227659 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 50814 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 10913 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 351942 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 566551 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2254148 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu2.inst 0.020912 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.069837 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989111 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 19693 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10326 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 346717 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 513928 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10907 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5932 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 155624 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 223811 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 47020 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 9087 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 331652 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 566093 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2240790 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1543420 # number of Writeback hits -system.l2c.Writeback_hits::total 1543420 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 115 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 56 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 83 # number of UpgradeReq hits +system.l2c.Writeback_hits::writebacks 1542501 # number of Writeback hits +system.l2c.Writeback_hits::total 1542501 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 139 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 58 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 57 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 254 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 69377 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 36565 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 61899 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 167841 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22091 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 11660 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 334413 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 579602 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10171 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5452 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 152259 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 264224 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 50814 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 10913 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 351942 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 628450 # number of demand (read+write) hits -system.l2c.demand_hits::total 2421991 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22091 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 11660 # number of overall hits -system.l2c.overall_hits::cpu0.inst 334413 # number of overall hits -system.l2c.overall_hits::cpu0.data 579602 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10171 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5452 # number of overall hits -system.l2c.overall_hits::cpu1.inst 152259 # number of overall hits -system.l2c.overall_hits::cpu1.data 264224 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 50814 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 10913 # number of overall hits -system.l2c.overall_hits::cpu2.inst 351942 # number of overall hits -system.l2c.overall_hits::cpu2.data 628450 # number of overall hits -system.l2c.overall_hits::total 2421991 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 70841 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 36082 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 59675 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 166598 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 19693 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 10328 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 346717 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 584769 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10907 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5932 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 155624 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 259893 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 47020 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 9087 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 331652 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 625768 # number of demand (read+write) hits +system.l2c.demand_hits::total 2407390 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 19693 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 10328 # number of overall hits +system.l2c.overall_hits::cpu0.inst 346717 # number of overall hits +system.l2c.overall_hits::cpu0.data 584769 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 10907 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5932 # number of overall hits +system.l2c.overall_hits::cpu1.inst 155624 # number of overall hits +system.l2c.overall_hits::cpu1.data 259893 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 47020 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 9087 # number of overall hits +system.l2c.overall_hits::cpu2.inst 331652 # number of overall hits +system.l2c.overall_hits::cpu2.data 625768 # number of overall hits +system.l2c.overall_hits::total 2407390 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6308 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 16059 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1908 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3914 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 25 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6671 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 16268 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2301 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4539 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 22 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 6873 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 12824 # number of ReadReq misses -system.l2c.ReadReq_misses::total 47916 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 775 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 221 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 356 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1352 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 72577 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 23336 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 33144 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 129057 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu2.inst 6029 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 11901 # number of ReadReq misses +system.l2c.ReadReq_misses::total 47736 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 761 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 281 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 269 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1311 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 76320 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 23649 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 29451 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 129420 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6308 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 88636 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1908 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 27250 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 25 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6671 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 92588 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2301 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 28188 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 22 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 6873 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 45968 # number of demand (read+write) misses -system.l2c.demand_misses::total 176973 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 6029 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 41352 # number of demand (read+write) misses +system.l2c.demand_misses::total 177156 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6308 # number of overall misses -system.l2c.overall_misses::cpu0.data 88636 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1908 # number of overall misses -system.l2c.overall_misses::cpu1.data 27250 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 25 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6671 # number of overall misses +system.l2c.overall_misses::cpu0.data 92588 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2301 # number of overall misses +system.l2c.overall_misses::cpu1.data 28188 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 22 # number of overall misses system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu2.inst 6873 # number of overall misses -system.l2c.overall_misses::cpu2.data 45968 # number of overall misses -system.l2c.overall_misses::total 176973 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 145483750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 305732245 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2908500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.itb.walker 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 619386243 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1056307494 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2129906982 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2658895 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 4530318 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 7189213 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1598265396 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 2458778359 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 4057043755 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 145483750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1903997641 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 2908500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.itb.walker 88750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 619386243 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 3515085853 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 6186950737 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 145483750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1903997641 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 2908500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.itb.walker 88750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 619386243 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3515085853 # number of overall miss cycles -system.l2c.overall_miss_latency::total 6186950737 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 22091 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 11662 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 340721 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 526284 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 10171 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5452 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 154167 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 231573 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 50839 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 10914 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 358815 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 579375 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2302064 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::cpu2.inst 6029 # number of overall misses +system.l2c.overall_misses::cpu2.data 41352 # number of overall misses +system.l2c.overall_misses::total 177156 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 178484750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 352246744 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2002250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 74500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 488673998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 943243246 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1964725488 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 3587383 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 3136875 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 6724258 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1676320610 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 2179701143 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 3856021753 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 178484750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2028567354 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 2002250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 74500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 488673998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 3122944389 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 5820747241 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 178484750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2028567354 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 2002250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 74500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 488673998 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 3122944389 # number of overall miss cycles +system.l2c.overall_miss_latency::total 5820747241 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 19693 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 10330 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 353388 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 530196 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 10907 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5932 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 157925 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 228350 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 47042 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 9088 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 337681 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 577994 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2288526 # number of ReadReq accesses(hits+misses) system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses) system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1543420 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1543420 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 890 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 277 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 439 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1606 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 141954 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 59901 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 95043 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296898 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 22091 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 11664 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 340721 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 668238 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 10171 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5452 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 154167 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 291474 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 50839 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 10914 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 358815 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 674418 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2598964 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 22091 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 11664 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 340721 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 668238 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 10171 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5452 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 154167 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 291474 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 50839 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 10914 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 358815 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 674418 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2598964 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000343 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018514 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.030514 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.012376 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.016902 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000492 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000092 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.019155 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.022134 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020814 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.870787 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.797834 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.810934 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.841843 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.511271 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.389576 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.348726 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.434685 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000343 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018514 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.132641 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.012376 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.093490 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000492 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.itb.walker 0.000092 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.019155 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.068160 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.068094 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000343 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018514 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.132641 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.012376 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.093490 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000492 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.itb.walker 0.000092 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.019155 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.068160 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.068094 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76249.344864 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 78112.479561 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 116340 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 88750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 90118.760803 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 82369.580006 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 44450.851114 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12031.199095 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12725.612360 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5317.465237 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68489.261056 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74184.719979 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 31436.061237 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76249.344864 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 69871.473064 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 116340 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 90118.760803 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 76468.105051 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 34959.856797 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76249.344864 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 69871.473064 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 116340 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 90118.760803 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 76468.105051 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 34959.856797 # average overall miss latency +system.l2c.Writeback_accesses::writebacks 1542501 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1542501 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 900 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 339 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 326 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1565 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 147161 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 59731 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 89126 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296018 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 19693 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 10332 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 353388 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 677357 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 10907 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5932 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 157925 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 288081 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 47042 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 9088 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 337681 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 667120 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2584546 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 19693 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 10332 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 353388 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 677357 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 10907 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5932 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 157925 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 288081 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 47042 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 9088 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 337681 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 667120 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2584546 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000387 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018877 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.030683 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.014570 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.019877 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000468 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000110 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.017854 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.020590 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.020859 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.845556 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.828909 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.825153 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.837700 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.518616 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.395925 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.330442 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.437203 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000387 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018877 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.136690 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.014570 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.097847 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000468 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.000110 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.017854 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.061986 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.068544 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000387 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018877 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.136690 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.014570 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.097847 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000468 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.000110 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.017854 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.061986 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.068544 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77568.339852 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 77604.482045 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 91011.363636 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 74500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 81053.905789 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 79257.478027 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 41158.150830 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12766.487544 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11661.245353 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5129.106026 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70883.361241 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74011.108044 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 29794.635705 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 77568.339852 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 71965.636228 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 91011.363636 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 74500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 81053.905789 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 75520.999927 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 32856.619256 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 77568.339852 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 71965.636228 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 91011.363636 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 74500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 81053.905789 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 75520.999927 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 32856.619256 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -697,131 +714,131 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 95227 # number of writebacks -system.l2c.writebacks::total 95227 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.inst 1908 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 3914 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 25 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 95389 # number of writebacks +system.l2c.writebacks::total 95389 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu2.inst 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu1.inst 2301 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4539 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 22 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 6872 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 12824 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25544 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 221 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 356 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 577 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 23336 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 33144 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 56480 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1908 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 27250 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 25 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 6027 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 11901 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 24791 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 281 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 269 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 550 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 23649 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 29451 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 53100 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2301 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 28188 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 22 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 6872 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 45968 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 82024 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1908 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 27250 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 25 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 6027 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 41352 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 77891 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2301 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 28188 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 22 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 6872 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 45968 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 82024 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 121373750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 256053755 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2594000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 532537507 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 893917000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1806552262 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 2360218 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 3787353 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 6147571 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1304557104 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2042074099 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 3346631203 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 121373750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1560610859 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2594000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 532537507 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2935991099 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5153183465 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 121373750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1560610859 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2594000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 532537507 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2935991099 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5153183465 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28189792500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30481780500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 58671573000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 471155500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 768000500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1239156000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28660948000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31249781000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 59910729000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012376 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016902 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000492 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000092 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.019152 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.022134 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.011096 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.797834 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.810934 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.359278 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.389576 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.348726 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.190234 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012376 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.093490 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000492 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000092 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.019152 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.068160 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.031560 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012376 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.093490 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000492 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000092 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.019152 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.068160 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.031560 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63613.076520 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65419.968063 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 103760 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 77493.816502 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 69706.565814 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 70723.154635 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10679.719457 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10638.632022 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10654.369151 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55903.201234 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61612.180153 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 59253.385322 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63613.076520 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57270.123266 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 103760 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 77493.816502 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63870.324987 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 62825.312896 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63613.076520 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57270.123266 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 103760 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 77493.816502 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63870.324987 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62825.312896 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu2.inst 6027 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 41352 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 77891 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 149580250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 295478756 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 1731250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 413107752 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 794213750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1654174258 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3410269 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 2847765 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 6258034 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1378867890 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1809513813 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 3188381703 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 149580250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1674346646 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 1731250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 413107752 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2603727563 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 4842555961 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 149580250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1674346646 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 1731250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 413107752 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2603727563 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 4842555961 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28165267500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30426261500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 58591529000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 495358500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 671313500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1166672000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28660626000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31097575000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59758201000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014570 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019877 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000468 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000110 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.017848 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.020590 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.010833 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.828909 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.825153 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.351438 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.395925 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.330442 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.179381 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014570 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.097847 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000468 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000110 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.017848 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.061986 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.030137 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014570 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.097847 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000468 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000110 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.017848 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.061986 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.030137 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65006.627553 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65097.765147 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 78693.181818 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 68542.849179 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66735.043274 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 66724.789561 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12136.188612 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10586.486989 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11378.243636 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58305.547380 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61441.506672 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60044.853164 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65006.627553 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59399.270824 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 78693.181818 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 68542.849179 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62964.972988 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62170.930672 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65006.627553 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59399.270824 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 78693.181818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 68542.849179 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62964.972988 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62170.930672 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -832,39 +849,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47570 # number of replacements -system.iocache.tags.tagsinuse 0.094174 # Cycle average of tags in use +system.iocache.tags.replacements 47575 # number of replacements +system.iocache.tags.tagsinuse 0.094274 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47586 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000166705009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.094174 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005886 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005886 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses -system.iocache.ReadReq_misses::total 905 # number of ReadReq misses +system.iocache.tags.warmup_cycle 5000200819009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.094274 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005892 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005892 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses +system.iocache.ReadReq_misses::total 910 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses -system.iocache.demand_misses::total 47625 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses -system.iocache.overall_misses::total 47625 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131928771 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 131928771 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5225930177 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5225930177 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 5357858948 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5357858948 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 5357858948 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5357858948 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses +system.iocache.demand_misses::total 47630 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses +system.iocache.overall_misses::total 47630 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129801048 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 129801048 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6845673540 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6845673540 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6975474588 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6975474588 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6975474588 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6975474588 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -873,56 +890,56 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145777.647514 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 145777.647514 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 111856.382213 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 111856.382213 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 112500.975286 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 112500.975286 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 112500.975286 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 112500.975286 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 75733 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142638.514286 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 142638.514286 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 146525.546661 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 146525.546661 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 146451.282553 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 146451.282553 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 146451.282553 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 146451.282553 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 105453 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7002 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 6453 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.815910 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 16.341702 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 739 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 23440 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 23440 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 24179 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 24179 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 24179 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 24179 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93470771 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 93470771 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4006299177 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4006299177 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4099769948 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4099769948 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4099769948 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4099769948 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.816575 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.816575 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.501712 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.501712 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.507696 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.507696 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.507696 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.507696 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 126482.775372 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 126482.775372 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 170917.200384 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 170917.200384 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 169559.119401 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 169559.119401 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 169559.119401 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 169559.119401 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 724 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 724 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 27280 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 27280 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 28004 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 28004 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 28004 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 28004 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92126548 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 92126548 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 5426189542 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5426189542 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 5518316090 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5518316090 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 5518316090 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5518316090 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.795604 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.795604 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.583904 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.583904 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.587949 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.587949 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.587949 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.587949 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127246.613260 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 127246.613260 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 198907.241276 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 198907.241276 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 197054.566848 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 197054.566848 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 197054.566848 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 197054.566848 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -936,459 +953,459 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52280174 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1811511 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1810976 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 6959 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 6959 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 914733 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 716 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 716 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 178384 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 154949 # Transaction distribution +system.toL2Bus.throughput 52188015 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1787129 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1786595 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 6474 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 6474 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 905502 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 665 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 665 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 176137 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 148862 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1025990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3658453 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 36523 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 129481 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4850447 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32830848 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 121529738 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 130928 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 488080 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 154979594 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 268493674 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 116064 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5106548110 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 991248 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3625702 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34347 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 125379 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4776676 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31718784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120252184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 120160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 463592 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 152554720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 268001344 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 137632 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5049278590 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 945000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 882000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2311338505 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2232669307 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4765806692 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4714355905 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 20170721 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 19343965 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 68576287 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 67521559 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1274820 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 150850 # Transaction distribution -system.iobus.trans_dist::ReadResp 150850 # Transaction distribution -system.iobus.trans_dist::WriteReq 29496 # Transaction distribution -system.iobus.trans_dist::WriteResp 29496 # Transaction distribution -system.iobus.trans_dist::MessageReq 903 # Transaction distribution -system.iobus.trans_dist::MessageResp 903 # Transaction distribution +system.iobus.throughput 1276093 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 150466 # Transaction distribution +system.iobus.trans_dist::ReadResp 150466 # Transaction distribution +system.iobus.trans_dist::WriteReq 32862 # Transaction distribution +system.iobus.trans_dist::WriteResp 32862 # Transaction distribution +system.iobus.trans_dist::MessageReq 892 # Transaction distribution +system.iobus.trans_dist::MessageResp 892 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5804 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4556 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 46 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287488 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 552 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 500 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15072 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 14980 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 312334 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 48358 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 48358 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1806 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1806 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 362498 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 310648 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 56008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 56008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1784 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1784 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 368440 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3277 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2572 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 23 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 17 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143744 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143595 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1000 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7490 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 160445 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1536536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1536536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3612 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3612 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1700593 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6549885 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2124548 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 159467 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1782176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1782176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1945211 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6556491 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2113460 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4801000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 3772000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 39000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 143745000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 143596000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 436000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 394000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11266000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11170000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 213288448 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 248070339 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 306278000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 305066000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 29307500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 32957751 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 903000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 892000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.numCycles 1216464910 # number of cpu cycles simulated +system.cpu0.numCycles 1184263733 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 71961421 # Number of instructions committed -system.cpu0.committedOps 146368954 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 134434152 # Number of integer alu accesses +system.cpu0.committedInsts 72124506 # Number of instructions committed +system.cpu0.committedOps 146682326 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 134713165 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 983451 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14191112 # number of instructions that are conditional controls -system.cpu0.num_int_insts 134434152 # number of integer instructions +system.cpu0.num_func_calls 981373 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14229217 # number of instructions that are conditional controls +system.cpu0.num_int_insts 134713165 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 247103574 # number of times the integer registers were read -system.cpu0.num_int_register_writes 115380288 # number of times the integer registers were written +system.cpu0.num_int_register_reads 247622256 # number of times the integer registers were read +system.cpu0.num_int_register_writes 115606613 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83614520 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55784493 # number of times the CC registers were written -system.cpu0.num_mem_refs 14023782 # number of memory refs -system.cpu0.num_load_insts 10248970 # Number of load instructions -system.cpu0.num_store_insts 3774812 # Number of store instructions -system.cpu0.num_idle_cycles 1155422884.085227 # Number of idle cycles -system.cpu0.num_busy_cycles 61042025.914772 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050180 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949820 # Percentage of idle cycles +system.cpu0.num_cc_register_reads 83816060 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55907358 # number of times the CC registers were written +system.cpu0.num_mem_refs 14049102 # number of memory refs +system.cpu0.num_load_insts 10253492 # Number of load instructions +system.cpu0.num_store_insts 3795610 # Number of store instructions +system.cpu0.num_idle_cycles 1123870108.492543 # Number of idle cycles +system.cpu0.num_busy_cycles 60393624.507457 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050997 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949003 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 853207 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.801369 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129244758 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 853719 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 151.390279 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147441059000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 310.509377 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 127.091120 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 73.200872 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.606464 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.248225 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.142970 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997659 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 87593978 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 38906796 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2743984 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129244758 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 87593978 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 38906796 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2743984 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 129244758 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 87593978 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 38906796 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2743984 # number of overall hits -system.cpu0.icache.overall_hits::total 129244758 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 340722 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 154167 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 378624 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 873513 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 340722 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 154167 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 378624 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 873513 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 340722 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 154167 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 378624 # number of overall misses -system.cpu0.icache.overall_misses::total 873513 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2138351750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5548047899 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7686399649 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2138351750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5548047899 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7686399649 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2138351750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5548047899 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7686399649 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 87934700 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39060963 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3122608 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 130118271 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 87934700 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39060963 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3122608 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 130118271 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 87934700 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39060963 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3122608 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 130118271 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003875 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.003947 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.121252 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006713 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003875 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.003947 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121252 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006713 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003875 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.003947 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.121252 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006713 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13870.359740 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14653.186008 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8799.410712 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13870.359740 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14653.186008 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8799.410712 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13870.359740 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14653.186008 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8799.410712 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6480 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 848510 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.789516 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 129618382 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 849022 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 152.667872 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147463418500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 302.993641 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 130.368033 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 77.427843 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.591784 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.254625 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.151226 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997636 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 87771297 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 39145197 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2701888 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 129618382 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 87771297 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 39145197 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2701888 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 129618382 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 87771297 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 39145197 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2701888 # number of overall hits +system.cpu0.icache.overall_hits::total 129618382 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 353389 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 157925 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 356099 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 867413 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 353389 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 157925 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 356099 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 867413 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 353389 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 157925 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 356099 # number of overall misses +system.cpu0.icache.overall_misses::total 867413 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2216316250 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5093590204 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7309906454 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2216316250 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5093590204 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7309906454 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2216316250 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5093590204 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7309906454 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 88124686 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 39303122 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3057987 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 130485795 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 88124686 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 39303122 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3057987 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 130485795 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 88124686 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 39303122 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3057987 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 130485795 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004010 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004018 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116449 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006648 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004010 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004018 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116449 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006648 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004010 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004018 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116449 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006648 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14033.979737 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14303.859893 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8427.250288 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14033.979737 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14303.859893 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8427.250288 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14033.979737 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14303.859893 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8427.250288 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4049 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 241 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 236 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.887967 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.156780 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 19783 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 19783 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 19783 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 19783 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 19783 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 19783 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 154167 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 358841 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 513008 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 154167 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 358841 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 513008 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 154167 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 358841 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 513008 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1829084250 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4581098483 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6410182733 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1829084250 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4581098483 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6410182733 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1829084250 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4581098483 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6410182733 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.003947 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.114917 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003943 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.003947 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.114917 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.003943 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.003947 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.114917 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.003943 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11864.304618 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12766.374196 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12495.288052 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11864.304618 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12766.374196 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12495.288052 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11864.304618 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12766.374196 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12495.288052 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 18382 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 18382 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 18382 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 18382 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 18382 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 18382 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 157925 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 337717 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 495642 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 157925 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 337717 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 495642 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 157925 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 337717 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 495642 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1899637750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4221033432 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6120671182 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1899637750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4221033432 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6120671182 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1899637750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4221033432 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6120671182 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004018 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110438 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003798 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004018 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110438 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.003798 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004018 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110438 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.003798 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12028.733576 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12498.729504 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12348.976039 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12028.733576 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12498.729504 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12348.976039 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12028.733576 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12498.729504 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12348.976039 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1633606 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999469 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19601664 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1634118 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 11.995256 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1632030 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997838 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19577218 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1632542 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.991862 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 202.875385 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 302.501214 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.622869 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.396241 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.590823 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012935 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5120812 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2495791 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 3903609 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11520212 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3628684 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1642970 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2808111 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8079765 # number of WriteReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8749496 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4138761 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6711720 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19599977 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8749496 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4138761 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6711720 # number of overall hits -system.cpu0.dcache.overall_hits::total 19599977 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 526284 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 231573 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 944815 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1702672 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 142844 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 60178 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 112298 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 315320 # number of WriteReq misses -system.cpu0.dcache.demand_misses::cpu0.data 669128 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 291751 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1057113 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2017992 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 669128 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 291751 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1057113 # number of overall misses -system.cpu0.dcache.overall_misses::total 2017992 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3286416755 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15267347781 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 18553764536 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2165300822 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3604529651 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5769830473 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 5451717577 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 18871877432 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 24323595009 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 5451717577 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 18871877432 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 24323595009 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5647096 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2727364 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4848424 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13222884 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3771528 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1703148 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2920409 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8395085 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9418624 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4430512 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7768833 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21617969 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9418624 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4430512 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7768833 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21617969 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.093196 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.084907 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.194871 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.128767 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.037874 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.035333 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.038453 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.037560 # miss rate for WriteReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.071043 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065850 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.136071 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.093348 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071043 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065850 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.136071 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.093348 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14191.709547 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16159.086997 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10896.851852 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35981.601615 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32097.897122 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18298.333353 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18686.200140 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17852.280155 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 12053.365429 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18686.200140 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17852.280155 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12053.365429 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 177204 # number of cycles access was blocked +system.cpu0.dcache.tags.occ_blocks::cpu0.data 205.523243 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 299.707974 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.766620 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.401413 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.585367 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013216 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5112635 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2556554 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 3831407 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11500596 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3643791 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1689050 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2742153 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8074994 # number of WriteReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8756426 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 4245604 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6573560 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19575590 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8756426 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 4245604 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6573560 # number of overall hits +system.cpu0.dcache.overall_hits::total 19575590 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 530196 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 228350 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 940486 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1699032 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 148061 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 60070 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 106578 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 314709 # number of WriteReq misses +system.cpu0.dcache.demand_misses::cpu0.data 678257 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 288420 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1047064 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2013741 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 678257 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 288420 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1047064 # number of overall misses +system.cpu0.dcache.overall_misses::total 2013741 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3284093256 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15033857981 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 18317951237 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2239487659 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3281341546 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5520829205 # number of WriteReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 5523580915 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 18315199527 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 23838780442 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 5523580915 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 18315199527 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 23838780442 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5642831 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 2784904 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4771893 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13199628 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3791852 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1749120 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2848731 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8389703 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9434683 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4534024 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7620624 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21589331 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9434683 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4534024 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7620624 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21589331 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.093959 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.081996 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.197089 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.128718 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.039047 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034343 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.037412 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.037511 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.071890 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.063612 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.137399 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.093275 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071890 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.063612 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.137399 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.093275 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14381.840403 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15985.201248 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10781.404492 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37281.299467 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30788.169660 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17542.647986 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19151.171607 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17491.958015 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 11838.056851 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19151.171607 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17491.958015 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11838.056851 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 171453 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 11696 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 11788 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.150821 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.544706 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1543420 # number of writebacks -system.cpu0.dcache.writebacks::total 1543420 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 365400 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 365400 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 16856 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 16856 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 382256 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 382256 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 382256 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 382256 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 231573 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 579415 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 810988 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 60178 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 95442 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 155620 # number of WriteReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 291751 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 674857 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 966608 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 291751 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 674857 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 966608 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2821426245 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8425862038 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11247288283 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2033592178 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3216384846 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5249977024 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4855018423 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11642246884 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16497265307 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4855018423 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11642246884 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16497265307 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30662990000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33250431500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63913421500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 506056500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 816755500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1322812000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31169046500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34067187000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65236233500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.084907 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.119506 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.061332 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035333 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032681 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018537 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065850 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.086867 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.044713 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065850 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086867 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.044713 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12183.744413 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14542.015719 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13868.624792 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33792.950547 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33699.889420 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33735.876006 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16640.965834 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17251.427908 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17067.172325 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16640.965834 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17251.427908 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17067.172325 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1542501 # number of writebacks +system.cpu0.dcache.writebacks::total 1542501 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 362466 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 362466 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17153 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 17153 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 379619 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 379619 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 379619 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 379619 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 228350 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 578020 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 806370 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 60070 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 89425 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 149495 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 288420 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 667445 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 955865 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 288420 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 667445 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 955865 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2826173744 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8314744809 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11140918553 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2108252341 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2905747700 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5014000041 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4934426085 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11220492509 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16154918594 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4934426085 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11220492509 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16154918594 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30636255000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33190282000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63826537000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 532271000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 712236000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1244507000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31168526000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33902518000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65071044000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.081996 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.121130 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.061090 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034343 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031391 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017819 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.063612 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.087584 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.044275 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063612 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087584 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.044275 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12376.499864 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14384.873895 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13816.137199 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35096.592992 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32493.684093 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33539.583538 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17108.474048 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16811.111790 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16900.837037 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17108.474048 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16811.111790 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16900.837037 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1399,306 +1416,306 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606006645 # number of cpu cycles simulated +system.cpu1.numCycles 2606010326 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35315213 # Number of instructions committed -system.cpu1.committedOps 68682433 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 63797816 # Number of integer alu accesses +system.cpu1.committedInsts 35502902 # Number of instructions committed +system.cpu1.committedOps 69019443 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64128875 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 457734 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6497995 # number of instructions that are conditional controls -system.cpu1.num_int_insts 63797816 # number of integer instructions +system.cpu1.num_func_calls 466888 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6511590 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64128875 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 117816925 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55078781 # number of times the integer registers were written +system.cpu1.num_int_register_reads 118555351 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55341107 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36195960 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26980721 # number of times the CC registers were written -system.cpu1.num_mem_refs 4621452 # number of memory refs -system.cpu1.num_load_insts 2916499 # Number of load instructions -system.cpu1.num_store_insts 1704953 # Number of store instructions -system.cpu1.num_idle_cycles 2477007170.096548 # Number of idle cycles -system.cpu1.num_busy_cycles 128999474.903452 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049501 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950499 # Percentage of idle cycles +system.cpu1.num_cc_register_reads 36337345 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27074895 # number of times the CC registers were written +system.cpu1.num_mem_refs 4724906 # number of memory refs +system.cpu1.num_load_insts 2973846 # Number of load instructions +system.cpu1.num_store_insts 1751060 # Number of store instructions +system.cpu1.num_idle_cycles 2477242501.972853 # Number of idle cycles +system.cpu1.num_busy_cycles 128767824.027147 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049412 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950588 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28832932 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28832932 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 311283 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26470595 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25835663 # Number of BTB hits +system.cpu2.branchPred.lookups 28668505 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28668505 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 293936 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26313496 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25716329 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.601369 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 539109 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 63758 # Number of incorrect RAS predictions. -system.cpu2.numCycles 156318365 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.730568 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 531231 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 59742 # Number of incorrect RAS predictions. +system.cpu2.numCycles 154176343 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9648571 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 142153316 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28832932 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26374772 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54477061 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1438031 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 74339 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 25017392 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 3513 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 6379 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 22688 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 421 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3122610 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 142940 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2082 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 90361689 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.101501 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.407201 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9183670 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 141279801 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28668505 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26247560 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54165747 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1372429 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 60595 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 24017130 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 2633 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 7414 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 19025 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3057990 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 134510 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1720 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 88520588 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.147296 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.411069 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 36017869 39.86% 39.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 584325 0.65% 40.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23803917 26.34% 66.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 312236 0.35% 67.19% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 599559 0.66% 67.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 810629 0.90% 68.76% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 333254 0.37% 69.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 522143 0.58% 69.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27377757 30.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 34483261 38.96% 38.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 569039 0.64% 39.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23712203 26.79% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 303942 0.34% 66.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 596203 0.67% 67.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 791828 0.89% 68.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 321684 0.36% 68.66% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 518300 0.59% 69.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27224128 30.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 90361689 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.184450 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.909383 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 11120847 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 23921754 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 35744474 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1291324 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1114642 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 279457828 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 12 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1114642 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12111653 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 14421944 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4371925 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 35874443 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5298501 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 278479903 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 7178 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2457632 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 2167618 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 332694530 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 605890178 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 372281709 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 54 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 322791874 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 9902651 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 146965 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 147763 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11459312 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6166984 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3428654 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 344111 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 288647 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 276817235 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 412713 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 275284943 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 59120 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 6994425 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10714687 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 55194 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 90361689 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.046479 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.402703 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 88520588 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.185946 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.916352 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10629848 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 22917593 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 30946726 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1286674 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1067388 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 277843876 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 5 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1067388 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11607450 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 13707721 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4125990 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 31086433 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5253313 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 276918591 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 6816 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2458805 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 2129053 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 330941436 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 602250525 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 370032440 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 42 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 321416172 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 9525262 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 139074 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 139963 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11350220 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6069912 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3334552 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 325084 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 284462 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 275324678 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 401766 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 273874447 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 58026 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 6719880 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10332541 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 51920 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 88520588 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.093907 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.392477 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 26846835 29.71% 29.71% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6154250 6.81% 36.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3929000 4.35% 40.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2711977 3.00% 43.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25114660 27.79% 71.66% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1340428 1.48% 73.15% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23928680 26.48% 99.63% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 282970 0.31% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 52889 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 25429283 28.73% 28.73% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6033030 6.82% 35.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3870306 4.37% 39.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2690716 3.04% 42.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25010151 28.25% 71.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1323131 1.49% 72.70% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23827077 26.92% 99.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 285216 0.32% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 51678 0.06% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 90361689 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 88520588 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 125502 33.84% 33.84% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 241 0.06% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 190694 51.42% 85.33% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 54418 14.67% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 120453 33.21% 33.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 124 0.03% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 190037 52.39% 85.63% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 52134 14.37% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 78208 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 265424287 96.42% 96.45% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 56044 0.02% 96.47% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 46278 0.02% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6463688 2.35% 98.83% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3216438 1.17% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 69880 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 264196051 96.47% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 53857 0.02% 96.51% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 45427 0.02% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6378380 2.33% 98.86% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3130852 1.14% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 275284943 # Type of FU issued -system.cpu2.iq.rate 1.761053 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 370855 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001347 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 641401400 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 284227989 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 273934511 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 90 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 102 # Number of floating instruction queue writes +system.cpu2.iq.FU_type_0::total 273874447 # Type of FU issued +system.cpu2.iq.rate 1.776371 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 362748 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001325 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 636728050 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 282449613 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 272560977 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 75 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 74 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 22 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 275577549 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 41 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 638960 # Number of loads that had data forwarded from stores +system.cpu2.iq.int_alu_accesses 274167280 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 35 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 638144 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 974310 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6664 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4257 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 503319 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 933920 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 7005 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3826 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 481474 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656257 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10390 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656274 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10618 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1114642 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9684851 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 815798 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 277229948 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 71784 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6166984 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3428654 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 232570 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 630862 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 4638 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4257 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 175308 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 177843 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 353151 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 274790127 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6353973 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 494815 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1067388 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9024497 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 812904 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 275726444 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 67814 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6069912 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3334552 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 224273 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 631637 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 3885 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3826 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 167894 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 164610 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 332504 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273407129 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6276348 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 467317 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9504896 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27944071 # Number of branches executed -system.cpu2.iew.exec_stores 3150923 # Number of stores executed -system.cpu2.iew.exec_rate 1.757888 # Inst execution rate -system.cpu2.iew.wb_sent 274642284 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 273934533 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 213583516 # num instructions producing a value -system.cpu2.iew.wb_consumers 349233536 # num instructions consuming a value +system.cpu2.iew.exec_refs 9343774 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27815177 # Number of branches executed +system.cpu2.iew.exec_stores 3067426 # Number of stores executed +system.cpu2.iew.exec_rate 1.773340 # Inst execution rate +system.cpu2.iew.wb_sent 273265355 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 272560999 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212629872 # num instructions producing a value +system.cpu2.iew.wb_consumers 347702126 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.752414 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611578 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.767852 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611529 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7294558 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357518 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 313650 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 89247046 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.024569 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.872131 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7002811 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 349846 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 295934 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 87453200 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 3.072767 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.870996 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 31615758 35.42% 35.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4405793 4.94% 40.36% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1230871 1.38% 41.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24727866 27.71% 69.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 857199 0.96% 70.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 581394 0.65% 71.06% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 343629 0.39% 71.44% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23391082 26.21% 97.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2093454 2.35% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 30168588 34.50% 34.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4310788 4.93% 39.43% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1198483 1.37% 40.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24616834 28.15% 68.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 847666 0.97% 69.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 576601 0.66% 70.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 339942 0.39% 70.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23302626 26.65% 97.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2091672 2.39% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 89247046 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136718686 # Number of instructions committed -system.cpu2.commit.committedOps 269933879 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 87453200 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 136077774 # Number of instructions committed +system.cpu2.commit.committedOps 268723335 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8118007 # Number of memory references committed -system.cpu2.commit.loads 5192672 # Number of loads committed -system.cpu2.commit.membars 165488 # Number of memory barriers committed -system.cpu2.commit.branches 27614013 # Number of branches committed +system.cpu2.commit.refs 7989069 # Number of memory references committed +system.cpu2.commit.loads 5135991 # Number of loads committed +system.cpu2.commit.membars 163538 # Number of memory barriers committed +system.cpu2.commit.branches 27499066 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 246437097 # Number of committed integer instructions. -system.cpu2.commit.function_calls 432570 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 2093454 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 245318960 # Number of committed integer instructions. +system.cpu2.commit.function_calls 428759 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 2091672 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 364355237 # The number of ROB reads -system.cpu2.rob.rob_writes 555575410 # The number of ROB writes -system.cpu2.timesIdled 476451 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65956676 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4907452688 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136718686 # Number of Instructions Simulated -system.cpu2.committedOps 269933879 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 136718686 # Number of Instructions Simulated -system.cpu2.cpi 1.143358 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.143358 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.874617 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.874617 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 365607519 # number of integer regfile reads -system.cpu2.int_regfile_writes 219416427 # number of integer regfile writes +system.cpu2.rob.rob_reads 361063162 # The number of ROB reads +system.cpu2.rob.rob_writes 552523197 # The number of ROB writes +system.cpu2.timesIdled 466136 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65655755 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4909695924 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 136077774 # Number of Instructions Simulated +system.cpu2.committedOps 268723335 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 136077774 # Number of Instructions Simulated +system.cpu2.cpi 1.133002 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.133002 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.882611 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.882611 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 363659019 # number of integer regfile reads +system.cpu2.int_regfile_writes 218348978 # number of integer regfile writes system.cpu2.fp_regfile_reads 72934 # number of floating regfile reads system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 139623375 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107543298 # number of cc regfile writes -system.cpu2.misc_regfile_reads 89002893 # number of misc regfile reads -system.cpu2.misc_regfile_writes 130765 # number of misc regfile writes +system.cpu2.cc_regfile_reads 138971726 # number of cc regfile reads +system.cpu2.cc_regfile_writes 107072573 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88484504 # number of misc regfile reads +system.cpu2.misc_regfile_writes 124462 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |