diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 11:07:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 11:07:18 +0100 |
| commit | 62b6ff22ec1f90014b1d0fc778014bdb38cc09ce (patch) | |
| tree | 8dc7be3b13f98b2f6d082dc7424335d9ddfe764d /tests/long/fs/10.linux-boot/ref | |
| parent | 71a02f624e9c406ad37a1ed7030f98a36da6e59f (diff) | |
| download | gem5-62b6ff22ec1f90014b1d0fc778014bdb38cc09ce.tar.xz | |
stats: update for snoop filter tweak
--HG--
extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref')
28 files changed, 32641 insertions, 32382 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 3a2e9a680..2f001f46a 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.907083 # Nu sim_ticks 1907083088000 # Number of ticks simulated final_tick 1907083088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20979 # Simulator instruction rate (inst/s) -host_op_rate 20979 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 712669715 # Simulator tick rate (ticks/s) -host_mem_usage 389460 # Number of bytes of host memory used -host_seconds 2675.97 # Real time elapsed on the host +host_inst_rate 20329 # Simulator instruction rate (inst/s) +host_op_rate 20329 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 690572794 # Simulator tick rate (ticks/s) +host_mem_usage 384580 # Number of bytes of host memory used +host_seconds 2761.60 # Real time elapsed on the host sim_insts 56139550 # Number of instructions simulated sim_ops 56139550 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 4b8dc4618..7d7e06664 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.929078 # Number of seconds simulated -sim_ticks 1929077876500 # Number of ticks simulated -final_tick 1929077876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.908652 # Number of seconds simulated +sim_ticks 1908652088000 # Number of ticks simulated +final_tick 1908652088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169237 # Simulator instruction rate (inst/s) -host_op_rate 169237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5749129790 # Simulator tick rate (ticks/s) -host_mem_usage 339544 # Number of bytes of host memory used -host_seconds 335.54 # Real time elapsed on the host -sim_insts 56786201 # Number of instructions simulated -sim_ops 56786201 # Number of ops (including micro ops) simulated +host_inst_rate 169428 # Simulator instruction rate (inst/s) +host_op_rate 169428 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5757307258 # Simulator tick rate (ticks/s) +host_mem_usage 336708 # Number of bytes of host memory used +host_seconds 331.52 # Real time elapsed on the host +sim_insts 56168509 # Number of instructions simulated +sim_ops 56168509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 856320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24603328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 123072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 684608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 873216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24648192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 103232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 582976 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26268288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 856320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 123072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 979392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7871488 # Number of bytes written to this memory -system.physmem.bytes_written::total 7871488 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13380 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 384427 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10697 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26208576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 873216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 103232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 976448 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7849920 # Number of bytes written to this memory +system.physmem.bytes_written::total 7849920 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13644 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385128 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1613 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9109 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410442 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122992 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122992 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 443901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12753932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 63798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 354889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13617018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 443901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 63798 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 507700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4080441 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4080441 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4080441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 443901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12753932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 63798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 354889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17697459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410442 # Number of read requests accepted -system.physmem.writeReqs 122992 # Number of write requests accepted -system.physmem.readBursts 410442 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122992 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26260992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue -system.physmem.bytesWritten 7869440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26268288 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7871488 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 409509 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122655 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122655 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 457504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12913926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 305439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13731458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 457504 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 511590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4112808 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4112808 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4112808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 457504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12913926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 305439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17844266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 409509 # Number of read requests accepted +system.physmem.writeReqs 122655 # Number of write requests accepted +system.physmem.readBursts 409509 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122655 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26200320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue +system.physmem.bytesWritten 7848512 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26208576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7849920 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26358 # Per bank write bursts -system.physmem.perBankRdBursts::1 25853 # Per bank write bursts -system.physmem.perBankRdBursts::2 25982 # Per bank write bursts -system.physmem.perBankRdBursts::3 25455 # Per bank write bursts -system.physmem.perBankRdBursts::4 25391 # Per bank write bursts -system.physmem.perBankRdBursts::5 25779 # Per bank write bursts -system.physmem.perBankRdBursts::6 25718 # Per bank write bursts -system.physmem.perBankRdBursts::7 25362 # Per bank write bursts -system.physmem.perBankRdBursts::8 25502 # Per bank write bursts -system.physmem.perBankRdBursts::9 25880 # Per bank write bursts -system.physmem.perBankRdBursts::10 25847 # Per bank write bursts -system.physmem.perBankRdBursts::11 25125 # Per bank write bursts -system.physmem.perBankRdBursts::12 25573 # Per bank write bursts -system.physmem.perBankRdBursts::13 25368 # Per bank write bursts -system.physmem.perBankRdBursts::14 25415 # Per bank write bursts -system.physmem.perBankRdBursts::15 25720 # Per bank write bursts -system.physmem.perBankWrBursts::0 8608 # Per bank write bursts -system.physmem.perBankWrBursts::1 7821 # Per bank write bursts -system.physmem.perBankWrBursts::2 8027 # Per bank write bursts -system.physmem.perBankWrBursts::3 7496 # Per bank write bursts -system.physmem.perBankWrBursts::4 7316 # Per bank write bursts -system.physmem.perBankWrBursts::5 7320 # Per bank write bursts -system.physmem.perBankWrBursts::6 7241 # Per bank write bursts -system.physmem.perBankWrBursts::7 6937 # Per bank write bursts -system.physmem.perBankWrBursts::8 7156 # Per bank write bursts -system.physmem.perBankWrBursts::9 7588 # Per bank write bursts -system.physmem.perBankWrBursts::10 7741 # Per bank write bursts -system.physmem.perBankWrBursts::11 7304 # Per bank write bursts -system.physmem.perBankWrBursts::12 7945 # Per bank write bursts -system.physmem.perBankWrBursts::13 8097 # Per bank write bursts -system.physmem.perBankWrBursts::14 8174 # Per bank write bursts -system.physmem.perBankWrBursts::15 8189 # Per bank write bursts +system.physmem.perBankRdBursts::0 25687 # Per bank write bursts +system.physmem.perBankRdBursts::1 26129 # Per bank write bursts +system.physmem.perBankRdBursts::2 25602 # Per bank write bursts +system.physmem.perBankRdBursts::3 25363 # Per bank write bursts +system.physmem.perBankRdBursts::4 24824 # Per bank write bursts +system.physmem.perBankRdBursts::5 25086 # Per bank write bursts +system.physmem.perBankRdBursts::6 25117 # Per bank write bursts +system.physmem.perBankRdBursts::7 24738 # Per bank write bursts +system.physmem.perBankRdBursts::8 25651 # Per bank write bursts +system.physmem.perBankRdBursts::9 26257 # Per bank write bursts +system.physmem.perBankRdBursts::10 25842 # Per bank write bursts +system.physmem.perBankRdBursts::11 26258 # Per bank write bursts +system.physmem.perBankRdBursts::12 25994 # Per bank write bursts +system.physmem.perBankRdBursts::13 25940 # Per bank write bursts +system.physmem.perBankRdBursts::14 25679 # Per bank write bursts +system.physmem.perBankRdBursts::15 25213 # Per bank write bursts +system.physmem.perBankWrBursts::0 7897 # Per bank write bursts +system.physmem.perBankWrBursts::1 8119 # Per bank write bursts +system.physmem.perBankWrBursts::2 8345 # Per bank write bursts +system.physmem.perBankWrBursts::3 7678 # Per bank write bursts +system.physmem.perBankWrBursts::4 7188 # Per bank write bursts +system.physmem.perBankWrBursts::5 7302 # Per bank write bursts +system.physmem.perBankWrBursts::6 7389 # Per bank write bursts +system.physmem.perBankWrBursts::7 6798 # Per bank write bursts +system.physmem.perBankWrBursts::8 7376 # Per bank write bursts +system.physmem.perBankWrBursts::9 7907 # Per bank write bursts +system.physmem.perBankWrBursts::10 7738 # Per bank write bursts +system.physmem.perBankWrBursts::11 7709 # Per bank write bursts +system.physmem.perBankWrBursts::12 7797 # Per bank write bursts +system.physmem.perBankWrBursts::13 7971 # Per bank write bursts +system.physmem.perBankWrBursts::14 7878 # Per bank write bursts +system.physmem.perBankWrBursts::15 7541 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1929076824500 # Total gap between requests +system.physmem.numWrRetry 13 # Number of times write queue was full causing retry +system.physmem.totGap 1908647739500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410442 # Read request sizes (log2) +system.physmem.readPktSize::6 409509 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122992 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 318267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 37921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24678 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122655 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 37774 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24859 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -158,194 +158,206 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 32 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65334 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 522.399241 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 318.882184 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 410.899985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14976 22.92% 22.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11360 17.39% 40.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5432 8.31% 48.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2850 4.36% 52.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2530 3.87% 56.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1671 2.56% 59.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3857 5.90% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1188 1.82% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21470 32.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65334 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5522 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.304962 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2840.771031 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5519 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64693 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.314006 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.672506 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.720496 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14759 22.81% 22.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11414 17.64% 40.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5700 8.81% 49.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2716 4.20% 53.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2485 3.84% 57.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1481 2.29% 59.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1583 2.45% 62.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1463 2.26% 64.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23092 35.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64693 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5538 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 73.921271 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2818.439252 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5535 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5522 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5522 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.267294 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.111227 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.252131 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4917 89.04% 89.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 44 0.80% 89.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 22 0.40% 90.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 38 0.69% 90.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 207 3.75% 94.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 6 0.11% 94.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 12 0.22% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 27 0.49% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 186 3.37% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 6 0.11% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 8 0.14% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 2 0.04% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 8 0.14% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 6 0.11% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.04% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 4 0.07% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 5 0.09% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 3 0.05% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 3 0.05% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.05% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5522 # Writes before turning the bus around for reads -system.physmem.totQLat 4416821750 # Total ticks spent queuing -system.physmem.totMemAccLat 12110471750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2051640000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10764.12 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5538 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5538 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.143915 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.892939 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.348287 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4779 86.29% 86.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 158 2.85% 89.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 16 0.29% 89.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 27 0.49% 89.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 200 3.61% 93.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 23 0.42% 93.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 15 0.27% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.13% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 3 0.05% 94.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.11% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 11 0.20% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.13% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 10 0.18% 95.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.07% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.02% 95.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 30 0.54% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.04% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 13 0.23% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 169 3.05% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.05% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 7 0.13% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.04% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.07% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.05% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 12 0.22% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 9 0.16% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5538 # Writes before turning the bus around for reads +system.physmem.totQLat 3969590750 # Total ticks spent queuing +system.physmem.totMemAccLat 11645465750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2046900000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9696.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29514.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.61 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.62 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.08 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28446.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.77 # Average write queue length when enqueuing -system.physmem.readRowHits 369361 # Number of row buffer hits during reads -system.physmem.writeRowHits 98593 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.16 # Row buffer hit rate for writes -system.physmem.avgGap 3616336.46 # Average gap between requests -system.physmem.pageHitRate 87.74 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 246047760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 134252250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1606004400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 393763680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125997774240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63271865610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1101943260750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1293592968690 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.576874 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1832974418500 # Time in different power states -system.physmem_0.memoryStateTime::REF 64416040000 # Time in different power states +system.physmem.avgRdQLen 2.19 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.90 # Average write queue length when enqueuing +system.physmem.readRowHits 368832 # Number of row buffer hits during reads +system.physmem.writeRowHits 98488 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.10 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.30 # Row buffer hit rate for writes +system.physmem.avgGap 3586578.08 # Average gap between requests +system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 244233360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133262250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1579858800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 393439680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124663821360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 57966073335 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1094343472500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1279324161285 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.276452 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1820370973000 # Time in different power states +system.physmem_0.memoryStateTime::REF 63734060000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31684384000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 24546489500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 247877280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 135250500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1594554000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 403017120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125997774240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 63221156415 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1101987750750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1293587380305 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.573972 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1833051648500 # Time in different power states -system.physmem_1.memoryStateTime::REF 64416040000 # Time in different power states +system.physmem_1.actEnergy 244845720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133596375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1613305200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 401222160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124663821360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 57268583145 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1094955297750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1279280671710 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.253671 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1821389841500 # Time in different power states +system.physmem_1.memoryStateTime::REF 63734060000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31607167750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23527607250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 17100345 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14625316 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 474432 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10759421 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4832502 # Number of BTB hits +system.cpu0.branchPred.lookups 18555851 # Number of BP lookups +system.cpu0.branchPred.condPredicted 15805635 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 543843 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 11677993 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5178603 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 44.914145 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 945329 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 34555 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 5020643 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 507910 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 4512733 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 209375 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 44.344974 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 1050126 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 41449 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5562960 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 527221 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 5035739 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 249629 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9634816 # DTB read hits -system.cpu0.dtb.read_misses 36704 # DTB read misses -system.cpu0.dtb.read_acv 586 # DTB read access violations -system.cpu0.dtb.read_accesses 618265 # DTB read accesses -system.cpu0.dtb.write_hits 5807101 # DTB write hits -system.cpu0.dtb.write_misses 8981 # DTB write misses +system.cpu0.dtb.read_hits 10426157 # DTB read hits +system.cpu0.dtb.read_misses 39598 # DTB read misses +system.cpu0.dtb.read_acv 591 # DTB read access violations +system.cpu0.dtb.read_accesses 665311 # DTB read accesses +system.cpu0.dtb.write_hits 6323119 # DTB write hits +system.cpu0.dtb.write_misses 9829 # DTB write misses system.cpu0.dtb.write_acv 421 # DTB write access violations -system.cpu0.dtb.write_accesses 195454 # DTB write accesses -system.cpu0.dtb.data_hits 15441917 # DTB hits -system.cpu0.dtb.data_misses 45685 # DTB misses -system.cpu0.dtb.data_acv 1007 # DTB access violations -system.cpu0.dtb.data_accesses 813719 # DTB accesses -system.cpu0.itb.fetch_hits 1375653 # ITB hits -system.cpu0.itb.fetch_misses 7396 # ITB misses -system.cpu0.itb.fetch_acv 601 # ITB acv -system.cpu0.itb.fetch_accesses 1383049 # ITB accesses +system.cpu0.dtb.write_accesses 221072 # DTB write accesses +system.cpu0.dtb.data_hits 16749276 # DTB hits +system.cpu0.dtb.data_misses 49427 # DTB misses +system.cpu0.dtb.data_acv 1012 # DTB access violations +system.cpu0.dtb.data_accesses 886383 # DTB accesses +system.cpu0.itb.fetch_hits 1503637 # ITB hits +system.cpu0.itb.fetch_misses 7915 # ITB misses +system.cpu0.itb.fetch_acv 722 # ITB acv +system.cpu0.itb.fetch_accesses 1511552 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -358,590 +370,590 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 146500468 # number of cpu cycles simulated +system.cpu0.numCycles 120614537 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26225748 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 74880065 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 17100345 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6285741 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 112740313 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1369370 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 398 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 30412 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 147220 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 425638 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 504 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8642043 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 322305 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 140254918 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.533885 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.795707 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 28910287 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 80847463 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 18555851 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6755950 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 84571652 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1544806 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 27521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 158722 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 425179 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 306 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 9281945 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 366954 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 114866072 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.703841 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.035887 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 126345960 90.08% 90.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 903115 0.64% 90.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1906918 1.36% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 803345 0.57% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2649453 1.89% 94.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 589849 0.42% 94.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 700559 0.50% 95.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 843084 0.60% 96.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5512635 3.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 99921621 86.99% 86.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 978753 0.85% 87.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2003703 1.74% 89.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 871619 0.76% 90.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2763119 2.41% 92.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 643273 0.56% 93.31% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 756873 0.66% 93.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 980520 0.85% 94.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5946591 5.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 140254918 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.116726 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.511125 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 20974212 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 107876486 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8907132 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1841497 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 655590 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 626155 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 29675 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 64967024 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 87739 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 655590 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 21855511 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 78567360 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18275925 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9798485 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11102045 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 62456562 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 201631 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2042440 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 306402 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 7083961 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 42144620 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 75447660 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 75312247 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 126226 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34366321 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7778299 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1457881 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 236313 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12541674 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10026235 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6171298 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1512964 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 977849 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 55240015 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1897630 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 53565100 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 74212 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9657224 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 4199823 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1322202 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 140254918 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.381912 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.107336 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 114866072 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.153844 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.670296 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 23249023 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 79273649 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9681952 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1921768 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 739679 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 692177 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 33362 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 69931495 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 102843 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 739679 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 24188488 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 52133494 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18507080 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10598824 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8698505 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 67143844 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 198929 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2037542 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 235156 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4634826 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 45210033 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 80787031 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 80633489 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 143553 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36399823 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8810210 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1599007 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 262557 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 13124305 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10911287 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6742479 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1608349 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1040811 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 59252141 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 2087306 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 57311786 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 84500 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10900957 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4754694 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1456877 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 114866072 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.498944 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.243932 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 118450817 84.45% 84.45% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9324559 6.65% 91.10% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3896910 2.78% 93.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2805800 2.00% 95.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2901850 2.07% 97.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1433856 1.02% 98.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 954902 0.68% 99.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 366563 0.26% 99.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 119661 0.09% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 91593251 79.74% 79.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9917884 8.63% 88.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4171968 3.63% 92.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2987675 2.60% 94.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 3091850 2.69% 97.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1551239 1.35% 98.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1031605 0.90% 99.55% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 391084 0.34% 99.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 129516 0.11% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 140254918 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 114866072 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 172960 16.73% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 530801 51.33% 68.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 330287 31.94% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 177618 15.88% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 15.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 580154 51.88% 67.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 360585 32.24% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3306 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 36704403 68.52% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56318 0.11% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 27375 0.05% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1652 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 10076531 18.81% 87.50% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5896825 11.01% 98.51% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 798690 1.49% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3316 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 38999657 68.05% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 59968 0.10% 68.16% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 28473 0.05% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1656 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 10921462 19.06% 87.27% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6423481 11.21% 98.48% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 873773 1.52% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 53565100 # Type of FU issued -system.cpu0.iq.rate 0.365631 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1034048 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019305 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 247915569 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 66533789 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 51792941 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 577809 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 279350 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 262536 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 54284218 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 311624 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 608466 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 57311786 # Type of FU issued +system.cpu0.iq.rate 0.475165 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1118357 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019514 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 230030260 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 71938879 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 55311420 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 662241 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 320414 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 300136 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 58069335 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 357492 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 651404 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2001818 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4069 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18629 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 679305 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2319887 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3968 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 19302 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 772094 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18387 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 376944 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18487 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 403076 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 655590 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 75078561 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 955285 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 60714699 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 160012 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10026235 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6171298 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1682472 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 42874 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 711273 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18629 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 185912 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 515422 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 701334 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 52870028 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9698038 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 695072 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 739679 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 48919856 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 836899 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 65195890 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 175652 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10911287 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6742479 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1850250 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 42611 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 592619 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 19302 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 209624 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 584555 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 794179 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 56526207 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 10495265 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 785579 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3577054 # number of nop insts executed -system.cpu0.iew.exec_refs 15531241 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8401878 # Number of branches executed -system.cpu0.iew.exec_stores 5833203 # Number of stores executed -system.cpu0.iew.exec_rate 0.360886 # Inst execution rate -system.cpu0.iew.wb_sent 52244753 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 52055477 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26703720 # num instructions producing a value -system.cpu0.iew.wb_consumers 36905470 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.355326 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.723571 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 10154720 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 575428 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 626255 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 138489248 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.363854 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.249176 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 3856443 # number of nop insts executed +system.cpu0.iew.exec_refs 16847340 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8962761 # Number of branches executed +system.cpu0.iew.exec_stores 6352075 # Number of stores executed +system.cpu0.iew.exec_rate 0.468652 # Inst execution rate +system.cpu0.iew.wb_sent 55828896 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 55611556 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 28259375 # num instructions producing a value +system.cpu0.iew.wb_consumers 39130384 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.461068 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.722185 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 11491140 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 630429 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 709660 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 112872616 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.474349 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.409733 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 120648787 87.12% 87.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7115506 5.14% 92.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3823437 2.76% 95.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2034446 1.47% 96.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1589267 1.15% 97.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 580000 0.42% 98.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 430694 0.31% 98.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 453916 0.33% 98.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1813195 1.31% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 93942624 83.23% 83.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7580066 6.72% 89.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4021065 3.56% 93.51% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2150933 1.91% 95.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1669707 1.48% 96.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 619428 0.55% 97.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 456360 0.40% 97.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 507616 0.45% 98.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1924817 1.71% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 138489248 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50389922 # Number of instructions committed -system.cpu0.commit.committedOps 50389922 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 112872616 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 53540971 # Number of instructions committed +system.cpu0.commit.committedOps 53540971 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13516410 # Number of memory references committed -system.cpu0.commit.loads 8024417 # Number of loads committed -system.cpu0.commit.membars 195679 # Number of memory barriers committed -system.cpu0.commit.branches 7630866 # Number of branches committed -system.cpu0.commit.fp_insts 253714 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 46654336 # Number of committed integer instructions. -system.cpu0.commit.function_calls 644656 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2912807 5.78% 5.78% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 32876835 65.24% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 54961 0.11% 71.13% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.13% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 26901 0.05% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1652 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.19% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8220096 16.31% 87.50% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5497981 10.91% 98.41% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 798689 1.59% 100.00% # Class of committed instruction +system.cpu0.commit.refs 14561785 # Number of memory references committed +system.cpu0.commit.loads 8591400 # Number of loads committed +system.cpu0.commit.membars 215482 # Number of memory barriers committed +system.cpu0.commit.branches 8090306 # Number of branches committed +system.cpu0.commit.fp_insts 289534 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 49542263 # Number of committed integer instructions. +system.cpu0.commit.function_calls 699437 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 3105795 5.80% 5.80% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 34689949 64.79% 70.59% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 58544 0.11% 70.70% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.70% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 28001 0.05% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1656 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8806882 16.45% 87.21% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5976371 11.16% 98.37% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 873773 1.63% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 50389922 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1813195 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 197034230 # The number of ROB reads -system.cpu0.rob.rob_writes 122856265 # The number of ROB writes -system.cpu0.timesIdled 490676 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 6245550 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3710936476 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47480420 # Number of Instructions Simulated -system.cpu0.committedOps 47480420 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 3.085492 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.085492 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.324097 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.324097 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 69229174 # number of integer regfile reads -system.cpu0.int_regfile_writes 37925510 # number of integer regfile writes -system.cpu0.fp_regfile_reads 125098 # number of floating regfile reads -system.cpu0.fp_regfile_writes 133204 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1692059 # number of misc regfile reads -system.cpu0.misc_regfile_writes 801866 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1263704 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.064166 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10905904 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1264137 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.627154 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.064166 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988407 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988407 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 433 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 184 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.845703 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 58069444 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 58069444 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6953524 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6953524 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3586613 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3586613 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 178977 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 178977 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184325 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 184325 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10540137 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10540137 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10540137 # number of overall hits -system.cpu0.dcache.overall_hits::total 10540137 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1569058 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1569058 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1703592 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1703592 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20226 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20226 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2959 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2959 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3272650 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3272650 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3272650 # number of overall misses -system.cpu0.dcache.overall_misses::total 3272650 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54620758000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 54620758000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 110116261626 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 110116261626 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 348212000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 348212000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46063500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 46063500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 164737019626 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 164737019626 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 164737019626 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 164737019626 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8522582 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8522582 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5290205 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5290205 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 199203 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 199203 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187284 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 187284 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13812787 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13812787 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13812787 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13812787 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.184106 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.184106 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322028 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.322028 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101535 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101535 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015800 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015800 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.236929 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.236929 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.236929 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.236929 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34811.178427 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 34811.178427 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64637.695895 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 64637.695895 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17216.058539 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17216.058539 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15567.252450 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15567.252450 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50337.500077 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50337.500077 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50337.500077 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50337.500077 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 6721817 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 17671 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 111036 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 116 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.537276 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 152.336207 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 741086 # number of writebacks -system.cpu0.dcache.writebacks::total 741086 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 559859 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 559859 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449235 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1449235 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5567 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5567 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2009094 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2009094 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2009094 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2009094 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1009199 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1009199 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 254357 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 254357 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14659 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14659 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2959 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2959 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1263556 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1263556 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1263556 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1263556 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7031 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7031 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10105 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10105 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17136 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17136 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43480023500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43480023500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 17474692057 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 17474692057 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 173733500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 173733500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 43104500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 43104500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60954715557 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 60954715557 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 60954715557 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 60954715557 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1558946000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1558946000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1558946000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1558946000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118415 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118415 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048081 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048081 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.073588 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.073588 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015800 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015800 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091477 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.091477 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091477 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.091477 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 43083.696575 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 43083.696575 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68701.439540 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68701.439540 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11851.661096 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11851.661096 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14567.252450 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14567.252450 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48240.612650 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48240.612650 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221724.647987 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221724.647987 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 90974.906629 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 90974.906629 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 911237 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.249711 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7675800 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 911749 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.418764 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42368821500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.249711 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992675 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992675 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 53540971 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1924817 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 175788251 # The number of ROB reads +system.cpu0.rob.rob_writes 132059822 # The number of ROB writes +system.cpu0.timesIdled 545123 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5748465 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3696064399 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 50438489 # Number of Instructions Simulated +system.cpu0.committedOps 50438489 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.391319 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.391319 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.418179 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.418179 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 73773620 # number of integer regfile reads +system.cpu0.int_regfile_writes 40428970 # number of integer regfile writes +system.cpu0.fp_regfile_reads 142673 # number of floating regfile reads +system.cpu0.fp_regfile_writes 153221 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1866400 # number of misc regfile reads +system.cpu0.misc_regfile_writes 877434 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1337856 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.906059 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11855471 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1338256 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.858896 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 26822500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.906059 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988098 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988098 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 62973100 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 62973100 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 7528886 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7528886 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3919891 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3919891 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 201495 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 201495 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 204000 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 204000 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11448777 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11448777 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11448777 # number of overall hits +system.cpu0.dcache.overall_hits::total 11448777 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1699683 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1699683 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1831149 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1831149 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21973 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21973 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 873 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 873 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3530832 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3530832 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3530832 # number of overall misses +system.cpu0.dcache.overall_misses::total 3530832 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40671315500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 40671315500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77312811875 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 77312811875 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 331728000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 331728000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6457500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 6457500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 117984127375 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 117984127375 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 117984127375 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 117984127375 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 9228569 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 9228569 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5751040 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5751040 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 223468 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 223468 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 204873 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 204873 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14979609 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14979609 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14979609 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14979609 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.184176 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.184176 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318403 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.318403 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.098327 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.098327 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004261 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004261 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.235709 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.235709 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.235709 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.235709 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23928.765246 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 23928.765246 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42220.928977 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42220.928977 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15097.073681 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15097.073681 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7396.907216 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7396.907216 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33415.389737 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33415.389737 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33415.389737 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33415.389737 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4312836 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 8080 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 119422 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 127 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.114250 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 63.622047 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 792748 # number of writebacks +system.cpu0.dcache.writebacks::total 792748 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 643460 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 643460 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1557660 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1557660 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 6525 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 6525 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2201120 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2201120 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2201120 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2201120 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1056223 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1056223 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 273489 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 273489 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15448 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15448 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 873 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 873 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1329712 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1329712 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1329712 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1329712 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7053 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7053 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9807 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9807 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16860 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16860 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30297527500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30297527500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12178891856 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12178891856 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 190480500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 190480500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5584500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5584500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42476419356 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 42476419356 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42476419356 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 42476419356 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1570178500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1570178500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1570178500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1570178500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.114451 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.114451 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.047555 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.047555 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.069128 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.069128 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004261 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004261 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.088768 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.088768 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.088768 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.088768 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28684.782948 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28684.782948 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44531.560158 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44531.560158 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12330.431124 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.431124 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6396.907216 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6396.907216 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31944.074624 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31944.074624 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31944.074624 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31944.074624 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222625.620303 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222625.620303 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93130.397390 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93130.397390 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 1021310 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.519684 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 8197716 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1021822 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.022646 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 28452447500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.519684 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995156 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995156 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 316 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 196 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 492 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9554008 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9554008 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7675800 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7675800 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7675800 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7675800 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7675800 # number of overall hits -system.cpu0.icache.overall_hits::total 7675800 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 966240 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 966240 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 966240 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 966240 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 966240 # number of overall misses -system.cpu0.icache.overall_misses::total 966240 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14731064486 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14731064486 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14731064486 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14731064486 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14731064486 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14731064486 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8642040 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8642040 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8642040 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8642040 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8642040 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8642040 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111807 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.111807 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111807 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.111807 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111807 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.111807 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15245.761391 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15245.761391 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15245.761391 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15245.761391 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15245.761391 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15245.761391 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 11439 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 10303980 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 10303980 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 8197716 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 8197716 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 8197716 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 8197716 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 8197716 # number of overall hits +system.cpu0.icache.overall_hits::total 8197716 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1084226 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1084226 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1084226 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1084226 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1084226 # number of overall misses +system.cpu0.icache.overall_misses::total 1084226 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15369093993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 15369093993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 15369093993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 15369093993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 15369093993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 15369093993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 9281942 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 9281942 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 9281942 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 9281942 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 9281942 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 9281942 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116810 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.116810 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116810 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.116810 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116810 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.116810 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14175.175649 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14175.175649 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14175.175649 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14175.175649 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14175.175649 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14175.175649 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5565 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 347 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 223 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 32.965418 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.955157 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 911237 # number of writebacks -system.cpu0.icache.writebacks::total 911237 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54272 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 54272 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 54272 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 54272 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 54272 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 54272 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 911968 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 911968 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 911968 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 911968 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 911968 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 911968 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12931897989 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12931897989 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12931897989 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12931897989 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12931897989 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12931897989 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105527 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.105527 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.105527 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14180.210258 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency -system.cpu1.branchPred.lookups 4129053 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3551647 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 103168 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2303722 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 822541 # Number of BTB hits +system.cpu0.icache.writebacks::writebacks 1021310 # number of writebacks +system.cpu0.icache.writebacks::total 1021310 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 62188 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 62188 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 62188 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 62188 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 62188 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 62188 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1022038 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1022038 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1022038 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1022038 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1022038 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1022038 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13659780995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 13659780995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13659780995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 13659780995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13659780995 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 13659780995 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.110110 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.110110 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.110110 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.110110 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.110110 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.110110 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13365.237883 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13365.237883 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13365.237883 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13365.237883 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13365.237883 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13365.237883 # average overall mshr miss latency +system.cpu1.branchPred.lookups 2642221 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2286827 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 62241 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1292185 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 477042 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 35.704872 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 211273 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8217 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 1287279 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 153619 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1133660 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 37557 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 36.917469 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 126491 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 4205 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 709163 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 105030 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 604133 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 17634 # Number of mispredicted indirect branches. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2247369 # DTB read hits -system.cpu1.dtb.read_misses 13283 # DTB read misses -system.cpu1.dtb.read_acv 72 # DTB read access violations -system.cpu1.dtb.read_accesses 382556 # DTB read accesses -system.cpu1.dtb.write_hits 1356336 # DTB write hits -system.cpu1.dtb.write_misses 3091 # DTB write misses -system.cpu1.dtb.write_acv 71 # DTB write access violations -system.cpu1.dtb.write_accesses 152961 # DTB write accesses -system.cpu1.dtb.data_hits 3603705 # DTB hits -system.cpu1.dtb.data_misses 16374 # DTB misses -system.cpu1.dtb.data_acv 143 # DTB access violations -system.cpu1.dtb.data_accesses 535517 # DTB accesses -system.cpu1.itb.fetch_hits 615373 # ITB hits -system.cpu1.itb.fetch_misses 3011 # ITB misses -system.cpu1.itb.fetch_acv 117 # ITB acv -system.cpu1.itb.fetch_accesses 618384 # ITB accesses +system.cpu1.dtb.read_hits 1454361 # DTB read hits +system.cpu1.dtb.read_misses 11674 # DTB read misses +system.cpu1.dtb.read_acv 55 # DTB read access violations +system.cpu1.dtb.read_accesses 336696 # DTB read accesses +system.cpu1.dtb.write_hits 804644 # DTB write hits +system.cpu1.dtb.write_misses 2787 # DTB write misses +system.cpu1.dtb.write_acv 46 # DTB write access violations +system.cpu1.dtb.write_accesses 125975 # DTB write accesses +system.cpu1.dtb.data_hits 2259005 # DTB hits +system.cpu1.dtb.data_misses 14461 # DTB misses +system.cpu1.dtb.data_acv 101 # DTB access violations +system.cpu1.dtb.data_accesses 462671 # DTB accesses +system.cpu1.itb.fetch_hits 472443 # ITB hits +system.cpu1.itb.fetch_misses 2661 # ITB misses +system.cpu1.itb.fetch_acv 95 # ITB acv +system.cpu1.itb.fetch_accesses 475104 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -954,558 +966,567 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 16726806 # number of cpu cycles simulated +system.cpu1.numCycles 10299543 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6696452 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 16370488 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4129053 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1187433 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 8741861 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 347188 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 25893 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 58137 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 49356 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1820963 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 76422 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 15745356 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.039703 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.449166 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 3708105 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 10416725 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2642221 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 708563 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 5867887 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 223660 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 23709 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 51632 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 40219 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1189367 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 46143 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 9803421 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.062560 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.469546 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12876670 81.78% 81.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 185062 1.18% 82.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 297924 1.89% 84.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 209767 1.33% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 372753 2.37% 88.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 143050 0.91% 89.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 159866 1.02% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 207293 1.32% 91.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1292971 8.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 7976409 81.36% 81.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 98791 1.01% 82.37% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 205509 2.10% 84.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 143569 1.46% 85.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 244577 2.49% 88.43% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 96035 0.98% 89.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 110446 1.13% 90.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 69630 0.71% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 858455 8.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 15745356 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.246852 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.978698 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5498623 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 7777976 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2045729 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 256320 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 166707 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 143442 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7016 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 13354105 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22028 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 166707 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5670233 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 826473 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5769862 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2131801 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1180278 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 12651091 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3750 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 88341 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 32960 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 615086 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 8374295 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 15046844 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 14984377 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 56291 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6609856 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1764431 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 476570 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 48769 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2080322 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2346654 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1454994 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 292964 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 152733 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 11085695 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 541496 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 10671183 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 25309 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2321405 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1075261 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 398456 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 15745356 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.677735 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.406788 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 9803421 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.256538 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.011377 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 3120035 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 5128574 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1274002 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 173173 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 107636 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 84669 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 4317 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 8395667 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 13790 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 107636 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 3236399 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 505262 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 3781107 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1330090 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 842925 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 7927045 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 866 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 80988 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 18891 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 445625 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 5308652 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 9558760 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 9526496 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 27580 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 4111841 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1196803 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 316905 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 22710 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1429971 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1508631 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 873340 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 185286 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 107493 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 6977977 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 344578 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 6652421 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 19333 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1592530 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 796148 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 266679 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 9803421 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.678582 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.403550 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 11382155 72.29% 72.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1870956 11.88% 84.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 802175 5.09% 89.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 575742 3.66% 92.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 534921 3.40% 96.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 285738 1.81% 98.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 185455 1.18% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 78165 0.50% 99.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 30049 0.19% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 7053571 71.95% 71.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1194265 12.18% 84.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 509519 5.20% 89.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 375157 3.83% 93.16% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 322481 3.29% 96.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 169260 1.73% 98.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 99294 1.01% 99.19% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 57333 0.58% 99.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 22541 0.23% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 15745356 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 9803421 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 27488 9.05% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 170713 56.19% 65.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 105586 34.76% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24978 11.96% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 11.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 116023 55.55% 67.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 67859 32.49% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3991 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 6611083 61.95% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16524 0.15% 62.14% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 12068 0.11% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1990 0.02% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2360403 22.12% 84.40% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1384355 12.97% 97.37% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 280769 2.63% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3973 0.06% 0.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 4085085 61.41% 61.47% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 10572 0.16% 61.63% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10292 0.15% 61.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.78% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1986 0.03% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.81% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1521104 22.87% 84.68% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 824727 12.40% 97.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 194682 2.93% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 10671183 # Type of FU issued -system.cpu1.iq.rate 0.637969 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 303787 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.028468 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 37199457 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 13849868 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 10195275 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 217360 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 103372 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 100900 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 10854739 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 116240 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 112250 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 6652421 # Type of FU issued +system.cpu1.iq.rate 0.645895 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 208860 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.031396 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 23247701 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 8874149 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 6353252 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 88754 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 44866 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 42405 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 6811194 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 46114 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 75849 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 494389 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1075 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4794 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 168808 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 328260 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 949 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4058 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 119869 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 442 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 89761 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 415 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 72546 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 166707 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 440216 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 341566 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 12247032 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 53191 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2346654 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1454994 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 491166 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 5461 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 335179 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4794 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 42007 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 137108 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 179115 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 10495256 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2269179 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 175926 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 107636 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 325014 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 147509 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 7654698 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 36160 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1508631 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 873340 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 319432 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4857 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 141756 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4058 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 24786 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 89639 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 114425 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 6540293 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1470121 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 112127 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 619841 # number of nop insts executed -system.cpu1.iew.exec_refs 3634984 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1567515 # Number of branches executed -system.cpu1.iew.exec_stores 1365805 # Number of stores executed -system.cpu1.iew.exec_rate 0.627451 # Inst execution rate -system.cpu1.iew.wb_sent 10344393 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 10296175 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4904906 # num instructions producing a value -system.cpu1.iew.wb_consumers 6922372 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.615549 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.708559 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 2337439 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 143040 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 155210 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 15327667 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.637432 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.616488 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 332143 # number of nop insts executed +system.cpu1.iew.exec_refs 2281164 # number of memory reference insts executed +system.cpu1.iew.exec_branches 956130 # Number of branches executed +system.cpu1.iew.exec_stores 811043 # Number of stores executed +system.cpu1.iew.exec_rate 0.635008 # Inst execution rate +system.cpu1.iew.wb_sent 6430736 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 6395657 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 3121788 # num instructions producing a value +system.cpu1.iew.wb_consumers 4363189 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.620965 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.715483 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 1558734 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 77899 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 97361 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 9525282 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.626287 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.584809 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 11807980 77.04% 77.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1622081 10.58% 87.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 578152 3.77% 91.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 357481 2.33% 93.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 274261 1.79% 95.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 117588 0.77% 96.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 104376 0.68% 96.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 117710 0.77% 97.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 348038 2.27% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 7314942 76.80% 76.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1051446 11.04% 87.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 355573 3.73% 91.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 228997 2.40% 93.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 163534 1.72% 95.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 72316 0.76% 96.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 75781 0.80% 97.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 55973 0.59% 97.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 206720 2.17% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 15327667 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9770342 # Number of instructions committed -system.cpu1.commit.committedOps 9770342 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 9525282 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 5965556 # Number of instructions committed +system.cpu1.commit.committedOps 5965556 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3138451 # Number of memory references committed -system.cpu1.commit.loads 1852265 # Number of loads committed -system.cpu1.commit.membars 45725 # Number of memory barriers committed -system.cpu1.commit.branches 1397481 # Number of branches committed -system.cpu1.commit.fp_insts 99132 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 9064844 # Number of committed integer instructions. -system.cpu1.commit.function_calls 152839 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 468541 4.80% 4.80% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 5805964 59.42% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 16275 0.17% 64.39% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 12061 0.12% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1990 0.02% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.53% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1897990 19.43% 83.96% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1286752 13.17% 97.13% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 280769 2.87% 100.00% # Class of committed instruction +system.cpu1.commit.refs 1933842 # Number of memory references committed +system.cpu1.commit.loads 1180371 # Number of loads committed +system.cpu1.commit.membars 21608 # Number of memory barriers committed +system.cpu1.commit.branches 842250 # Number of branches committed +system.cpu1.commit.fp_insts 40666 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 5575941 # Number of committed integer instructions. +system.cpu1.commit.function_calls 91630 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 239508 4.01% 4.01% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 3553035 59.56% 63.57% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 10403 0.17% 63.75% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.75% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 10285 0.17% 63.92% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.92% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.92% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.92% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1986 0.03% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.95% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1201979 20.15% 84.10% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 753678 12.63% 96.74% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 194682 3.26% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 9770342 # Class of committed instruction -system.cpu1.commit.bw_lim_events 348038 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 26989101 # The number of ROB reads -system.cpu1.rob.rob_writes 24630830 # The number of ROB writes -system.cpu1.timesIdled 131471 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 981450 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3841428948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9305781 # Number of Instructions Simulated -system.cpu1.committedOps 9305781 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.797464 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.797464 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.556339 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.556339 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 13488576 # number of integer regfile reads -system.cpu1.int_regfile_writes 7349661 # number of integer regfile writes -system.cpu1.fp_regfile_reads 55714 # number of floating regfile reads -system.cpu1.fp_regfile_writes 55051 # number of floating regfile writes -system.cpu1.misc_regfile_reads 538402 # number of misc regfile reads -system.cpu1.misc_regfile_writes 228232 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 120114 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.559727 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2854712 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 120626 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.665810 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 62007957000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.559727 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.950312 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.950312 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 5965556 # Class of committed instruction +system.cpu1.commit.bw_lim_events 206720 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 16752551 # The number of ROB reads +system.cpu1.rob.rob_writes 15324043 # The number of ROB writes +system.cpu1.timesIdled 69166 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 496122 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3807004634 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 5730020 # Number of Instructions Simulated +system.cpu1.committedOps 5730020 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.797471 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.797471 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.556337 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.556337 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 8470716 # number of integer regfile reads +system.cpu1.int_regfile_writes 4619691 # number of integer regfile writes +system.cpu1.fp_regfile_reads 26922 # number of floating regfile reads +system.cpu1.fp_regfile_writes 25344 # number of floating regfile writes +system.cpu1.misc_regfile_reads 302216 # number of misc regfile reads +system.cpu1.misc_regfile_writes 137559 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 64410 # number of replacements +system.cpu1.dcache.tags.tagsinuse 463.614906 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 1794834 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 64922 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.646006 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1880101020500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 463.614906 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.905498 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.905498 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 244 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 13510694 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 13510694 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1801260 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1801260 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 972413 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 972413 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 37246 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 37246 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 33039 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 33039 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2773673 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2773673 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2773673 # number of overall hits -system.cpu1.dcache.overall_hits::total 2773673 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 221542 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 221542 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 271468 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 271468 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5109 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5109 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3089 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3089 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 493010 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 493010 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 493010 # number of overall misses -system.cpu1.dcache.overall_misses::total 493010 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2936746000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2936746000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12570320655 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 12570320655 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51167000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 51167000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 47352500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 47352500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 15507066655 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 15507066655 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 15507066655 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 15507066655 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2022802 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2022802 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1243881 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1243881 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 42355 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 42355 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 36128 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 36128 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3266683 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3266683 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3266683 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3266683 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109522 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.109522 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.218243 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.218243 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120623 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120623 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085502 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.085502 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.150921 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.150921 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.150921 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.150921 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13255.933412 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13255.933412 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46304.981269 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 46304.981269 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10015.071443 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10015.071443 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15329.394626 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15329.394626 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31453.858248 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 31453.858248 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31453.858248 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 31453.858248 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 759613 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1583 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 22564 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.664820 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 131.916667 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 79554 # number of writebacks -system.cpu1.dcache.writebacks::total 79554 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 136401 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 136401 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 226329 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 226329 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 689 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 689 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 362730 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 362730 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 362730 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 362730 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 85141 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 85141 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 45139 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 45139 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4420 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4420 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3085 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3085 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 130280 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 130280 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 130280 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 130280 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 162 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 162 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2990 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2990 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3152 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3152 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1075350000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1075350000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2078906462 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2078906462 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 39137500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 39137500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44267500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44267500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3154256462 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3154256462 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3154256462 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3154256462 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32176000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32176000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 32176000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 32176000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042091 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042091 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036289 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036289 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104356 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104356 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085391 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085391 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039881 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039881 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039881 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039881 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12630.225156 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12630.225156 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46055.660560 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46055.660560 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8854.638009 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8854.638009 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14349.270665 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14349.270665 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24211.363694 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24211.363694 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198617.283951 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198617.283951 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10208.121827 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10208.121827 # average overall mshr uncacheable latency -system.cpu1.icache.tags.replacements 244089 # number of replacements -system.cpu1.icache.tags.tagsinuse 469.435893 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1565201 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 244601 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.398997 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1896682174500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 469.435893 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.916867 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.916867 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 430 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2065632 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2065632 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1565201 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1565201 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1565201 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1565201 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1565201 # number of overall hits -system.cpu1.icache.overall_hits::total 1565201 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 255762 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 255762 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 255762 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 255762 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 255762 # number of overall misses -system.cpu1.icache.overall_misses::total 255762 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3690348499 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3690348499 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3690348499 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3690348499 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3690348499 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3690348499 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1820963 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1820963 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1820963 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1820963 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1820963 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1820963 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.140454 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.140454 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.140454 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.140454 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.140454 # 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number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7450335261 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 18882500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 18882500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6469000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 6469000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 34500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 34500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8897542761 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8897542761 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8897542761 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8897542761 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1300427 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1300427 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 732331 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 732331 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 17937 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 17937 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15987 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 15987 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2032758 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2032758 # 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miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.134546 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134546 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.134546 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12974.203236 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12974.203236 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46002.786353 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 46002.786353 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10858.251869 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10858.251869 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7701.190476 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7701.190476 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32532.267983 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 32532.267983 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32532.267983 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 32532.267983 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 463151 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 490 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 15628 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.635974 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 49 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 38002 # number of writebacks +system.cpu1.dcache.writebacks::total 38002 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 65961 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 65961 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 137427 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 137427 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 372 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 372 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 203388 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 203388 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 203388 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 203388 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 45584 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 45584 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 24527 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 24527 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1367 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1367 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 840 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 840 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 70111 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 70111 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 70111 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 70111 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 146 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 146 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2584 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2584 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 2730 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 2730 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 575200000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 575200000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1170679567 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1170679567 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 13141000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 13141000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5630000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5630000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 33500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 33500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1745879567 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1745879567 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1745879567 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1745879567 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29635500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29635500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 29635500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 29635500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035053 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035053 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033492 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033492 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076211 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.076211 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.052543 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.052543 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034491 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034491 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034491 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034491 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12618.462618 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12618.462618 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47730.238798 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 47730.238798 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9613.021214 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9613.021214 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 6702.380952 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 6702.380952 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24901.649770 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24901.649770 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24901.649770 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24901.649770 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202982.876712 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202982.876712 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10855.494505 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10855.494505 # average overall mshr uncacheable latency +system.cpu1.icache.tags.replacements 125381 # number of replacements +system.cpu1.icache.tags.tagsinuse 466.454678 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1056750 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 125892 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 8.394100 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1880706304500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 466.454678 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.911044 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.911044 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 412 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 1315314 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1315314 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1056751 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1056751 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1056751 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1056751 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1056751 # number of overall hits +system.cpu1.icache.overall_hits::total 1056751 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 132616 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 132616 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 132616 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 132616 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 132616 # number of overall misses +system.cpu1.icache.overall_misses::total 132616 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1887030000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1887030000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1887030000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1887030000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1887030000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1887030000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1189367 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1189367 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1189367 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1189367 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1189367 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1189367 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.111501 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.111501 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.111501 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.111501 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.111501 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.111501 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14229.278518 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14229.278518 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14229.278518 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14229.278518 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14229.278518 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14229.278518 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 347 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 56 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 31 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.875000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.193548 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 244089 # number of writebacks -system.cpu1.icache.writebacks::total 244089 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11093 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 11093 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 11093 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 11093 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 11093 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 11093 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 244669 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 244669 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 244669 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 244669 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 244669 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 244669 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3289647499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3289647499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3289647499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3289647499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3289647499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3289647499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.134362 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.134362 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.134362 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13445.297520 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 125381 # number of writebacks +system.cpu1.icache.writebacks::total 125381 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6669 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 6669 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 6669 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 6669 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 6669 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 6669 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 125947 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 125947 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 125947 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 125947 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 125947 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 125947 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1682313500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1682313500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1682313500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1682313500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1682313500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1682313500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105894 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105894 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105894 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.105894 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105894 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.105894 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13357.312997 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13357.312997 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13357.312997 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13357.312997 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13357.312997 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13357.312997 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1518,98 +1539,98 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7368 # Transaction distribution -system.iobus.trans_dist::ReadResp 7368 # Transaction distribution -system.iobus.trans_dist::WriteReq 54647 # Transaction distribution -system.iobus.trans_dist::WriteResp 54647 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11984 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7381 # Transaction distribution +system.iobus.trans_dist::ReadResp 7381 # Transaction distribution +system.iobus.trans_dist::WriteReq 53943 # Transaction distribution +system.iobus.trans_dist::WriteResp 53943 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10586 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1002 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40576 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 124030 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47936 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122648 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42344 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2701 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 74130 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2735754 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12444500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 68539 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661680 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661680 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2730219 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 10864500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 814000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 814501 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 176000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14015000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14057500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6047501 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6034500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 93000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215709165 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216209541 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27481000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26789000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41964000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.551900 # Cycle average of tags in use +system.iocache.tags.replacements 41702 # number of replacements +system.iocache.tags.tagsinuse 0.516326 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41718 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1726981964000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.551900 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.034494 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.034494 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1712300449000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.516326 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.032270 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.032270 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375543 # Number of tag accesses -system.iocache.tags.data_accesses 375543 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.tags.tag_accesses 375606 # Number of tag accesses +system.iocache.tags.data_accesses 375606 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 182 # number of ReadReq misses +system.iocache.ReadReq_misses::total 182 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22072883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22072883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245136282 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5245136282 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5267209165 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5267209165 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5267209165 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5267209165 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41734 # number of demand (read+write) misses +system.iocache.demand_misses::total 41734 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41734 # number of overall misses +system.iocache.overall_misses::total 41734 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22913883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22913883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4860118658 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4860118658 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4883032541 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4883032541 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4883032541 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4883032541 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 182 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 182 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41734 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41734 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41734 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41734 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1618,38 +1639,38 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126130.760000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126130.760000 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.657538 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126230.657538 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126230.238575 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126230.238575 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125900.456044 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125900.456044 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116964.734742 # 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mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013354 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.289149 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012811 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.143788 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.161097 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20056.649257 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20198.347107 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20084.356820 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19892.857143 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19767.326733 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19818.713450 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79295.132091 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 104113.674099 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 81034.887394 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74547.929718 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 76233.106634 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74726.078254 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63867.930013 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80681.168831 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63915.099362 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74547.929718 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68343.674055 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76233.106634 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 102152.901543 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69339.986886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74547.929718 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68343.674055 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76233.106634 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 102152.901543 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69339.986886 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210123.422657 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190482.876712 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209725.100708 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87900.385528 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10186.996337 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 77070.495151 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 843888 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 393117 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 439 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 7199 # Transaction distribution +system.membus.trans_dist::ReadResp 297053 # Transaction distribution +system.membus.trans_dist::WriteReq 12391 # Transaction distribution +system.membus.trans_dist::WriteResp 12391 # Transaction distribution +system.membus.trans_dist::WritebackDirty 122655 # Transaction distribution +system.membus.trans_dist::CleanEvict 262560 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5361 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1592 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 121253 # Transaction distribution -system.membus.trans_dist::ReadExResp 120834 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 290100 # Transaction distribution -system.membus.trans_dist::BadAddressError 46 # Transaction distribution +system.membus.trans_dist::ReadExReq 120253 # Transaction distribution +system.membus.trans_dist::ReadExResp 120107 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289902 # Transaction distribution +system.membus.trans_dist::BadAddressError 48 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1182230 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1222898 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1306335 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 74130 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31481536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31555666 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39180 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1169885 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 96 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1209161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83451 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83451 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1292612 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68539 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31400256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31468795 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34213906 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 12142 # Total snoops (count) -system.membus.snoop_fanout::samples 875570 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size::total 34127035 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 4109 # Total snoops (count) +system.membus.snoop_fanout::samples 478250 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001409 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037514 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 875570 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 477576 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 674 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 875570 # Request fanout histogram -system.membus.reqLayer0.occupancy 36438999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 478250 # Request fanout histogram +system.membus.reqLayer0.occupancy 34894499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1356482971 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1351079796 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 60000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2177455750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2171993250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 936113 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 976613 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 5114760 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2557108 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 345514 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1336 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5115302 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2557070 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 337938 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1067 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 7193 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2266679 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13095 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13095 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 943643 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1155325 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 827144 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10512 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 6044 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 16556 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 299688 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 299688 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1156637 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1102911 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 46 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2735017 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3843601 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 733385 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 384537 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7696540 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 116675136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 128186756 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31277824 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 12692238 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 288831954 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 463427 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3024601 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.120612 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.326035 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2263337 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12391 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12391 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 911885 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1146691 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 834780 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 5446 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1712 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 7158 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 303166 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 303166 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1147985 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1108204 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 48 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 217 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3065153 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4053991 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 377239 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 207014 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7703397 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 130759360 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 136128589 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 16082688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 6548014 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 289518651 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 362547 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2930720 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.118515 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.323634 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2660134 87.95% 87.95% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 364147 12.04% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 303 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 17 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2583760 88.16% 88.16% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 346605 11.83% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 335 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 20 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3024601 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4550078915 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2930720 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4551122919 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 295885 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 306385 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1369499398 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1534824957 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1926492121 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2028150819 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 368355265 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 190444943 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 200907831 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 107558787 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2131,170 +2160,161 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6529 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 180918 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 63985 40.38% 40.38% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.47% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1935 1.22% 41.69% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 191 0.12% 41.81% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 92196 58.19% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 158438 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 62993 49.19% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1935 1.51% 50.81% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 191 0.15% 50.96% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 62802 49.04% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 128052 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1871632607000 97.04% 97.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 66355000 0.00% 97.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 578065000 0.03% 97.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 91849500 0.00% 97.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 56349581000 2.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1928718457500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984496 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 198541 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 71138 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 133 0.08% 40.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1928 1.10% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 20 0.01% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 101928 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 175147 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 69801 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 133 0.09% 49.37% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1928 1.36% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 20 0.01% 50.74% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 69782 49.26% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 141664 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864307233500 97.69% 97.69% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 66845500 0.00% 97.70% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 580922500 0.03% 97.73% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 11315500 0.00% 97.73% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 43373119000 2.27% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1908339436000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981206 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681179 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808215 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.68% 3.68% # number of syscalls executed -system.cpu0.kern.syscall::3 15 7.89% 11.58% # number of syscalls executed -system.cpu0.kern.syscall::4 4 2.11% 13.68% # number of syscalls executed -system.cpu0.kern.syscall::6 28 14.74% 28.42% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.53% 28.95% # number of syscalls executed -system.cpu0.kern.syscall::17 8 4.21% 33.16% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.68% 36.84% # number of syscalls executed -system.cpu0.kern.syscall::20 4 2.11% 38.95% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.53% 39.47% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.58% 41.05% # number of syscalls executed -system.cpu0.kern.syscall::33 6 3.16% 44.21% # number of syscalls executed -system.cpu0.kern.syscall::41 2 1.05% 45.26% # number of syscalls executed -system.cpu0.kern.syscall::45 31 16.32% 61.58% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.58% 63.16% # number of syscalls executed -system.cpu0.kern.syscall::48 8 4.21% 67.37% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.74% 72.11% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.53% 72.63% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.63% 75.26% # number of syscalls executed -system.cpu0.kern.syscall::71 21 11.05% 86.32% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.58% 87.89% # number of syscalls executed -system.cpu0.kern.syscall::74 5 2.63% 90.53% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.53% 91.05% # number of syscalls executed -system.cpu0.kern.syscall::90 2 1.05% 92.11% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.68% 95.79% # number of syscalls executed -system.cpu0.kern.syscall::97 2 1.05% 96.84% # number of syscalls executed -system.cpu0.kern.syscall::98 2 1.05% 97.89% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.53% 98.42% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.53% 98.95% # number of syscalls executed -system.cpu0.kern.syscall::147 2 1.05% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 190 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.684621 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808829 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.70% 3.70% # number of syscalls executed +system.cpu0.kern.syscall::3 18 8.33% 12.04% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.85% 13.89% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.81% 28.70% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.46% 29.17% # number of syscalls executed +system.cpu0.kern.syscall::17 8 3.70% 32.87% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.63% 37.50% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.78% 40.28% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.46% 40.74% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.39% 42.13% # number of syscalls executed +system.cpu0.kern.syscall::33 6 2.78% 44.91% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.93% 45.83% # number of syscalls executed +system.cpu0.kern.syscall::45 33 15.28% 61.11% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.39% 62.50% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.63% 67.13% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.63% 71.76% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.46% 72.22% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.78% 75.00% # number of syscalls executed +system.cpu0.kern.syscall::71 23 10.65% 85.65% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.39% 87.04% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.78% 89.81% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.46% 90.28% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.39% 91.67% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.17% 95.83% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.93% 96.76% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.93% 97.69% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.46% 98.15% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.93% 99.07% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 216 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 292 0.18% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3426 2.05% 2.23% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed -system.cpu0.kern.callpal::swpipl 151781 91.02% 93.28% # number of callpals executed -system.cpu0.kern.callpal::rdps 6336 3.80% 97.08% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.08% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 97.08% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.09% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.09% # number of callpals executed -system.cpu0.kern.callpal::rti 4399 2.64% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 318 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 135 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 166759 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6855 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1159 # number of protection mode switches +system.cpu0.kern.callpal::wripir 116 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3824 2.08% 2.14% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.17% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed +system.cpu0.kern.callpal::swpipl 168401 91.54% 93.72% # number of callpals executed +system.cpu0.kern.callpal::rdps 6369 3.46% 97.18% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.18% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 97.18% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.19% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.19% # number of callpals executed +system.cpu0.kern.callpal::rti 4665 2.54% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 373 0.20% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 183960 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7174 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1257 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1159 -system.cpu0.kern.mode_good::user 1159 +system.cpu0.kern.mode_good::kernel 1257 +system.cpu0.kern.mode_good::user 1257 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.169074 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.175216 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.289244 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1925885387000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1988942000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.298185 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1906404052500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1926707500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3427 # number of times the context was actually changed +system.cpu0.kern.swap_context 3825 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2571 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 58929 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 18404 37.04% 37.04% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1933 3.89% 40.93% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 292 0.59% 41.51% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 29063 58.49% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 49692 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 18019 47.45% 47.45% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1933 5.09% 52.55% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 292 0.77% 53.31% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 17727 46.69% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 37971 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1882485952500 97.58% 97.58% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 565596500 0.03% 97.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 145516500 0.01% 97.62% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 45879988500 2.38% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1929077054000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.979081 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2309 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 39314 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10555 33.51% 33.51% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1926 6.11% 39.62% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 116 0.37% 39.99% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18905 60.01% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 31502 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10515 45.81% 45.81% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1926 8.39% 54.19% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 116 0.51% 54.70% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10399 45.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22956 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1877342030500 98.36% 98.36% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 564972500 0.03% 98.39% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 56160500 0.00% 98.39% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 30688096500 1.61% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1908651260000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.996210 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.609951 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.764127 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.74% 0.74% # number of syscalls executed -system.cpu1.kern.syscall::3 15 11.03% 11.76% # number of syscalls executed -system.cpu1.kern.syscall::6 14 10.29% 22.06% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.74% 22.79% # number of syscalls executed -system.cpu1.kern.syscall::17 7 5.15% 27.94% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.21% 30.15% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.47% 31.62% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.21% 33.82% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.21% 36.03% # number of syscalls executed -system.cpu1.kern.syscall::33 5 3.68% 39.71% # number of syscalls executed -system.cpu1.kern.syscall::45 23 16.91% 56.62% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.21% 58.82% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.47% 60.29% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.74% 61.03% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.47% 62.50% # number of syscalls executed -system.cpu1.kern.syscall::71 33 24.26% 86.76% # number of syscalls executed -system.cpu1.kern.syscall::74 11 8.09% 94.85% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.74% 95.59% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.47% 97.06% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.21% 99.26% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.74% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 136 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.550066 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.728716 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 12 10.91% 10.91% # number of syscalls executed +system.cpu1.kern.syscall::6 10 9.09% 20.00% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.91% 20.91% # number of syscalls executed +system.cpu1.kern.syscall::17 7 6.36% 27.27% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.73% 30.00% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.73% 32.73% # number of syscalls executed +system.cpu1.kern.syscall::33 5 4.55% 37.27% # number of syscalls executed +system.cpu1.kern.syscall::45 21 19.09% 56.36% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.73% 59.09% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.91% 60.00% # number of syscalls executed +system.cpu1.kern.syscall::71 31 28.18% 88.18% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.09% 97.27% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.73% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 110 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 191 0.37% 0.37% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1171 2.27% 2.65% # number of callpals executed -system.cpu1.kern.callpal::tbi 5 0.01% 2.66% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.67% # number of callpals executed -system.cpu1.kern.callpal::swpipl 44279 85.92% 88.59% # number of callpals executed -system.cpu1.kern.callpal::rdps 2440 4.73% 93.33% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.33% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 93.34% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.34% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.34% # number of callpals executed -system.cpu1.kern.callpal::rti 3187 6.18% 99.53% # number of callpals executed -system.cpu1.kern.callpal::callsys 197 0.38% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 45 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 20 0.06% 0.06% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed +system.cpu1.kern.callpal::swpctx 440 1.35% 1.42% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.43% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.45% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26890 82.68% 84.13% # number of callpals executed +system.cpu1.kern.callpal::rdps 2393 7.36% 91.49% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.50% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.02% 91.51% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.52% # number of callpals executed +system.cpu1.kern.callpal::rti 2569 7.90% 99.42% # number of callpals executed +system.cpu1.kern.callpal::callsys 144 0.44% 99.86% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.14% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 51536 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1550 # number of protection mode switches -system.cpu1.kern.mode_switch::user 578 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2436 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 794 -system.cpu1.kern.mode_good::user 578 -system.cpu1.kern.mode_good::idle 216 -system.cpu1.kern.mode_switch_good::kernel 0.512258 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 32523 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 900 # number of protection mode switches +system.cpu1.kern.mode_switch::user 488 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2082 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 529 +system.cpu1.kern.mode_good::user 488 +system.cpu1.kern.mode_good::idle 41 +system.cpu1.kern.mode_switch_good::kernel 0.587778 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.088670 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.347940 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4980780500 0.26% 0.26% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 920793000 0.05% 0.31% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1923175472500 99.69% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1172 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.019693 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.304899 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 2122812500 0.11% 0.11% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 785064000 0.04% 0.15% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1905743375500 99.85% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 441 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index d6b9de05c..9b89e5da4 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.876794 # Nu sim_ticks 1876794488000 # Number of ticks simulated final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142986 # Simulator instruction rate (inst/s) -host_op_rate 142986 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5064945596 # Simulator tick rate (ticks/s) -host_mem_usage 335448 # Number of bytes of host memory used -host_seconds 370.55 # Real time elapsed on the host +host_inst_rate 156335 # Simulator instruction rate (inst/s) +host_op_rate 156335 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5537786455 # Simulator tick rate (ticks/s) +host_mem_usage 329540 # Number of bytes of host memory used +host_seconds 338.91 # Real time elapsed on the host sim_insts 52982943 # Number of instructions simulated sim_ops 52982943 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 555ee4194..f41b81651 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.843617 # Number of seconds simulated -sim_ticks 1843616607000 # Number of ticks simulated -final_tick 1843616607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841599 # Number of seconds simulated +sim_ticks 1841599161000 # Number of ticks simulated +final_tick 1841599161000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 248643 # Simulator instruction rate (inst/s) -host_op_rate 248643 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6281412703 # Simulator tick rate (ticks/s) -host_mem_usage 335188 # Number of bytes of host memory used -host_seconds 293.50 # Real time elapsed on the host -sim_insts 72977545 # Number of instructions simulated -sim_ops 72977545 # Number of ops (including micro ops) simulated +host_inst_rate 245408 # Simulator instruction rate (inst/s) +host_op_rate 245408 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6773643024 # Simulator tick rate (ticks/s) +host_mem_usage 331844 # Number of bytes of host memory used +host_seconds 271.88 # Real time elapsed on the host +sim_insts 66720805 # Number of instructions simulated +sim_ops 66720805 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 493824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20821760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 146560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1538304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 275200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2511424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 472448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20115392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2145088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 298752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2611904 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25788032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 493824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 146560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 275200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 915584 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7477248 # Number of bytes written to this memory -system.physmem.bytes_written::total 7477248 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7716 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 325340 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 24036 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4300 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39241 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25791552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 472448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 298752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 918208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7488832 # Number of bytes written to this memory +system.physmem.bytes_written::total 7488832 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7382 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 314303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 33517 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4668 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 40811 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402938 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116832 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116832 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 267856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 11293975 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 834395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 149272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1362227 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 402993 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117013 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117013 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 256542 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10922785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1164796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 162224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1418280 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13987741 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 267856 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79496 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 149272 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 496624 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4055750 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4055750 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4055750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 267856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 11293975 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 834395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 149272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1362227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 14004976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 256542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79826 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 162224 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4066483 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4066483 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4066483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 256542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10922785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1164796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 162224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1418280 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18043491 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 69882 # Number of read requests accepted -system.physmem.writeReqs 42058 # Number of write requests accepted -system.physmem.readBursts 69882 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 42058 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 4471360 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1088 # Total number of bytes read from write queue -system.physmem.bytesWritten 2689856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 4472448 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2691712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 17 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 18071459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 81308 # Number of read requests accepted +system.physmem.writeReqs 46917 # Number of write requests accepted +system.physmem.readBursts 81308 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 46917 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5202560 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1152 # Total number of bytes read from write queue +system.physmem.bytesWritten 3000896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5203712 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 3002688 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 18 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4380 # Per bank write bursts -system.physmem.perBankRdBursts::1 4144 # Per bank write bursts -system.physmem.perBankRdBursts::2 4349 # Per bank write bursts -system.physmem.perBankRdBursts::3 4638 # Per bank write bursts -system.physmem.perBankRdBursts::4 3888 # Per bank write bursts -system.physmem.perBankRdBursts::5 4647 # Per bank write bursts -system.physmem.perBankRdBursts::6 4275 # Per bank write bursts -system.physmem.perBankRdBursts::7 4272 # Per bank write bursts -system.physmem.perBankRdBursts::8 4610 # Per bank write bursts -system.physmem.perBankRdBursts::9 4314 # Per bank write bursts -system.physmem.perBankRdBursts::10 4557 # Per bank write bursts -system.physmem.perBankRdBursts::11 4086 # Per bank write bursts -system.physmem.perBankRdBursts::12 4064 # Per bank write bursts -system.physmem.perBankRdBursts::13 4584 # Per bank write bursts -system.physmem.perBankRdBursts::14 4708 # Per bank write bursts -system.physmem.perBankRdBursts::15 4349 # Per bank write bursts -system.physmem.perBankWrBursts::0 2696 # Per bank write bursts -system.physmem.perBankWrBursts::1 2323 # Per bank write bursts -system.physmem.perBankWrBursts::2 2672 # Per bank write bursts -system.physmem.perBankWrBursts::3 3008 # Per bank write bursts -system.physmem.perBankWrBursts::4 2271 # Per bank write bursts -system.physmem.perBankWrBursts::5 2656 # Per bank write bursts -system.physmem.perBankWrBursts::6 2498 # Per bank write bursts -system.physmem.perBankWrBursts::7 2402 # Per bank write bursts -system.physmem.perBankWrBursts::8 3013 # Per bank write bursts -system.physmem.perBankWrBursts::9 2448 # Per bank write bursts -system.physmem.perBankWrBursts::10 2834 # Per bank write bursts -system.physmem.perBankWrBursts::11 2439 # Per bank write bursts -system.physmem.perBankWrBursts::12 2426 # Per bank write bursts -system.physmem.perBankWrBursts::13 2711 # Per bank write bursts -system.physmem.perBankWrBursts::14 2911 # Per bank write bursts -system.physmem.perBankWrBursts::15 2721 # Per bank write bursts +system.physmem.perBankRdBursts::0 4879 # Per bank write bursts +system.physmem.perBankRdBursts::1 4860 # Per bank write bursts +system.physmem.perBankRdBursts::2 4840 # Per bank write bursts +system.physmem.perBankRdBursts::3 5116 # Per bank write bursts +system.physmem.perBankRdBursts::4 5145 # Per bank write bursts +system.physmem.perBankRdBursts::5 5201 # Per bank write bursts +system.physmem.perBankRdBursts::6 5134 # Per bank write bursts +system.physmem.perBankRdBursts::7 5033 # Per bank write bursts +system.physmem.perBankRdBursts::8 5242 # Per bank write bursts +system.physmem.perBankRdBursts::9 4887 # Per bank write bursts +system.physmem.perBankRdBursts::10 5474 # Per bank write bursts +system.physmem.perBankRdBursts::11 5136 # Per bank write bursts +system.physmem.perBankRdBursts::12 4904 # Per bank write bursts +system.physmem.perBankRdBursts::13 4973 # Per bank write bursts +system.physmem.perBankRdBursts::14 5564 # Per bank write bursts +system.physmem.perBankRdBursts::15 4902 # Per bank write bursts +system.physmem.perBankWrBursts::0 2770 # Per bank write bursts +system.physmem.perBankWrBursts::1 2825 # Per bank write bursts +system.physmem.perBankWrBursts::2 2866 # Per bank write bursts +system.physmem.perBankWrBursts::3 3058 # Per bank write bursts +system.physmem.perBankWrBursts::4 2994 # Per bank write bursts +system.physmem.perBankWrBursts::5 2828 # Per bank write bursts +system.physmem.perBankWrBursts::6 3105 # Per bank write bursts +system.physmem.perBankWrBursts::7 2723 # Per bank write bursts +system.physmem.perBankWrBursts::8 3290 # Per bank write bursts +system.physmem.perBankWrBursts::9 2741 # Per bank write bursts +system.physmem.perBankWrBursts::10 3262 # Per bank write bursts +system.physmem.perBankWrBursts::11 2912 # Per bank write bursts +system.physmem.perBankWrBursts::12 2689 # Per bank write bursts +system.physmem.perBankWrBursts::13 2734 # Per bank write bursts +system.physmem.perBankWrBursts::14 3349 # Per bank write bursts +system.physmem.perBankWrBursts::15 2743 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 1842604622000 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 1840587284000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 69882 # Read request sizes (log2) +system.physmem.readPktSize::6 81308 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 42058 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 49770 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5325 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.writePktSize::6 46917 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 63682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5539 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -153,188 +153,204 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 1943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 762 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 39 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 20044 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 357.274795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.112689 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 369.610579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7222 36.03% 36.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4570 22.80% 58.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1644 8.20% 67.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 908 4.53% 71.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 718 3.58% 75.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 515 2.57% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 476 2.37% 80.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 378 1.89% 81.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3613 18.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 20044 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 1835 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 38.063215 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 849.708875 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 1833 99.89% 99.89% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::58 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21624 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 379.368110 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.960357 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 378.240859 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7179 33.20% 33.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4878 22.56% 55.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1948 9.01% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1045 4.83% 69.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 873 4.04% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 450 2.08% 75.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 417 1.93% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 373 1.72% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4461 20.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21624 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2049 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 39.666179 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 981.071588 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2047 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::34816-36863 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 1835 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 1835 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.904087 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.705845 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.745243 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 40 2.18% 2.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 6 0.33% 2.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 1558 84.90% 87.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 20 1.09% 88.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 5 0.27% 88.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 16 0.87% 89.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 75 4.09% 93.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 6 0.33% 94.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 1 0.05% 94.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 15 0.82% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 72 3.92% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 3 0.16% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 2 0.11% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 1 0.05% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 5 0.27% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 1 0.05% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.11% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.11% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.11% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.05% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.11% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 1835 # Writes before turning the bus around for reads -system.physmem.totQLat 876234250 # Total ticks spent queuing -system.physmem.totMemAccLat 2186203000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 349325000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12541.82 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 2049 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2049 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.883846 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.590123 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.999579 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 33 1.61% 1.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 8 0.39% 2.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.05% 2.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 3 0.15% 2.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1695 82.72% 84.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 48 2.34% 87.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 10 0.49% 87.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 15 0.73% 88.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 91 4.44% 92.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 8 0.39% 93.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.05% 93.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 4 0.20% 93.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 2 0.10% 93.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.15% 93.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.10% 93.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.10% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 2 0.10% 94.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.05% 94.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.10% 94.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 13 0.63% 94.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.20% 95.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 77 3.76% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.05% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.10% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.10% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.05% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 2 0.10% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.05% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.05% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.05% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 4 0.20% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.05% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 4 0.20% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2049 # Writes before turning the bus around for reads +system.physmem.totQLat 885699750 # Total ticks spent queuing +system.physmem.totMemAccLat 2409887250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 406450000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10895.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31291.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.46 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.43 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.46 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29645.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.83 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.83 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.63 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.05 # Average write queue length when enqueuing -system.physmem.readRowHits 58965 # Number of row buffer hits during reads -system.physmem.writeRowHits 32885 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.19 # Row buffer hit rate for writes -system.physmem.avgGap 16460645.18 # Average gap between requests -system.physmem.pageHitRate 82.07 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 75547080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 41146875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 269825400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 133008480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89192778480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 36154606095 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 800813931750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 926680844160 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.855224 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1310352812250 # Time in different power states -system.physmem_0.memoryStateTime::REF 45599580000 # Time in different power states +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgWrQLen 7.69 # Average write queue length when enqueuing +system.physmem.readRowHits 69553 # Number of row buffer hits during reads +system.physmem.writeRowHits 37002 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.87 # Row buffer hit rate for writes +system.physmem.avgGap 14354355.89 # Average gap between requests +system.physmem.pageHitRate 83.11 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 80733240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 43918875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 313622400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 150135120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89060552880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 35737868835 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 798596823000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 923983654350 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.983586 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1308907007000 # Time in different power states +system.physmem_0.memoryStateTime::REF 45531980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9807496500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9262769000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 75985560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 41344875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 275121600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 139339440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89192778480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35610008715 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 799074942000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 924409520670 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.996911 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1311143061750 # Time in different power states -system.physmem_1.memoryStateTime::REF 45599580000 # Time in different power states +system.physmem_1.actEnergy 82744200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 44962500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 320439600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 153705600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89060552880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35470252125 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 802756182000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 927888838905 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.649647 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1309307344000 # Time in different power states +system.physmem_1.memoryStateTime::REF 45531980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9002444500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8896844750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4891655 # DTB read hits -system.cpu0.dtb.read_misses 6160 # DTB read misses -system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 428724 # DTB read accesses -system.cpu0.dtb.write_hits 3459344 # DTB write hits +system.cpu0.dtb.read_hits 4808616 # DTB read hits +system.cpu0.dtb.read_misses 6111 # DTB read misses +system.cpu0.dtb.read_acv 122 # DTB read access violations +system.cpu0.dtb.read_accesses 428608 # DTB read accesses +system.cpu0.dtb.write_hits 3411554 # DTB write hits system.cpu0.dtb.write_misses 685 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 165214 # DTB write accesses -system.cpu0.dtb.data_hits 8350999 # DTB hits -system.cpu0.dtb.data_misses 6845 # DTB misses -system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 593938 # DTB accesses -system.cpu0.itb.fetch_hits 2745673 # ITB hits -system.cpu0.itb.fetch_misses 3063 # ITB misses -system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2748736 # ITB accesses +system.cpu0.dtb.write_accesses 164458 # DTB write accesses +system.cpu0.dtb.data_hits 8220170 # DTB hits +system.cpu0.dtb.data_misses 6796 # DTB misses +system.cpu0.dtb.data_acv 206 # DTB access violations +system.cpu0.dtb.data_accesses 593066 # DTB accesses +system.cpu0.itb.fetch_hits 2729287 # ITB hits +system.cpu0.itb.fetch_misses 3056 # ITB misses +system.cpu0.itb.fetch_acv 101 # ITB acv +system.cpu0.itb.fetch_accesses 2732343 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -347,32 +363,32 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928907955 # number of cpu cycles simulated +system.cpu0.numCycles 928788202 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211433 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74803 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6425 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211368 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74795 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1880 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105704 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182590 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73436 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105681 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182557 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73428 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1880 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73436 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148955 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1820384307000 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39982500 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 369735500 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22821848000 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1843615873000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73428 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148937 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818752965500 98.76% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39793500 0.00% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 370197000 0.02% 98.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22435471000 1.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841598427000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694732 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815789 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694808 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815838 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -408,499 +424,499 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4175 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175329 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6784 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175300 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5177 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192244 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5921 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1908 -system.cpu0.kern.mode_good::user 1739 +system.cpu0.kern.callpal::total 192212 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1906 +system.cpu0.kern.mode_good::user 1737 system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.322243 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 30037472000 1.63% 1.63% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2599704500 0.14% 1.77% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810978694500 98.23% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4175 # number of times the context was actually changed -system.cpu0.committedInsts 33609672 # Number of instructions committed -system.cpu0.committedOps 33609672 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31482741 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 165750 # Number of float alu accesses -system.cpu0.num_func_calls 801937 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4632385 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31482741 # number of integer instructions -system.cpu0.num_fp_insts 165750 # number of float instructions -system.cpu0.num_int_register_reads 44252512 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23025410 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 85784 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 87202 # number of times the floating registers were written -system.cpu0.num_mem_refs 8380910 # number of memory refs -system.cpu0.num_load_insts 4912915 # Number of load instructions -system.cpu0.num_store_insts 3467995 # Number of store instructions -system.cpu0.num_idle_cycles 904803576.609886 # Number of idle cycles -system.cpu0.num_busy_cycles 24104378.390114 # Number of busy cycles -system.cpu0.not_idle_fraction 0.025949 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.974051 # Percentage of idle cycles -system.cpu0.Branches 5693464 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1614345 4.80% 4.80% # Class of executed instruction -system.cpu0.op_class::IntAlu 22916205 68.17% 72.97% # Class of executed instruction -system.cpu0.op_class::IntMult 32373 0.10% 73.07% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 73.07% # Class of executed instruction -system.cpu0.op_class::FloatAdd 13074 0.04% 73.11% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1630 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 73.11% # Class of executed instruction -system.cpu0.op_class::MemRead 5044574 15.01% 88.12% # Class of executed instruction -system.cpu0.op_class::MemWrite 3471125 10.33% 98.44% # Class of executed instruction -system.cpu0.op_class::IprAccess 523401 1.56% 100.00% # Class of executed instruction +system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.390854 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29766458500 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2570000000 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809261966500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4176 # number of times the context was actually changed +system.cpu0.committedInsts 30028359 # Number of instructions committed +system.cpu0.committedOps 30028359 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 27949209 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 163605 # Number of float alu accesses +system.cpu0.num_func_calls 796078 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3573160 # number of instructions that are conditional controls +system.cpu0.num_int_insts 27949209 # number of integer instructions +system.cpu0.num_fp_insts 163605 # number of float instructions +system.cpu0.num_int_register_reads 38472094 # number of times the integer registers were read +system.cpu0.num_int_register_writes 20603467 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84586 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86140 # number of times the floating registers were written +system.cpu0.num_mem_refs 8249833 # number of memory refs +system.cpu0.num_load_insts 4829697 # Number of load instructions +system.cpu0.num_store_insts 3420136 # Number of store instructions +system.cpu0.num_idle_cycles 907169648.432742 # Number of idle cycles +system.cpu0.num_busy_cycles 21618553.567258 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023276 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976724 # Percentage of idle cycles +system.cpu0.Branches 4625246 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1572413 5.24% 5.24% # Class of executed instruction +system.cpu0.op_class::IntAlu 19517057 64.98% 70.22% # Class of executed instruction +system.cpu0.op_class::IntMult 31821 0.11% 70.32% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 70.32% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12868 0.04% 70.36% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1602 0.01% 70.37% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.37% # Class of executed instruction +system.cpu0.op_class::MemRead 4960051 16.51% 86.88% # Class of executed instruction +system.cpu0.op_class::MemWrite 3423231 11.40% 98.28% # Class of executed instruction +system.cpu0.op_class::IprAccess 516318 1.72% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 33616727 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1394181 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997813 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13501786 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1394693 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.680830 # Average number of references to valid blocks. +system.cpu0.op_class::total 30035361 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1394566 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13521910 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1395078 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.692583 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 255.971999 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 119.140649 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 136.885165 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.499945 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.232697 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.267354 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 257.707457 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 77.564418 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.725941 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.503335 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.151493 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.345168 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 64418479 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 64418479 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4048167 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1034034 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2748996 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7831197 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3168136 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 783371 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1326904 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5278411 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114770 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19408 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 58589 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 192767 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123716 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21423 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 54189 # 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number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 166271 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 38690 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 668713 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 873674 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9504 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2145 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7260 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18909 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 22 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 25 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 896057 # 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number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 31601504728 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28793000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 133300000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 162093000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 511000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 511000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4446549500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 38230127228 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 42676676728 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4446549500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 38230127228 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 42676676728 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4777953 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1121376 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3293503 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 9192832 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3334407 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 822061 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1995617 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6152085 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124274 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21553 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 65849 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 211676 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123719 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21423 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 54211 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199353 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8112360 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 1943437 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5289120 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15344917 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8112360 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 1943437 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5289120 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15344917 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.152740 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.077888 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.165328 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.148119 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049865 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.047065 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.335091 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.142013 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076476 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099522 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.110252 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089330 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000024 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000406 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000125 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.110456 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.064850 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.229380 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.145671 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.110456 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.064850 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.229380 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.145671 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 26509.434178 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16087.552593 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8133.730405 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 55083.031791 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 44070.239741 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 36170.819697 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13423.310023 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 18360.881543 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8572.267174 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 23227.272727 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20440 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35281.115114 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31511.289979 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19092.070371 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35281.115114 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31511.289979 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19092.070371 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1649152 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2017 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 58664 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 28.111823 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 183.363636 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 836302 # number of writebacks -system.cpu0.dcache.writebacks::total 836302 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 286455 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 286455 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 571181 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 571181 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1840 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1840 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 857636 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 857636 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 857636 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 857636 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 87342 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 258052 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 345394 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 38690 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 97532 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 136222 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2145 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5420 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7565 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 22 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 22 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 126032 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 355584 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 481616 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 126032 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 355584 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 481616 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1346 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1396 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2742 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1629 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 1971 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3600 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2975 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3367 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6342 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2228045000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4632792500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6860837500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2092472500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4580895301 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6673367801 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 26648000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69159500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95807500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 489000 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 296833500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 314974000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 611807500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.077888 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.078352 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037572 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047065 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048873 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022142 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099522 # 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average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 225626.074499 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223124.544128 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 99775.966387 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 93547.371547 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96469.173762 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 969392 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.185439 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43108744 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 969903 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 44.446449 # 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miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050308 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.321337 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.138254 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075910 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101161 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.112247 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090012 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000470 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000135 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109632 # 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number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 21576 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 127611 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 325967 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 453578 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 127611 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 325967 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 453578 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 127611 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 325967 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 453578 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1810322000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4484314476 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6294636476 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1810322000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4484314476 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6294636476 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1810322000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4484314476 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6294636476 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.017096 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.107958 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010285 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.017096 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.107958 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010285 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.017096 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.107958 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010285 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14186.253536 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13756.958453 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13877.737624 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14186.253536 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13756.958453 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13877.737624 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14186.253536 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13756.958453 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13877.737624 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 969876 # number of writebacks +system.cpu0.icache.writebacks::total 969876 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22058 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 22058 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 22058 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 22058 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 22058 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 22058 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 126603 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 334632 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 461235 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 126603 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 334632 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 461235 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 126603 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 334632 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 461235 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1685858000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4399066985 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6084924985 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1685858000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4399066985 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6084924985 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1685858000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4399066985 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6084924985 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016781 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.108090 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011339 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016781 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.108090 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011339 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016781 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.108090 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011339 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13316.098355 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13145.984201 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13192.678320 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13316.098355 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13145.984201 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13192.678320 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13316.098355 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13145.984201 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13192.678320 # average overall mshr miss latency system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1140904 # DTB read hits -system.cpu1.dtb.read_misses 1286 # DTB read misses -system.cpu1.dtb.read_acv 30 # DTB read access violations -system.cpu1.dtb.read_accesses 118136 # DTB read accesses -system.cpu1.dtb.write_hits 843894 # DTB write hits -system.cpu1.dtb.write_misses 157 # DTB write misses -system.cpu1.dtb.write_acv 18 # DTB write access violations -system.cpu1.dtb.write_accesses 48616 # DTB write accesses -system.cpu1.dtb.data_hits 1984798 # DTB hits -system.cpu1.dtb.data_misses 1443 # DTB misses -system.cpu1.dtb.data_acv 48 # DTB access violations -system.cpu1.dtb.data_accesses 166752 # DTB accesses -system.cpu1.itb.fetch_hits 760414 # ITB hits -system.cpu1.itb.fetch_misses 659 # ITB misses -system.cpu1.itb.fetch_acv 28 # ITB acv -system.cpu1.itb.fetch_accesses 761073 # ITB accesses +system.cpu1.dtb.read_hits 1184324 # DTB read hits +system.cpu1.dtb.read_misses 1316 # DTB read misses +system.cpu1.dtb.read_acv 34 # DTB read access violations +system.cpu1.dtb.read_accesses 141546 # DTB read accesses +system.cpu1.dtb.write_hits 885341 # DTB write hits +system.cpu1.dtb.write_misses 169 # DTB write misses +system.cpu1.dtb.write_acv 22 # DTB write access violations +system.cpu1.dtb.write_accesses 57820 # DTB write accesses +system.cpu1.dtb.data_hits 2069665 # DTB hits +system.cpu1.dtb.data_misses 1485 # DTB misses +system.cpu1.dtb.data_acv 56 # DTB access violations +system.cpu1.dtb.data_accesses 199366 # DTB accesses +system.cpu1.itb.fetch_hits 852668 # ITB hits +system.cpu1.itb.fetch_misses 656 # ITB misses +system.cpu1.itb.fetch_acv 33 # ITB acv +system.cpu1.itb.fetch_accesses 853324 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -913,7 +929,7 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953506414 # number of cpu cycles simulated +system.cpu1.numCycles 953375365 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -933,94 +949,94 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu1.committedInsts 7462812 # Number of instructions committed -system.cpu1.committedOps 7462812 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6940057 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 40181 # Number of float alu accesses -system.cpu1.num_func_calls 208293 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 930314 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6940057 # number of integer instructions -system.cpu1.num_fp_insts 40181 # number of float instructions -system.cpu1.num_int_register_reads 9712470 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5067319 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 20912 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 21313 # number of times the floating registers were written -system.cpu1.num_mem_refs 1991766 # number of memory refs -system.cpu1.num_load_insts 1145591 # Number of load instructions -system.cpu1.num_store_insts 846175 # Number of store instructions -system.cpu1.num_idle_cycles 924284293.570885 # Number of idle cycles -system.cpu1.num_busy_cycles 29222120.429115 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030647 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969353 # Percentage of idle cycles -system.cpu1.Branches 1204252 # Number of branches fetched -system.cpu1.op_class::No_OpClass 396048 5.31% 5.31% # Class of executed instruction -system.cpu1.op_class::IntAlu 4903561 65.69% 71.00% # Class of executed instruction -system.cpu1.op_class::IntMult 7744 0.10% 71.10% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 71.10% # Class of executed instruction -system.cpu1.op_class::FloatAdd 3327 0.04% 71.15% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::FloatDiv 440 0.01% 71.15% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.15% # Class of executed instruction -system.cpu1.op_class::MemRead 1174639 15.74% 86.89% # Class of executed instruction -system.cpu1.op_class::MemWrite 847384 11.35% 98.24% # Class of executed instruction -system.cpu1.op_class::IprAccess 131160 1.76% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7542911 # Number of instructions committed +system.cpu1.committedOps 7542911 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7009980 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 44709 # Number of float alu accesses +system.cpu1.num_func_calls 205791 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 911955 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7009980 # number of integer instructions +system.cpu1.num_fp_insts 44709 # number of float instructions +system.cpu1.num_int_register_reads 9753806 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5113025 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24116 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24503 # number of times the floating registers were written +system.cpu1.num_mem_refs 2076660 # number of memory refs +system.cpu1.num_load_insts 1189039 # Number of load instructions +system.cpu1.num_store_insts 887621 # Number of store instructions +system.cpu1.num_idle_cycles 923368497.825425 # Number of idle cycles +system.cpu1.num_busy_cycles 30006867.174575 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031474 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968526 # Percentage of idle cycles +system.cpu1.Branches 1183564 # Number of branches fetched +system.cpu1.op_class::No_OpClass 404590 5.36% 5.36% # Class of executed instruction +system.cpu1.op_class::IntAlu 4887103 64.78% 70.14% # Class of executed instruction +system.cpu1.op_class::IntMult 8470 0.11% 70.25% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.25% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5131 0.07% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 70.33% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::MemRead 1217523 16.14% 86.47% # Class of executed instruction +system.cpu1.op_class::MemWrite 888839 11.78% 98.25% # Class of executed instruction +system.cpu1.op_class::IprAccess 131986 1.75% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7464303 # Class of executed instruction -system.cpu2.branchPred.lookups 11115445 # Number of BP lookups -system.cpu2.branchPred.condPredicted 10184701 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 190030 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 8583596 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6500261 # Number of BTB hits +system.cpu1.op_class::total 7544452 # Class of executed instruction +system.cpu2.branchPred.lookups 10195062 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9245801 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 194837 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7645666 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5489178 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 75.728879 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 358939 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 14100 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 1769440 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 184650 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 1584790 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 83567 # Number of mispredicted indirect branches. +system.cpu2.branchPred.BTBHitPct 71.794635 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 367323 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 14555 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 1840410 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 186758 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 1653652 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 86236 # Number of mispredicted indirect branches. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3745527 # DTB read hits -system.cpu2.dtb.read_misses 14326 # DTB read misses -system.cpu2.dtb.read_acv 141 # DTB read access violations -system.cpu2.dtb.read_accesses 264538 # DTB read accesses -system.cpu2.dtb.write_hits 2181134 # DTB write hits -system.cpu2.dtb.write_misses 3579 # DTB write misses -system.cpu2.dtb.write_acv 134 # DTB write access violations -system.cpu2.dtb.write_accesses 94734 # DTB write accesses -system.cpu2.dtb.data_hits 5926661 # DTB hits -system.cpu2.dtb.data_misses 17905 # DTB misses -system.cpu2.dtb.data_acv 275 # DTB access violations -system.cpu2.dtb.data_accesses 359272 # DTB accesses -system.cpu2.itb.fetch_hits 551804 # ITB hits -system.cpu2.itb.fetch_misses 2698 # ITB misses -system.cpu2.itb.fetch_acv 198 # ITB acv -system.cpu2.itb.fetch_accesses 554502 # ITB accesses +system.cpu2.dtb.read_hits 3794321 # DTB read hits +system.cpu2.dtb.read_misses 14980 # DTB read misses +system.cpu2.dtb.read_acv 154 # DTB read access violations +system.cpu2.dtb.read_accesses 231448 # DTB read accesses +system.cpu2.dtb.write_hits 2188085 # DTB write hits +system.cpu2.dtb.write_misses 3764 # DTB write misses +system.cpu2.dtb.write_acv 156 # DTB write access violations +system.cpu2.dtb.write_accesses 84759 # DTB write accesses +system.cpu2.dtb.data_hits 5982406 # DTB hits +system.cpu2.dtb.data_misses 18744 # DTB misses +system.cpu2.dtb.data_acv 310 # DTB access violations +system.cpu2.dtb.data_accesses 316207 # DTB accesses +system.cpu2.itb.fetch_hits 533759 # ITB hits +system.cpu2.itb.fetch_misses 2736 # ITB misses +system.cpu2.itb.fetch_acv 191 # ITB acv +system.cpu2.itb.fetch_accesses 536495 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1033,303 +1049,303 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 32148288 # number of cpu cycles simulated +system.cpu2.numCycles 30327275 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9118770 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 42633402 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 11115445 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 7043850 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 20872660 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 537018 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 10698 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1962 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 54145 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 92611 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 906 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3019400 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 130811 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.icacheStallCycles 9354335 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 40099246 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 10195062 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6043259 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 18967134 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 549482 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 7 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 11119 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1939 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 54610 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 90342 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 596 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3095865 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 133552 # Number of outstanding Icache misses that were squashed system.cpu2.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 30420027 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.401491 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.386543 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::samples 28754585 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.394534 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.444600 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20612041 67.76% 67.76% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 327280 1.08% 68.83% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 509415 1.67% 70.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5051332 16.61% 87.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 910040 2.99% 90.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 211501 0.70% 90.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 256047 0.84% 91.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 439619 1.45% 93.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2102752 6.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 19879004 69.13% 69.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 339943 1.18% 70.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 516791 1.80% 72.11% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4053539 14.10% 86.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 887171 3.09% 89.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 213563 0.74% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 261735 0.91% 90.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 444517 1.55% 92.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2158322 7.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 30420027 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.345755 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.326148 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7385112 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 13918236 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8048801 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 564027 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 258008 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 221892 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 11066 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 38888307 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 34887 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 258008 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7685688 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4963925 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6082795 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8292905 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2890873 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 37903882 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 59292 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 377519 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 110958 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1815831 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 25463853 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 47138476 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 47075647 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 58641 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 22316309 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 3147544 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 533093 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 73531 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3880120 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3861851 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2321017 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 521824 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 313958 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 35078134 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 686210 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34388477 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 25878 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 3859283 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1728855 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 496373 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 30420027 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.130455 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.630155 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 28754585 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.336168 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.322217 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7569976 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 12996616 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7107544 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 570612 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 263955 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 225265 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 11264 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36283979 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 35882 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 263955 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7872857 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4931794 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5918579 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7355041 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2166486 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35279837 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 60983 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 402801 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 76926 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1084115 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 23748051 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 43586446 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 43526101 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56436 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20540056 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 3207995 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 542145 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 75307 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3912291 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3917277 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2333144 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 542030 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 329847 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32377023 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 701408 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 31676973 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 27053 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 3928896 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1754776 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 507029 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 28754585 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.101632 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.635117 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 18175934 59.75% 59.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2731876 8.98% 68.73% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1376382 4.52% 73.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5800287 19.07% 92.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1083705 3.56% 95.88% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 612376 2.01% 97.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 420135 1.38% 99.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 169190 0.56% 99.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 50142 0.16% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17376990 60.43% 60.43% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2804831 9.75% 70.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1408095 4.90% 75.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4807285 16.72% 91.80% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1079199 3.75% 95.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 630267 2.19% 97.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 421060 1.46% 99.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 175258 0.61% 99.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 51600 0.18% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 30420027 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 28754585 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 80804 19.32% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 207140 49.52% 68.84% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 130362 31.16% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 83759 19.66% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 19.66% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 210235 49.34% 69.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 132097 31.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 3134 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 27917447 81.18% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21186 0.06% 81.25% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.25% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 22118 0.06% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1566 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.32% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3912960 11.38% 92.70% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2212878 6.43% 99.14% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 297188 0.86% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2450 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 25141274 79.37% 79.38% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20994 0.07% 79.44% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 79.44% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20528 0.06% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.51% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3966361 12.52% 92.03% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2221145 7.01% 99.04% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 302997 0.96% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34388477 # Type of FU issued -system.cpu2.iq.rate 1.069683 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 418306 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.012164 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 99374264 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39499421 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 33606798 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 266901 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 130860 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 122949 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 34661254 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 142395 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 213891 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 31676973 # Type of FU issued +system.cpu2.iq.rate 1.044504 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 426091 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.013451 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 92299555 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 36885759 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 30885842 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 262120 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 128344 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 120451 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 31960571 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 140043 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 222851 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 829369 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1314 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6796 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 267816 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 843917 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1448 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6897 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 272853 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4168 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 214093 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4760 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 213103 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 258008 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4262177 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 221870 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 37207095 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 66855 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3861851 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2321017 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 613182 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 13352 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 173159 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6796 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 74128 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 200909 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 275037 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 34112414 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3770128 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 276063 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 263955 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4308277 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 202891 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34565468 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 70386 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3917277 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2333144 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 625709 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 13182 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 148814 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6897 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 76158 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 205534 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 281692 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 31394525 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3819678 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 282448 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1442751 # number of nop insts executed -system.cpu2.iew.exec_refs 5960966 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7830155 # Number of branches executed -system.cpu2.iew.exec_stores 2190838 # Number of stores executed -system.cpu2.iew.exec_rate 1.061096 # Inst execution rate -system.cpu2.iew.wb_sent 33803794 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 33729747 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 19634882 # num instructions producing a value -system.cpu2.iew.wb_consumers 23447045 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.049193 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.837414 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 4049200 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 189837 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 246514 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 29720868 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.113415 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.846179 # Number of insts commited each cycle +system.cpu2.iew.exec_nop 1487037 # number of nop insts executed +system.cpu2.iew.exec_refs 6017890 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6848661 # Number of branches executed +system.cpu2.iew.exec_stores 2198212 # Number of stores executed +system.cpu2.iew.exec_rate 1.035191 # Inst execution rate +system.cpu2.iew.wb_sent 31083503 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 31006293 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17785830 # num instructions producing a value +system.cpu2.iew.wb_consumers 21615859 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.022390 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.822814 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 4127890 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 194379 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 252373 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 28042775 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.083004 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.865926 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18948933 63.76% 63.76% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2226621 7.49% 71.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1117677 3.76% 75.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5469793 18.40% 93.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 585496 1.97% 95.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 200130 0.67% 96.06% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 163612 0.55% 96.61% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 172854 0.58% 97.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 835752 2.81% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18161783 64.76% 64.76% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2276613 8.12% 72.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1151869 4.11% 76.99% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4491226 16.02% 93.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 562178 2.00% 95.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 204579 0.73% 95.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 167176 0.60% 96.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 177068 0.63% 96.97% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 850283 3.03% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 29720868 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 33091654 # Number of instructions committed -system.cpu2.commit.committedOps 33091654 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 28042775 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30370432 # Number of instructions committed +system.cpu2.commit.committedOps 30370432 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5085683 # Number of memory references committed -system.cpu2.commit.loads 3032482 # Number of loads committed -system.cpu2.commit.membars 66632 # Number of memory barriers committed -system.cpu2.commit.branches 7528249 # Number of branches committed -system.cpu2.commit.fp_insts 118326 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 31611835 # Number of committed integer instructions. -system.cpu2.commit.function_calls 236844 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1189725 3.60% 3.60% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 26406955 79.80% 83.39% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20610 0.06% 83.46% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.46% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 21680 0.07% 83.52% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.52% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.52% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.52% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1566 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.53% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3099114 9.37% 92.89% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2054816 6.21% 99.10% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 297188 0.90% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5133651 # Number of memory references committed +system.cpu2.commit.loads 3073360 # Number of loads committed +system.cpu2.commit.membars 68499 # Number of memory barriers committed +system.cpu2.commit.branches 6541282 # Number of branches committed +system.cpu2.commit.fp_insts 116010 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28852886 # Number of committed integer instructions. +system.cpu2.commit.function_calls 241096 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1223345 4.03% 4.03% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 23598567 77.70% 81.73% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20428 0.07% 81.80% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 81.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20084 0.07% 81.86% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 81.86% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 81.86% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 81.86% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1224 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3141859 10.35% 92.21% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2061928 6.79% 99.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 302997 1.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 33091654 # Class of committed instruction -system.cpu2.commit.bw_lim_events 835752 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 65950880 # The number of ROB reads -system.cpu2.rob.rob_writes 74981980 # The number of ROB writes -system.cpu2.timesIdled 163418 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1728261 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1747565688 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31905061 # Number of Instructions Simulated -system.cpu2.committedOps 31905061 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.007623 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.007623 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.992434 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.992434 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 44683951 # number of integer regfile reads -system.cpu2.int_regfile_writes 23750131 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73395 # number of floating regfile reads -system.cpu2.fp_regfile_writes 76222 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5369196 # number of misc regfile reads -system.cpu2.misc_regfile_writes 267799 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 30370432 # Class of committed instruction +system.cpu2.commit.bw_lim_events 850283 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 61616016 # The number of ROB reads +system.cpu2.rob.rob_writes 69709723 # The number of ROB writes +system.cpu2.timesIdled 166720 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1572690 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745481695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 29149535 # Number of Instructions Simulated +system.cpu2.committedOps 29149535 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.040403 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.040403 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.961166 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.961166 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 41087551 # number of integer regfile reads +system.cpu2.int_regfile_writes 22005301 # number of integer regfile writes +system.cpu2.fp_regfile_reads 71153 # number of floating regfile reads +system.cpu2.fp_regfile_writes 74234 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4377642 # number of misc regfile reads +system.cpu2.misc_regfile_writes 272877 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1344,9 +1360,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7317 # Transaction distribution system.iobus.trans_dist::ReadResp 7317 # Transaction distribution -system.iobus.trans_dist::WriteReq 51364 # Transaction distribution -system.iobus.trans_dist::WriteResp 51364 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5196 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51362 # Transaction distribution +system.iobus.trans_dist::WriteResp 51362 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1355,11 +1371,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1825 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117362 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1368,35 +1384,35 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 45584 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707192 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2556000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2373500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 130500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 135500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 65000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 56000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6361000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5872500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2150000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 2528000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 80490654 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 89904673 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9084000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9173000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 15688000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17468000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.261471 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254561 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694927317000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.261471 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078842 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078842 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1693898501000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254561 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078410 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078410 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1410,14 +1426,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9857962 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9857962 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 1957317692 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 1957317692 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 1967175654 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1967175654 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 1967175654 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1967175654 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9598462 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9598462 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 2019796211 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2019796211 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 2029394673 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 2029394673 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 2029394673 # number of overall miss cycles +system.iocache.overall_miss_latency::total 2029394673 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1434,14 +1450,14 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 56982.439306 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 56982.439306 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 47105.258279 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 47105.258279 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 47146.211001 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 47146.211001 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 47146.211001 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 47146.211001 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55482.439306 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 55482.439306 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 48608.880704 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 48608.880704 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 48637.379820 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 48637.379820 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 48637.379820 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 48637.379820 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1450,469 +1466,475 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 68 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 68 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 15504 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 15504 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 15572 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 15572 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 15572 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 15572 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6457962 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 6457962 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1181451904 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1181451904 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 1187909866 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1187909866 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 1187909866 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1187909866 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.393064 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.393064 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.373123 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.373123 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.373206 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.373206 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.373206 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.373206 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 94970.029412 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 94970.029412 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76203.038184 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76203.038184 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76284.990110 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76284.990110 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76284.990110 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76284.990110 # average overall mshr miss latency -system.l2c.tags.replacements 337717 # number of replacements -system.l2c.tags.tagsinuse 65421.749224 # Cycle average of tags in use -system.l2c.tags.total_refs 4019101 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402879 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.975951 # Average number of references to valid blocks. +system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17280 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 17280 # 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number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1160901055 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415818 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.415818 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415818 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.415818 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 87120.885714 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 87120.885714 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66828.853762 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66828.853762 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66910.723631 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 66910.723631 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66910.723631 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 66910.723631 # average overall mshr miss latency +system.l2c.tags.replacements 337756 # number of replacements +system.l2c.tags.tagsinuse 65421.322565 # Cycle average of tags in use +system.l2c.tags.total_refs 4020988 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402918 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.979668 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54773.516183 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2590.636201 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2882.802644 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 510.736952 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 556.623198 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2023.578800 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2083.855246 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.835778 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.039530 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043988 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007793 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008493 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.030877 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.031797 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998257 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54641.026539 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2330.416055 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2713.129703 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 574.927105 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 600.162086 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2250.445944 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2311.215132 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.833756 # 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Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55335 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 987 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5975 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2686 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55336 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38519512 # Number of tag accesses -system.l2c.tags.data_accesses 38519512 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 836302 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 836302 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 969066 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 969066 # number of WritebackClean hits +system.l2c.tags.tag_accesses 38533534 # Number of tag accesses +system.l2c.tags.data_accesses 38533534 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 836681 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 836681 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 969577 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 969577 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 7 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 11 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 19 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 19 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 91578 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 24802 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 70520 # 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mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.238156 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.110776 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034440 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018143 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.238156 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.110776 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034440 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 38437.500000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 38437.500000 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 19500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66751.701629 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 79440.075298 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 74003.024218 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72291.902481 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73617.609254 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73180.402010 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 65365.897321 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 65720.457881 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 70542.653738 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 207382.404951 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 205358.178654 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 206160.070053 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91585.122999 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 94234.096353 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 93160.335549 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 823896 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 379632 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 408 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.trans_dist::ReadReq 7144 # Transaction distribution -system.membus.trans_dist::ReadResp 295030 # Transaction distribution -system.membus.trans_dist::WriteReq 9812 # Transaction distribution -system.membus.trans_dist::WriteResp 9812 # Transaction distribution -system.membus.trans_dist::WritebackDirty 116832 # Transaction distribution -system.membus.trans_dist::CleanEvict 261846 # Transaction distribution -system.membus.trans_dist::UpgradeReq 193 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 117 # Transaction distribution -system.membus.trans_dist::ReadExReq 115481 # Transaction distribution -system.membus.trans_dist::ReadExResp 115481 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 287900 # Transaction distribution -system.membus.trans_dist::BadAddressError 14 # Transaction distribution +system.membus.trans_dist::ReadResp 295138 # Transaction distribution +system.membus.trans_dist::WriteReq 9810 # Transaction distribution +system.membus.trans_dist::WriteResp 9810 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117013 # Transaction distribution +system.membus.trans_dist::CleanEvict 261704 # Transaction distribution +system.membus.trans_dist::UpgradeReq 179 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.membus.trans_dist::UpgradeResp 113 # Transaction distribution +system.membus.trans_dist::ReadExReq 115428 # Transaction distribution +system.membus.trans_dist::ReadExResp 115428 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288010 # Transaction distribution +system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 26048 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143608 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 28 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1177548 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109578 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109578 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1287126 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30619392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30664976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2664448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33329424 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 142 # Total snoops (count) -system.membus.snoop_fanout::samples 840769 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.trans_dist::InvalidateResp 24272 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143724 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1177664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 107800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 107800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1285464 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30633664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30679232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33343552 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 157 # Total snoops (count) +system.membus.snoop_fanout::samples 742227 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001296 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.035978 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 840769 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 741265 99.87% 99.87% # Request fanout histogram +system.membus.snoop_fanout::1 962 0.13% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 840769 # Request fanout histogram -system.membus.reqLayer0.occupancy 11262500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 742227 # Request fanout histogram +system.membus.reqLayer0.occupancy 10965500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 344258394 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 390337877 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 375059750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 436169750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 358538 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 370538 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4728439 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2363791 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1687 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1128 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1128 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4730181 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2364664 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1038 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1038 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2069439 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 9812 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 9812 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 878363 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 969392 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 601395 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 35 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 25 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 60 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302550 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302550 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 970097 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1092227 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 14 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 15504 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2909488 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4217684 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7127172 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124121024 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142832784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266953808 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 421384 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4223997 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.001001 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.031618 # Request fanout histogram +system.toL2Bus.trans_dist::ReadResp 2070392 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 866358 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 969876 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 609667 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 31 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 58 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302472 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302472 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 970586 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1092680 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 41 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2910960 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4218835 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7129795 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124183936 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142881728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 267065664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 338688 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4114055 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.000998 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.031568 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4219770 99.90% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4227 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4109951 99.90% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4104 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4223997 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1779844500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4114055 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1826321500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 97962 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 100962 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 680727278 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 692196311 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 738329921 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 770446828 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 9d2732791..605ec955f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,162 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.848878 # Number of seconds simulated -sim_ticks 2848878048000 # Number of ticks simulated -final_tick 2848878048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.847227 # Number of seconds simulated +sim_ticks 2847227406000 # Number of ticks simulated +final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186843 # Simulator instruction rate (inst/s) -host_op_rate 226247 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4196685224 # Simulator tick rate (ticks/s) -host_mem_usage 620168 # Number of bytes of host memory used -host_seconds 678.84 # Real time elapsed on the host -sim_insts 126836472 # Number of instructions simulated -sim_ops 153585571 # Number of ops (including micro ops) simulated +host_inst_rate 172654 # Simulator instruction rate (inst/s) +host_op_rate 209070 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3861033235 # Simulator tick rate (ticks/s) +host_mem_usage 617124 # Number of bytes of host memory used +host_seconds 737.43 # Real time elapsed on the host +sim_insts 127319545 # Number of instructions simulated +sim_ops 154173476 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 8960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 7488 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1701632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1345580 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8578560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 207872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 624532 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 336128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1647744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1317552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8353536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 217280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 643604 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 446720 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12804992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1701632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 207872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1909504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8865600 # Number of bytes written to this memory +system.physmem.bytes_read::total 12635780 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1647744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 217280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1865024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8874176 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8883164 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 140 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8891740 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 117 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26588 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21546 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134040 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3248 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9779 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5252 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25746 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21109 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 130524 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6980 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 200620 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138525 # Number of write requests responded to by this memory +system.physmem.num_reads::total 197977 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138659 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142916 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3145 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 143050 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2630 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 597299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 472319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3011206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 247 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 72966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 219220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 117986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 578719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 462749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2933919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 76313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 226046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 156896 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4494749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 597299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 72966 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 670265 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3111962 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4437924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 578719 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 76313 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 655032 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3116778 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6155 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3118127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3111962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3122947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3116778 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2630 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 597299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 478470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3011206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 247 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 72966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 219234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 117986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 578719 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 468904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2933919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 76313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 226060 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 156896 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7612876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 200620 # Number of read requests accepted -system.physmem.writeReqs 142916 # Number of write requests accepted -system.physmem.readBursts 200620 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 142916 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12829952 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue -system.physmem.bytesWritten 8896256 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12804992 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8883164 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7560871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 197977 # Number of read requests accepted +system.physmem.writeReqs 143050 # Number of write requests accepted +system.physmem.readBursts 197977 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 143050 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12661056 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue +system.physmem.bytesWritten 8904256 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12635780 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8891740 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12282 # Per bank write bursts -system.physmem.perBankRdBursts::1 12615 # Per bank write bursts -system.physmem.perBankRdBursts::2 13546 # Per bank write bursts -system.physmem.perBankRdBursts::3 12896 # Per bank write bursts -system.physmem.perBankRdBursts::4 15667 # Per bank write bursts -system.physmem.perBankRdBursts::5 12734 # Per bank write bursts -system.physmem.perBankRdBursts::6 12682 # Per bank write bursts -system.physmem.perBankRdBursts::7 12950 # Per bank write bursts -system.physmem.perBankRdBursts::8 12070 # Per bank write bursts -system.physmem.perBankRdBursts::9 12307 # Per bank write bursts -system.physmem.perBankRdBursts::10 11595 # Per bank write bursts -system.physmem.perBankRdBursts::11 10656 # Per bank write bursts -system.physmem.perBankRdBursts::12 11845 # Per bank write bursts -system.physmem.perBankRdBursts::13 12839 # Per bank write bursts -system.physmem.perBankRdBursts::14 12069 # Per bank write bursts -system.physmem.perBankRdBursts::15 11715 # Per bank write bursts -system.physmem.perBankWrBursts::0 8801 # Per bank write bursts -system.physmem.perBankWrBursts::1 9221 # Per bank write bursts -system.physmem.perBankWrBursts::2 9816 # Per bank write bursts -system.physmem.perBankWrBursts::3 9124 # Per bank write bursts -system.physmem.perBankWrBursts::4 8304 # Per bank write bursts -system.physmem.perBankWrBursts::5 8866 # Per bank write bursts -system.physmem.perBankWrBursts::6 8953 # Per bank write bursts -system.physmem.perBankWrBursts::7 8983 # Per bank write bursts -system.physmem.perBankWrBursts::8 8497 # Per bank write bursts -system.physmem.perBankWrBursts::9 8715 # Per bank write bursts -system.physmem.perBankWrBursts::10 8212 # Per bank write bursts -system.physmem.perBankWrBursts::11 7775 # Per bank write bursts -system.physmem.perBankWrBursts::12 8513 # Per bank write bursts -system.physmem.perBankWrBursts::13 8820 # Per bank write bursts -system.physmem.perBankWrBursts::14 8499 # Per bank write bursts -system.physmem.perBankWrBursts::15 7905 # Per bank write bursts +system.physmem.perBankRdBursts::0 11990 # Per bank write bursts +system.physmem.perBankRdBursts::1 12090 # Per bank write bursts +system.physmem.perBankRdBursts::2 12710 # Per bank write bursts +system.physmem.perBankRdBursts::3 12556 # Per bank write bursts +system.physmem.perBankRdBursts::4 14859 # Per bank write bursts +system.physmem.perBankRdBursts::5 12263 # Per bank write bursts +system.physmem.perBankRdBursts::6 12121 # Per bank write bursts +system.physmem.perBankRdBursts::7 12401 # Per bank write bursts +system.physmem.perBankRdBursts::8 11839 # Per bank write bursts +system.physmem.perBankRdBursts::9 11973 # Per bank write bursts +system.physmem.perBankRdBursts::10 12288 # Per bank write bursts +system.physmem.perBankRdBursts::11 11633 # Per bank write bursts +system.physmem.perBankRdBursts::12 12418 # Per bank write bursts +system.physmem.perBankRdBursts::13 12730 # Per bank write bursts +system.physmem.perBankRdBursts::14 11938 # Per bank write bursts +system.physmem.perBankRdBursts::15 12020 # Per bank write bursts +system.physmem.perBankWrBursts::0 8637 # Per bank write bursts +system.physmem.perBankWrBursts::1 8726 # Per bank write bursts +system.physmem.perBankWrBursts::2 9304 # Per bank write bursts +system.physmem.perBankWrBursts::3 8986 # Per bank write bursts +system.physmem.perBankWrBursts::4 8078 # Per bank write bursts +system.physmem.perBankWrBursts::5 8592 # Per bank write bursts +system.physmem.perBankWrBursts::6 8645 # Per bank write bursts +system.physmem.perBankWrBursts::7 8770 # Per bank write bursts +system.physmem.perBankWrBursts::8 8363 # Per bank write bursts +system.physmem.perBankWrBursts::9 8478 # Per bank write bursts +system.physmem.perBankWrBursts::10 8927 # Per bank write bursts +system.physmem.perBankWrBursts::11 8795 # Per bank write bursts +system.physmem.perBankWrBursts::12 9084 # Per bank write bursts +system.physmem.perBankWrBursts::13 8813 # Per bank write bursts +system.physmem.perBankWrBursts::14 8578 # Per bank write bursts +system.physmem.perBankWrBursts::15 8353 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 24 # Number of times write queue was full causing retry -system.physmem.totGap 2848877502000 # Total gap between requests +system.physmem.numWrRetry 38 # Number of times write queue was full causing retry +system.physmem.totGap 2847226871000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 552 # Read request sizes (log2) +system.physmem.readPktSize::2 553 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 200040 # Read request sizes (log2) +system.physmem.readPktSize::6 197396 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 138525 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 88667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 138659 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 85811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9476 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6090 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4527 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 718 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -184,160 +184,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 68 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 83 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92501 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 234.874693 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.252552 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 298.003949 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50468 54.56% 54.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17746 19.18% 73.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6298 6.81% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3474 3.76% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2881 3.11% 87.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1488 1.61% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 938 1.01% 90.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 959 1.04% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8249 8.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92501 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6731 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.782499 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 569.000641 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6729 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::60 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 145 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92332 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 233.562015 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.589518 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 297.350425 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50532 54.73% 54.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17809 19.29% 74.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6200 6.71% 80.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3503 3.79% 84.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2794 3.03% 87.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1407 1.52% 89.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 909 0.98% 90.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 989 1.07% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8189 8.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 92332 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6903 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.657830 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 561.171003 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6902 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6731 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6731 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.651315 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.819444 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.992190 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5609 83.33% 83.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 487 7.24% 90.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 91 1.35% 91.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 48 0.71% 92.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 35 0.52% 93.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 15 0.22% 93.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 45 0.67% 94.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 18 0.27% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 127 1.89% 96.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.15% 96.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.12% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 12 0.18% 96.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 75 1.11% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 97.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.04% 97.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 23 0.34% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 82 1.22% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.48% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6903 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6903 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.154860 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.644326 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.603874 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5813 84.21% 84.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 373 5.40% 89.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 70 1.01% 90.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 58 0.84% 91.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 265 3.84% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.36% 95.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 18 0.26% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 26 0.38% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 14 0.20% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 9 0.13% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.04% 96.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.12% 96.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 153 2.22% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.09% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.07% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 5 0.07% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.04% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.04% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.04% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.48% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.01% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.07% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.12% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.13% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6731 # Writes before turning the bus around for reads -system.physmem.totQLat 5345988099 # Total ticks spent queuing -system.physmem.totMemAccLat 9104763099 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1002340000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26667.54 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::108-111 8 0.12% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.13% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 6 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6903 # Writes before turning the bus around for reads +system.physmem.totQLat 5250518808 # Total ticks spent queuing +system.physmem.totMemAccLat 8959812558 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 989145000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26540.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45417.54 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.50 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.49 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 45290.69 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.45 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.13 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.44 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing -system.physmem.readRowHits 166512 # Number of row buffer hits during reads -system.physmem.writeRowHits 80458 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.88 # Row buffer hit rate for writes -system.physmem.avgGap 8292806.29 # Average gap between requests -system.physmem.pageHitRate 72.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 369525240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 201625875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 821901600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 467000640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186074475600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 85037796405 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634728846500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1907701171860 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.633786 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719381991131 # Time in different power states -system.physmem_0.memoryStateTime::REF 95130100000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.07 # Average write queue length when enqueuing +system.physmem.readRowHits 164412 # Number of row buffer hits during reads +system.physmem.writeRowHits 80213 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.64 # Row buffer hit rate for writes +system.physmem.avgGap 8348977.86 # Average gap between requests +system.physmem.pageHitRate 72.59 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 354957120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 193677000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 787722000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 451902240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185966660880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83190012300 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1635359290500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1906304222040 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.531375 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2720439936839 # Time in different power states +system.physmem_0.memoryStateTime::REF 95074980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34360263869 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31706739411 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 329782320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179940750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 741741000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 433745280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186074475600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83868136740 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635754863750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1907382685440 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.521992 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2721101495830 # Time in different power states -system.physmem_1.memoryStateTime::REF 95130100000 # Time in different power states +system.physmem_1.actEnergy 343072800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 187192500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 755336400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 449653680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185966660880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82901008620 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635612802500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1906215727380 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.500294 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2720864046511 # Time in different power states +system.physmem_1.memoryStateTime::REF 95074980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32646289170 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31288281989 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory @@ -363,19 +365,19 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 36258885 # Number of BP lookups -system.cpu0.branchPred.condPredicted 17779541 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1788671 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 20741460 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 11048316 # Number of BTB hits +system.cpu0.branchPred.lookups 20737076 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13605991 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1017313 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13202297 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8722072 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 53.266819 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 11219024 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 931479 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4153759 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 3951203 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 202556 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 105471 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 66.064807 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3399643 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 216094 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 760668 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 581758 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 178910 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 99353 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -406,59 +408,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 71829 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 71829 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46722 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25107 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 71829 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 71829 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 71829 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 7556 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12351.641080 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11368.840758 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 8528.588507 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 7496 99.21% 99.21% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 51 0.67% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 5 0.07% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 1 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 7556 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 581987000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 581987000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 581987000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5875 77.75% 77.75% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1681 22.25% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 7556 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71829 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 68420 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 68420 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46092 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22328 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 68420 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 68420 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 68420 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6777 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12395.971669 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11546.443771 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5803.014677 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6374 94.05% 94.05% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 345 5.09% 99.14% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 47 0.69% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 6 0.09% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.06% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6777 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 338010000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 338010000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 338010000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5225 77.10% 77.10% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1552 22.90% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6777 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 68420 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71829 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7556 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 68420 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6777 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7556 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 79385 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6777 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 75197 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 24842790 # DTB read hits -system.cpu0.dtb.read_misses 65179 # DTB read misses -system.cpu0.dtb.write_hits 18502994 # DTB write hits -system.cpu0.dtb.write_misses 6650 # DTB write misses +system.cpu0.dtb.read_hits 17339980 # DTB read hits +system.cpu0.dtb.read_misses 61941 # DTB read misses +system.cpu0.dtb.write_hits 14540399 # DTB write hits +system.cpu0.dtb.write_misses 6479 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3814 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1457 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2027 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3513 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24907969 # DTB read accesses -system.cpu0.dtb.write_accesses 18509644 # DTB write accesses +system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17401921 # DTB read accesses +system.cpu0.dtb.write_accesses 14546878 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43345784 # DTB hits -system.cpu0.dtb.misses 71829 # DTB misses -system.cpu0.dtb.accesses 43417613 # DTB accesses +system.cpu0.dtb.hits 31880379 # DTB hits +system.cpu0.dtb.misses 68420 # DTB misses +system.cpu0.dtb.accesses 31948799 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -488,38 +489,40 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 4265 # Table walker walks requested -system.cpu0.itb.walker.walksShort 4265 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 325 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3940 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 4265 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 4265 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 4265 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2684 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12705.663189 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11959.550432 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5173.129128 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2444 91.06% 91.06% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 221 8.23% 99.29% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 17 0.63% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2684 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 581277500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 581277500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 581277500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2364 88.08% 88.08% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 320 11.92% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2684 # Table walker page sizes translated +system.cpu0.itb.walker.walks 3977 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3977 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 304 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3673 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3977 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3977 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3977 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2411 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12713.811696 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 12041.525578 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4752.572139 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 358 14.85% 14.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1847 76.61% 91.46% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 161 6.68% 98.13% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 17 0.71% 98.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 26 1.08% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2411 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 337545500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 337545500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 337545500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2112 87.60% 87.60% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 299 12.40% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2411 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4265 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4265 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3977 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3977 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2684 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2684 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6949 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 71322502 # ITB inst hits -system.cpu0.itb.inst_misses 4265 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2411 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2411 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6388 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 38606266 # ITB inst hits +system.cpu0.itb.inst_misses 3977 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -528,762 +531,773 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2459 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2216 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7664 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 6955 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 71326767 # ITB inst accesses -system.cpu0.itb.hits 71322502 # DTB hits -system.cpu0.itb.misses 4265 # DTB misses -system.cpu0.itb.accesses 71326767 # DTB accesses -system.cpu0.numCycles 248723849 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 38610243 # ITB inst accesses +system.cpu0.itb.hits 38606266 # DTB hits +system.cpu0.itb.misses 3977 # DTB misses +system.cpu0.itb.accesses 38610243 # DTB accesses +system.cpu0.numCycles 167224982 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 112829406 # Number of instructions committed -system.cpu0.committedOps 136421013 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8883957 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1865 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5449058541 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.204424 # CPI: cycles per instruction -system.cpu0.ipc 0.453633 # IPC: instructions per cycle -system.cpu0.op_class_0::No_OpClass 2315 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 92785256 68.01% 68.02% # Class of committed instruction -system.cpu0.op_class_0::IntMult 112251 0.08% 68.10% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 8279 0.01% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::MemRead 24255979 17.78% 85.88% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 19256933 14.12% 100.00% # Class of committed instruction +system.cpu0.committedInsts 79715648 # Number of instructions committed +system.cpu0.committedOps 95927461 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5237247 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1849 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5527254348 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.097769 # CPI: cycles per instruction +system.cpu0.ipc 0.476697 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 63730677 66.44% 66.44% # Class of committed instruction +system.cpu0.op_class_0::IntMult 92076 0.10% 66.53% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 8115 0.01% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::MemRead 16811055 17.52% 84.07% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 15283265 15.93% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 136421013 # Class of committed instruction +system.cpu0.op_class_0::total 95927461 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1871 # number of quiesce instructions executed -system.cpu0.tickCycles 199772172 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 48951677 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 757698 # number of replacements -system.cpu0.dcache.tags.tagsinuse 497.510170 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 41768211 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 758210 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.087919 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 600550000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.510170 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971700 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.971700 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1852 # number of quiesce instructions executed +system.cpu0.tickCycles 128530134 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 38694848 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 715130 # number of replacements +system.cpu0.dcache.tags.tagsinuse 500.249385 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 30394668 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 715642 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.471890 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.249385 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977050 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.977050 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 86683357 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 86683357 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23240588 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23240588 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 17340312 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 17340312 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 329150 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 329150 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374937 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 374937 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370987 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 370987 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 40580900 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 40580900 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 40910050 # number of overall hits -system.cpu0.dcache.overall_hits::total 40910050 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 491866 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 491866 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 603751 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 603751 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141943 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 141943 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21447 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21447 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20439 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20439 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1095617 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1095617 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1237560 # number of overall misses -system.cpu0.dcache.overall_misses::total 1237560 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6971329500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6971329500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12451928500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 12451928500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330609500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 330609500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 530569000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 530569000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 651500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 651500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 19423258000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 19423258000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 19423258000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 19423258000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 23732454 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23732454 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17944063 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17944063 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 471093 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 471093 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396384 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 396384 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391426 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 391426 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 41676517 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 41676517 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 42147610 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 42147610 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020725 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.020725 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033646 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.033646 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301306 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301306 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054107 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054107 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052217 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052217 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026289 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026289 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029363 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029363 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14173.229091 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14173.229091 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20624.278055 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20624.278055 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15415.186273 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15415.186273 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25958.657469 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25958.657469 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63780149 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63780149 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15810331 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15810331 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13424811 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13424811 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320440 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 320440 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365226 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365226 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361080 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361080 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 29235142 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 29235142 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 29555582 # number of overall hits +system.cpu0.dcache.overall_hits::total 29555582 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 463723 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 463723 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 580901 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 580901 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136483 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 136483 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21307 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21307 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20567 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20567 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1044624 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1044624 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1181107 # number of overall misses +system.cpu0.dcache.overall_misses::total 1181107 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6183627500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6183627500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10315375000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10315375000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 321766500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 321766500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 497952500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 497952500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 229500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 229500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 16499002500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 16499002500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 16499002500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 16499002500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16274054 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16274054 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 14005712 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 14005712 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456923 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 456923 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386533 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386533 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381647 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381647 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30279766 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30279766 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30736689 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30736689 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028495 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028495 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041476 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.041476 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298700 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298700 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055123 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055123 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053890 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053890 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034499 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.034499 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038427 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.038427 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13334.744017 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13334.744017 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17757.543884 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17757.543884 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15101.445534 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15101.445534 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24211.236447 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24211.236447 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17728.145876 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 17728.145876 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15694.801060 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15694.801060 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15794.202029 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15794.202029 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13969.100598 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13969.100598 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 757698 # number of writebacks -system.cpu0.dcache.writebacks::total 757698 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75572 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 75572 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266010 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 266010 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14891 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14891 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 341582 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 341582 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 341582 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 341582 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 416294 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 416294 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337741 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 337741 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 108342 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 108342 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6556 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6556 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20439 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20439 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 754035 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 754035 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 862377 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 862377 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32042 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32042 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28724 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28724 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60766 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60766 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5289052500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5289052500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7033138500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7033138500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1803466000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1803466000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104788000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104788000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 510140000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 510140000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 641500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 641500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12322191000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12322191000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14125657000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14125657000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6702357000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6702357000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6702357000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6702357000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017541 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017541 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018822 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018822 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.229980 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.229980 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016540 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016540 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052217 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052217 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018093 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.018093 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020461 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020461 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12705.089432 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.089432 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20824.058968 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20824.058968 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16646.046778 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16646.046778 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15983.526541 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15983.526541 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24959.146729 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24959.146729 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 715130 # number of writebacks +system.cpu0.dcache.writebacks::total 715130 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 71798 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 71798 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255281 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 255281 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14780 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14780 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 327079 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 327079 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 327079 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 327079 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391925 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 391925 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325620 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325620 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103078 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 103078 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6527 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6527 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20567 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20567 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 717545 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 717545 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 820623 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 820623 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20575 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20575 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19271 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19271 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39846 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4674150000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4674150000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5703236000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5703236000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1673631500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1673631500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101407500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101407500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 477391500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 477391500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 223500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 223500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10377386000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10377386000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12051017500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12051017500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4615609000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4615609000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4615609000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4615609000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024083 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024083 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023249 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023249 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225592 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225592 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016886 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016886 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053890 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053890 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023697 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023697 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026698 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026698 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11926.133827 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11926.133827 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17515.005221 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17515.005221 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16236.553872 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16236.553872 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15536.617129 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15536.617129 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23211.528176 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23211.528176 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16341.669816 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16341.669816 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16379.909251 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16379.909251 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.115224 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.115224 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110297.814567 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110297.814567 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 2042425 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.725794 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 69271608 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 2042937 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 33.907853 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6975620000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.725794 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999464 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999464 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14462.348703 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14462.348703 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14685.205630 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14685.205630 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 224330.935601 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 224330.935601 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115836.194348 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115836.194348 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 1962004 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.774944 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36636559 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1962516 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.668158 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6612168000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774944 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999560 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999560 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 144672089 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 144672089 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 69271608 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 69271608 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 69271608 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 69271608 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 69271608 # number of overall hits -system.cpu0.icache.overall_hits::total 69271608 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 2042958 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2042958 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 2042958 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2042958 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 2042958 # number of overall misses -system.cpu0.icache.overall_misses::total 2042958 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20578821000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 20578821000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 20578821000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 20578821000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 20578821000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 20578821000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 71314566 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 71314566 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 71314566 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 71314566 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 71314566 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 71314566 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028647 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.028647 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028647 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.028647 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028647 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.028647 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10073.051428 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10073.051428 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10073.051428 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10073.051428 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10073.051428 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10073.051428 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 79160710 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 79160710 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 36636559 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36636559 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36636559 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36636559 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36636559 # number of overall hits +system.cpu0.icache.overall_hits::total 36636559 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1962531 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1962531 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1962531 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1962531 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1962531 # number of overall misses +system.cpu0.icache.overall_misses::total 1962531 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18757498000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18757498000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18757498000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18757498000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18757498000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18757498000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 38599090 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 38599090 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 38599090 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 38599090 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 38599090 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 38599090 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050844 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050844 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050844 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050844 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050844 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050844 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9557.809787 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9557.809787 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9557.809787 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9557.809787 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9557.809787 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9557.809787 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 2042425 # 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number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19557342500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 19557342500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19557342500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 19557342500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19557342500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 19557342500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 557356500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 557356500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 557356500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 557356500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028647 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028647 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028647 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028647 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028647 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028647 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9573.051673 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927381 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1927559 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 155 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.writebacks::writebacks 1962004 # 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number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17776233000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17776233000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17776233000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17776233000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17776233000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17776233000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 319470000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 319470000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 319470000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 319470000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050844 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.050844 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.050844 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9057.810042 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9057.810042 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9057.810042 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92626.848362 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92626.848362 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1841200 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1841258 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 51 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # 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Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 314209 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 14.902444 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14747.855464 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 65.322901 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.062340 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1306.886401 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.900138 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003987 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 14756.008973 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.059574 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.057522 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1311.534778 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.900635 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003544 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.079766 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.983894 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 987 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.080050 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984232 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 965 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15123 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 320 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 459 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 198 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4117 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8290 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2270 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.060242 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15115 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 400 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 257 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4162 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7775 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2779 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.058899 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.923035 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 93327543 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 93327543 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 87658 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5814 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 93472 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 506036 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 506036 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 2249753 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 2249753 # number of WritebackClean hits +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922546 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 89320549 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 89320549 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 82730 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5417 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 88147 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 481961 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 481961 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 2152508 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 2152508 # number of WritebackClean hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 233559 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 233559 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1972952 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1972952 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 430429 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 430429 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 87658 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5814 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1972952 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 663988 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 2730412 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 87658 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5814 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1972952 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 663988 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2730412 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 757 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 97 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 854 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56432 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 56432 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20439 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 20439 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 47758 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 47758 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 70006 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 70006 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 100757 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 100757 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 757 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 97 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 70006 # 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mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150478 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150478 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034232 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.188570 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.188570 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.175382 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.072306 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.175382 # mshr miss rate for overall accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163708 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163708 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034822 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034822 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.199889 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.199889 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010241 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.023084 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034822 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.187261 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075686 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010241 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.023084 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034822 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.187261 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.161933 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 39501.170960 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 79624.255077 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26001.258151 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26001.258151 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17421.547042 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17421.547042 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57646.697534 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57646.697534 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58632.110275 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29121.138899 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29121.138899 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37595.250453 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44500.623571 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37595.250453 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63941.054222 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201170.042444 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193884.994021 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 106077.255373 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 107785.824714 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 5755490 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2900081 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44333 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 350983 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 345970 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5013 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 141142 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2764242 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28724 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28724 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 743774 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2294086 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 245615 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 332229 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 86791 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42912 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113818 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 300259 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 296935 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2042958 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 604813 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3110 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6136174 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2759564 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14116 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 185351 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 9095205 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 261715136 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104822354 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23644 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 353660 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 366914794 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1076546 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4066304 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.104124 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.309432 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.167436 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26280.487805 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54135.843337 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 54135.843337 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19643.217143 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19643.217143 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15674.098026 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15674.098026 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 176499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 176499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39870.893725 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39870.893725 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42872.146620 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24148.579986 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24148.579986 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28945.690941 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33389.283701 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28945.690941 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54135.843337 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44757.813723 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84626.703392 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 216325.103281 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197417.852980 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84626.703392 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111702.278773 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109545.363206 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 5508026 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2775137 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42660 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 346625 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 340732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5893 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 122459 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2635557 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19271 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19271 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 716131 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2195168 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 240019 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 309687 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88590 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43220 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114518 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 288089 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284462 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1962531 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 586533 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3131 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5893963 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2592135 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13195 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174334 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 8673627 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251390912 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99322292 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22180 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 334344 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 351069728 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1056913 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3897709 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.106693 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.313582 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3647917 89.71% 89.71% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 413374 10.17% 99.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 5013 0.12% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3487742 89.48% 89.48% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 404074 10.37% 99.85% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 5893 0.15% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4066304 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5765624998 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3897709 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5501303494 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115477021 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115667783 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 3070848423 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2949460514 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1304480252 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1225261932 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 8215479 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7656487 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 96957457 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 90771952 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 3600044 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2023819 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 196135 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2284720 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1344428 # Number of BTB hits +system.cpu1.branchPred.lookups 19337823 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6215951 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 910078 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 9913117 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3669706 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 58.844322 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 748131 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 53981 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 144785 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 107908 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 36877 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 17103 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 37.018689 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8699112 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 707232 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3579063 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 3516137 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 62926 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 23615 # Number of mispredicted indirect branches. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1313,58 +1327,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 22955 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 22955 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18858 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4097 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 22955 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 22955 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 22955 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1846 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11730.498375 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11025.049339 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6418.983235 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 1704 92.31% 92.31% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 130 7.04% 99.35% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 9 0.49% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 1 0.05% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1846 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1572230032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1572230032 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1572230032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1316 71.29% 71.29% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 530 28.71% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1846 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 22955 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 26974 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 26974 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20087 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6887 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 26974 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 26974 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 26974 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2714 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11914.148858 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11049.041659 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5760.245338 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 673 24.80% 24.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1844 67.94% 92.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 118 4.35% 97.09% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.06% 99.15% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 13 0.48% 99.63% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 4 0.15% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.04% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.07% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.07% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2714 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -2024068032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -2024068032 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -2024068032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1997 73.58% 73.58% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 717 26.42% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2714 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26974 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 22955 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1846 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26974 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2714 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1846 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 24801 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2714 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 29688 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3573471 # DTB read hits -system.cpu1.dtb.read_misses 21372 # DTB read misses -system.cpu1.dtb.write_hits 2968093 # DTB write hits -system.cpu1.dtb.write_misses 1583 # DTB write misses +system.cpu1.dtb.read_hits 11185393 # DTB read hits +system.cpu1.dtb.read_misses 25019 # DTB read misses +system.cpu1.dtb.write_hits 6992115 # DTB write hits +system.cpu1.dtb.write_misses 1955 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1717 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 261 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2060 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 164 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 367 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3594843 # DTB read accesses -system.cpu1.dtb.write_accesses 2969676 # DTB write accesses +system.cpu1.dtb.perms_faults 283 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 11210412 # DTB read accesses +system.cpu1.dtb.write_accesses 6994070 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6541564 # DTB hits -system.cpu1.dtb.misses 22955 # DTB misses -system.cpu1.dtb.accesses 6564519 # DTB accesses +system.cpu1.dtb.hits 18177508 # DTB hits +system.cpu1.dtb.misses 26974 # DTB misses +system.cpu1.dtb.accesses 18204482 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1394,44 +1412,45 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2082 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2082 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 151 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1931 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2082 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2082 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2082 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 843 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11844.009490 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11365.721789 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4291.658656 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 129 15.30% 15.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 559 66.31% 81.61% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 106 12.57% 94.19% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 28 3.32% 97.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 97.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 9 1.07% 98.81% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 1 0.12% 98.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.24% 99.17% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.59% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.12% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 843 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1573105532 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1573105532 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1573105532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 703 83.39% 83.39% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 140 16.61% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 843 # Table walker page sizes translated +system.cpu1.itb.walker.walks 2420 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2420 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2239 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2420 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2420 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2420 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1133 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12165.931156 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11504.985007 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4742.932714 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 196 17.30% 17.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 640 56.49% 73.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 219 19.33% 93.12% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 41 3.62% 96.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 96.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 1.32% 98.23% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.71% 98.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.26% 99.21% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.44% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1133 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -2024645532 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -2024645532 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -2024645532 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 964 85.08% 85.08% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 169 14.92% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1133 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2082 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2082 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2420 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2420 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 843 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 843 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2925 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 6880260 # ITB inst hits -system.cpu1.itb.inst_misses 2082 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1133 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1133 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3553 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 39602800 # ITB inst hits +system.cpu1.itb.inst_misses 2420 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1440,759 +1459,748 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 907 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1166 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1103 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1819 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6882342 # ITB inst accesses -system.cpu1.itb.hits 6880260 # DTB hits -system.cpu1.itb.misses 2082 # DTB misses -system.cpu1.itb.accesses 6882342 # DTB accesses -system.cpu1.numCycles 40344479 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 39605220 # ITB inst accesses +system.cpu1.itb.hits 39602800 # DTB hits +system.cpu1.itb.misses 2420 # DTB misses +system.cpu1.itb.accesses 39605220 # DTB accesses +system.cpu1.numCycles 115435582 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 14007066 # Number of instructions committed -system.cpu1.committedOps 17164558 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1348197 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2750 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5656772716 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.880295 # CPI: cycles per instruction -system.cpu1.ipc 0.347187 # IPC: instructions per cycle -system.cpu1.op_class_0::No_OpClass 24 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 10609725 61.81% 61.81% # Class of committed instruction -system.cpu1.op_class_0::IntMult 25154 0.15% 61.96% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 3180 0.02% 61.98% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 61.98% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 61.98% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 61.98% # Class of committed instruction -system.cpu1.op_class_0::MemRead 3461168 20.16% 82.14% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 3065307 17.86% 100.00% # Class of committed instruction +system.cpu1.committedInsts 47603897 # Number of instructions committed +system.cpu1.committedOps 58246015 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 5049538 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2772 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5578401245 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.424919 # CPI: cycles per instruction +system.cpu1.ipc 0.412385 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 40076529 68.81% 68.81% # Class of committed instruction +system.cpu1.op_class_0::IntMult 45752 0.08% 68.88% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 3347 0.01% 68.89% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.89% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.89% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.89% # Class of committed instruction +system.cpu1.op_class_0::MemRead 11012402 18.91% 87.80% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 7107919 12.20% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 17164558 # Class of committed instruction +system.cpu1.op_class_0::total 58246015 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2755 # number of quiesce instructions executed -system.cpu1.tickCycles 27219778 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 13124701 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 155125 # number of replacements -system.cpu1.dcache.tags.tagsinuse 474.675908 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6200474 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 155475 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.880843 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 91637729500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.675908 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.927101 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.927101 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 281 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 69 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.683594 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 13156233 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 13156233 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3254524 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3254524 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2729726 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2729726 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42620 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 42620 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70434 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 70434 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61835 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 61835 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5984250 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5984250 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6026870 # number of overall hits -system.cpu1.dcache.overall_hits::total 6026870 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133031 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133031 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 121759 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 121759 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24466 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 24466 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16570 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16570 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23417 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23417 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 254790 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 254790 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 279256 # number of overall misses -system.cpu1.dcache.overall_misses::total 279256 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2166796500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2166796500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4455024500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4455024500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320532500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 320532500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 635944000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 635944000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1106500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1106500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6621821000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6621821000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6621821000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6621821000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3387555 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3387555 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2851485 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2851485 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67086 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 67086 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87004 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 87004 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85252 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 85252 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 6239040 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6239040 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 6306126 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 6306126 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039271 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.039271 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.042700 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.042700 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.364696 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.364696 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190451 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190451 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274680 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274680 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040838 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.040838 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044283 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044283 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16287.906578 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16287.906578 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36588.872280 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 36588.872280 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19344.146047 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19344.146047 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27157.364308 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27157.364308 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2777 # number of quiesce instructions executed +system.cpu1.tickCycles 97896037 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 17539545 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 196286 # number of replacements +system.cpu1.dcache.tags.tagsinuse 471.109798 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 17737294 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 196629 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 90.206907 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 91177108000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.109798 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920136 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.920136 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 36398755 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 36398755 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 10795076 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10795076 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6704752 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6704752 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50350 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50350 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80171 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 80171 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71533 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71533 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 17499828 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 17499828 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 17550178 # number of overall hits +system.cpu1.dcache.overall_hits::total 17550178 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 159722 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 159722 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 145538 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 145538 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 31004 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 31004 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16960 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16960 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23795 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23795 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 305260 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 305260 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 336264 # number of overall misses +system.cpu1.dcache.overall_misses::total 336264 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2429598500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2429598500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3913148500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3913148500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317482500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 317482500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 583924500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 583924500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 387500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 387500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6342747000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6342747000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6342747000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6342747000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10954798 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10954798 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6850290 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6850290 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81354 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 81354 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97131 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97131 # 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average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23712.367863 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23712.367863 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20778.179257 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20778.179257 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18862.402755 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18862.402755 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # 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mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035506 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027923 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027923 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.356796 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.356796 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056135 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056135 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274680 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274680 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032040 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.032040 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035495 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035495 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15322.997556 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15322.997556 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34082.457330 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34082.457330 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18742.041277 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18742.041277 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18273.341523 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18273.341523 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26157.876756 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26157.876756 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 196286 # number of writebacks +system.cpu1.dcache.writebacks::total 196286 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16292 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 16292 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52982 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 52982 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12069 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12069 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 69274 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 69274 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 69274 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 69274 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143430 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 143430 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92556 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 92556 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30096 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 30096 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4891 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4891 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23795 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23795 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 235986 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 235986 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 266082 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 266082 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14424 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11758 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11758 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26182 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26182 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2041290000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2041290000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2380409500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2380409500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 535271500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 535271500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82814000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82814000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 560137500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 560137500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 379500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 379500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4421699500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4421699500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4956971000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4956971000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2479783500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2479783500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2479783500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2479783500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013093 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013093 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013511 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013511 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369939 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369939 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050355 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050355 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249612 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249612 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013254 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.013254 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014876 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.014876 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14231.959841 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14231.959841 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25718.586585 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25718.586585 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17785.469830 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17785.469830 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16931.915764 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16931.915764 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23540.134482 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23540.134482 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22795.118584 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22795.118584 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22361.702936 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22361.702936 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131001.345442 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131001.345442 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 73706.850871 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 73706.850871 # average overall mshr uncacheable latency -system.cpu1.icache.tags.replacements 856657 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.135889 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6021932 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 857169 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 7.025373 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 73312939000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.135889 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974875 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974875 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18737.126355 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18737.126355 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18629.486399 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18629.486399 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171920.653078 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171920.653078 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94713.295394 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 94713.295394 # average overall mshr uncacheable latency +system.cpu1.icache.tags.replacements 946364 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.210861 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 38654025 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 946876 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.822690 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72815756000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.210861 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975021 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975021 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 50 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 14615371 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 14615371 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 6021932 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6021932 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6021932 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6021932 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6021932 # number of overall hits -system.cpu1.icache.overall_hits::total 6021932 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 857169 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 857169 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 857169 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 857169 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 857169 # number of overall misses -system.cpu1.icache.overall_misses::total 857169 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7590039500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7590039500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7590039500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7590039500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7590039500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7590039500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 6879101 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 6879101 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 6879101 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 6879101 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 6879101 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 6879101 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.124605 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.124605 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.124605 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.124605 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.124605 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.124605 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8854.776013 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8854.776013 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8854.776013 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8854.776013 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8854.776013 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8854.776013 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 80148678 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 80148678 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 38654025 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 38654025 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 38654025 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 38654025 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 38654025 # number of overall hits +system.cpu1.icache.overall_hits::total 38654025 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 946876 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 946876 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 946876 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 946876 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 946876 # number of overall misses +system.cpu1.icache.overall_misses::total 946876 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8324695000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8324695000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8324695000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8324695000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8324695000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8324695000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 39600901 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 39600901 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 39600901 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 39600901 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 39600901 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 39600901 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023910 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023910 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023910 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023910 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023910 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023910 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8791.747811 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8791.747811 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8791.747811 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8791.747811 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8791.747811 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8791.747811 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 856657 # number of writebacks -system.cpu1.icache.writebacks::total 856657 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 857169 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 857169 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 857169 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 857169 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 857169 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 857169 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 946364 # number of writebacks +system.cpu1.icache.writebacks::total 946364 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 946876 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 946876 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 946876 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 946876 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 946876 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 946876 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7161455000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7161455000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7161455000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7161455000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7161455000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7161455000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15471500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15471500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15471500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 15471500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124605 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124605 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124605 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.124605 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124605 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.124605 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8354.776013 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138138.392857 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138138.392857 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.num_hwpf_issued 119555 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 119603 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 42 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7851257000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7851257000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7851257000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7851257000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7851257000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7851257000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10474500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10474500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10474500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10474500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023910 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023910 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023910 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8291.747811 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8291.747811 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8291.747811 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 93522.321429 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 93522.321429 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.num_hwpf_issued 199879 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 199934 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 48 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 49365 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 38167 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15174.819793 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1843147 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 53515 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 34.441689 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58626 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 53638 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15286.424872 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 2058198 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 68366 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 30.105579 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14738.835731 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 34.198599 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.090889 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 401.694574 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.899587 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002087 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.024517 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.926197 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 877 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14388 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 49 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 826 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 60 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 344 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2130 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11914 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.053528 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.878174 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 34225299 # 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number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 82475 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 24322 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2742 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 844303 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 100548 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 971915 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 24322 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2742 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 844303 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 100548 # number of overall hits -system.cpu1.l2cache.overall_hits::total 971915 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 663 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 241 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 904 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29265 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29265 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23415 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23415 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32287 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 32287 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 12866 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 12866 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 66621 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 66621 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 663 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 241 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 12866 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 98908 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 112678 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 663 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 241 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 12866 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 98908 # number of overall misses -system.cpu1.l2cache.overall_misses::total 112678 # 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number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 14913000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4829500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 739774500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3309806996 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4069323996 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 24985 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2983 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 27968 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 94449 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 94449 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 899051 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 899051 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29265 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29265 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23415 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23415 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50360 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 50360 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 857169 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 857169 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 149096 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 149096 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 24985 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2983 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 857169 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 199456 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1084593 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 24985 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2983 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 857169 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 199456 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1084593 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026536 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.080791 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.032323 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.occ_blocks::writebacks 14816.571197 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 39.116539 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.045474 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 428.691662 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.904332 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5681 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7813 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.055359 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002747 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.840820 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 38543839 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 38543839 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 30076 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3135 # 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number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 962292245 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 962292245 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 589948999 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 589948999 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 435782000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 435782000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1000999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1000999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1490377000 # 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number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3369823496 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 10935000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3383500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 662136000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2693368996 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 962292245 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4332115741 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14575500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 365633500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 380209000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14575500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 365633500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 380209000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032323 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26182 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26294 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 10605000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3273500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 13878500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1006636893 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1006636893 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 505691500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 505691500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 380458500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 380458500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 318000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 318000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1135025000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1135025000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 675844000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 675844000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1246810496 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1246810496 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 10605000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3273500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 675844000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2381835496 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3071557996 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 10605000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3273500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 675844000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2381835496 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1006636893 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4078194889 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9578500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2364337500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2373916000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9578500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2364337500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2373916000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025012 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.636358 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.636358 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.014999 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014999 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.446571 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.446571 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.014999 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.494490 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103624 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.014999 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.494490 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548003 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548003 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.021165 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.402142 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402142 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439994 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103862 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439994 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.122054 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15839.048673 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48141.089849 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20158.858671 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20158.858671 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18611.232116 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18611.232116 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 500499.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 500499.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46505.975598 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46505.975598 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51500.038889 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18067.826079 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18067.826079 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27308.083789 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29983.303639 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.083789 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32725.097946 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122984.695594 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123244.408428 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 69196.347464 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 70461.267606 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 2128285 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1071677 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18282 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 177050 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 175620 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1430 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 34150 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1077374 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2311 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2311 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 124900 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 917333 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 97527 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 24473 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 71017 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41707 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 84949 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 57470 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 55019 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 857169 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 232907 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 41 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2571219 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 743876 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6996 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 52037 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3374128 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 109692032 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25376564 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11932 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 99940 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 135180468 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 380471 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1449236 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.140738 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.350577 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.125170 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16289.319249 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38663.269819 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38663.269819 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16840.104566 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16840.104566 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15989.010296 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15989.010296 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33124.908799 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33124.908799 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33723.067711 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17377.391964 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17377.391964 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22467.178825 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24203.219649 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22467.178825 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38663.269819 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26664.802502 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85522.321429 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163916.909318 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163312.878371 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85522.321429 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90303.930181 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90283.562790 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 2394243 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1206431 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20164 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 192169 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 190372 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1797 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 53056 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1216172 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11758 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11758 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 154274 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 1024857 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 118852 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 31456 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 74303 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42261 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86315 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 69975 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67112 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 946876 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 270105 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 65 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2840340 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 913098 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8024 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 64559 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3826021 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121174528 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30799564 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13460 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 122792 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 152110344 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 428107 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1655199 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.135380 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.345288 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1246703 86.02% 86.02% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 201103 13.88% 99.90% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1430 0.10% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1432915 86.57% 86.57% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 220487 13.32% 99.89% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1797 0.11% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1449236 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2091716493 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1655199 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2373087991 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 78610365 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79906669 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1286047248 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1420645672 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 331216893 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 410383006 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4013000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4659998 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 27068966 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 33872477 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31009 # Transaction distribution -system.iobus.trans_dist::ReadResp 31009 # Transaction distribution -system.iobus.trans_dist::WriteReq 59425 # Transaction distribution -system.iobus.trans_dist::WriteResp 59425 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31003 # Transaction distribution +system.iobus.trans_dist::ReadResp 31003 # Transaction distribution +system.iobus.trans_dist::WriteReq 59422 # Transaction distribution +system.iobus.trans_dist::WriteResp 59422 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2211,11 +2219,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2234,63 +2242,63 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48277500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48463001 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 326500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 88000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 84000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 577000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 574000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 19000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6148000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6138000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33110001 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33143500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187086234 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187679851 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36433 # number of replacements -system.iocache.tags.tagsinuse 14.469289 # Cycle average of tags in use +system.iocache.tags.replacements 36449 # number of replacements +system.iocache.tags.tagsinuse 14.476064 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 272370801000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.469289 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904331 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904331 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 271175186000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.476064 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904754 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904754 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2304,14 +2312,14 @@ system.iocache.demand_misses::realview.ide 36467 # system.iocache.demand_misses::total 36467 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36467 # number of overall misses system.iocache.overall_misses::total 36467 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31660877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31660877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4578259357 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4578259357 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4609920234 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4609920234 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4609920234 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4609920234 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31712877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31712877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4301380974 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4301380974 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4333093851 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4333093851 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4333093851 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4333093851 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2328,22 +2336,22 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 130291.674897 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 130291.674897 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126387.460165 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126387.460165 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 126413.476129 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126413.476129 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 126413.476129 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126413.476129 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 130505.666667 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 130505.666667 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118743.953567 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118743.953567 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118822.328434 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118822.328434 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118822.328434 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118822.328434 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 152 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 16.888889 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.writebacks::writebacks 36206 # number of writebacks +system.iocache.writebacks::total 36206 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses @@ -2352,14 +2360,14 @@ system.iocache.demand_mshr_misses::realview.ide 36467 system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19510877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19510877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2765398414 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2765398414 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2784909291 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2784909291 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2784909291 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2784909291 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19562877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19562877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2487893822 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2487893822 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2507456699 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2507456699 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2507456699 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2507456699 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2368,565 +2376,569 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80291.674897 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 80291.674897 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76341.608160 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76341.608160 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76367.929662 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76367.929662 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76367.929662 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76367.929662 # average overall mshr miss latency -system.l2c.tags.replacements 132278 # number of replacements -system.l2c.tags.tagsinuse 63284.055151 # Cycle average of tags in use -system.l2c.tags.total_refs 475189 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 196356 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.420038 # Average number of references to valid blocks. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80505.666667 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 80505.666667 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68680.814432 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68680.814432 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency +system.l2c.tags.replacements 131721 # number of replacements +system.l2c.tags.tagsinuse 63119.316885 # Cycle average of tags in use +system.l2c.tags.total_refs 480965 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 195649 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.458305 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13432.084830 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 86.256901 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.025522 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 9264.781047 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2924.876995 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33297.808041 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.154929 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1918.631510 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 571.851499 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1782.583876 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.204957 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001316 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.141369 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.044630 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.508084 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000079 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.029276 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008726 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027200 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.965638 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 29131 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 62 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 34885 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 127 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5182 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 23822 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 62 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 413 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3378 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 31070 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.444504 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000946 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.532303 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6384287 # Number of tag accesses -system.l2c.tags.data_accesses 6384287 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 266285 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 266285 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 34059 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2216 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 36275 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2214 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 916 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3130 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4440 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1284 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5724 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 468 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 93 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 47246 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 51272 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 49179 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 71 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 15 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 9697 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 5512 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3623 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 167176 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 468 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 93 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 47246 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 55712 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 49179 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 71 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 15 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 9697 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 6796 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 3623 # number of demand (read+write) hits -system.l2c.demand_hits::total 172900 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 468 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 93 # number of overall hits -system.l2c.overall_hits::cpu0.inst 47246 # number of overall hits -system.l2c.overall_hits::cpu0.data 55712 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 49179 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 71 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 15 # number of overall hits -system.l2c.overall_hits::cpu1.inst 9697 # number of overall hits -system.l2c.overall_hits::cpu1.data 6796 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 3623 # number of overall hits -system.l2c.overall_hits::total 172900 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9961 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2371 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12332 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 734 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1296 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2030 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11316 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8107 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19423 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 140 # number of ReadSharedReq misses +system.l2c.tags.occ_blocks::writebacks 13508.912510 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 74.990696 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038635 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 9208.691215 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2842.970469 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33089.520800 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.769626 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2121.922145 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 593.095570 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1670.405219 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.206130 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001144 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.140513 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043380 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.504906 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000134 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.032378 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009050 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.025488 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.963124 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 27523 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 36326 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 134 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4354 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 23032 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 79 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 3689 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 32199 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.419968 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.001205 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.554291 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6440622 # Number of tag accesses +system.l2c.tags.data_accesses 6440622 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 269250 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 269250 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 33826 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 2712 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 36538 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2202 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 1074 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3276 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4226 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1659 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5885 # 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mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.589886 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.591775 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.531889 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.230263 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010638 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.324339 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.276157 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731832 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.134146 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.244925 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.589886 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.591775 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.531889 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72739.684771 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72382.960776 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72671.099578 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74553.814714 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73866.126543 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74114.778325 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 138931.027483 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121991.059948 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 131860.424754 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132978.578571 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121108.391191 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126950.549250 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140333.580665 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 125863.636364 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123255.799619 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128328.838129 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137229.778184 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132978.578571 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121108.391191 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133328.864550 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140333.580665 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125863.636364 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123255.799619 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123072.534527 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 136698.978074 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132978.578571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121108.391191 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133328.864550 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140333.580665 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125863.636364 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123255.799619 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123072.534527 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 136698.978074 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183168.856719 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105088.889899 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 170005.801849 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96585.204012 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 59101.307139 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 94714.260374 # average overall mshr uncacheable latency -system.membus.trans_dist::ReadReq 39041 # Transaction distribution -system.membus.trans_dist::ReadResp 216336 # Transaction distribution -system.membus.trans_dist::WriteReq 31035 # Transaction distribution -system.membus.trans_dist::WriteResp 31035 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138525 # Transaction distribution -system.membus.trans_dist::CleanEvict 18214 # Transaction distribution -system.membus.trans_dist::UpgradeReq 73002 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40704 # Transaction distribution -system.membus.trans_dist::UpgradeResp 16 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 39822 # Transaction distribution -system.membus.trans_dist::ReadExResp 19318 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 177295 # Transaction distribution +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.225932 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.526619 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.260783 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.253306 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.563237 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.394231 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.725281 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.832627 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.767345 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.200686 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.014286 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.326431 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.161404 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728637 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.087248 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.164463 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.153794 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.559699 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.495784 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.200686 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.014286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.326431 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.276692 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728637 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.087248 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.164463 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.463027 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.559699 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.513955 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.200686 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.014286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.326431 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.276692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728637 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.087248 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.164463 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.463027 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.559699 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.513955 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23958.421959 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23070.102751 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23750.504267 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25792.503347 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24699.277978 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25082.317073 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89437.214305 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73128.741306 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 82502.962494 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71235.812444 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78696.563606 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72902.761226 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82897.365532 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88189.814683 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71235.812444 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84452.805313 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72902.761226 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74895.335186 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 87621.682669 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71235.812444 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84452.805313 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72902.761226 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74895.335186 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 87621.682669 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63626.703392 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 198323.110571 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64517.857143 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145946.883087 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166295.938507 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63626.703392 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102406.715856 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64517.857143 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80396.501050 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92143.139439 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 526346 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 301567 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 567 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 38557 # Transaction distribution +system.membus.trans_dist::ReadResp 213679 # Transaction distribution +system.membus.trans_dist::WriteReq 31029 # Transaction distribution +system.membus.trans_dist::WriteResp 31029 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138659 # Transaction distribution +system.membus.trans_dist::CleanEvict 18543 # Transaction distribution +system.membus.trans_dist::UpgradeReq 76988 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41072 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 39665 # Transaction distribution +system.membus.trans_dist::ReadExResp 19299 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 175122 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14218 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664863 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 787057 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72915 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72915 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 859972 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664223 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 786371 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 859302 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28436 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19371036 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19563630 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21880750 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 120342 # Total snoops (count) -system.membus.snoop_fanout::samples 593889 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28380 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19209376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19401896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21720040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123861 # Total snoops (count) +system.membus.snoop_fanout::samples 438659 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011132 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.104918 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 593889 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 433776 98.89% 98.89% # Request fanout histogram +system.membus.snoop_fanout::1 4883 1.11% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 593889 # Request fanout histogram -system.membus.reqLayer0.occupancy 88806999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 438659 # Request fanout histogram +system.membus.reqLayer0.occupancy 89013499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12293000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12314999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1011120672 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1002605728 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1148583006 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1133893717 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1341627 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1318131 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2969,52 +2981,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 1040507 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 561217 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 153026 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 21153 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 20199 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 954 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 39044 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 500503 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31035 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 404834 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 139205 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 109172 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43834 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 153006 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50921 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50921 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 461474 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1330590 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 273408 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1603998 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36819910 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4347048 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 41166958 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 447482 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 940492 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.338468 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.475327 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 1068358 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 578478 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 169754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 19773 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 18732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1041 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 38560 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 513452 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31029 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31029 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 371703 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 144260 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 113415 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 44348 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 157763 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51662 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51662 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 474894 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4314 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1271960 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368625 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1640585 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36024040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5855360 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 41879400 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 387762 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 889983 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.383411 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.488617 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 623120 66.25% 66.25% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 316418 33.64% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 954 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 549795 61.78% 61.78% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 339147 38.11% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1041 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 940492 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 900307645 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 889983 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 926156147 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 342123 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 342619 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 690598933 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 669727799 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 213088139 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 257138606 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 3f52f900f..c94a5f66f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.858505 # Nu sim_ticks 2858505242500 # Number of ticks simulated final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187730 # Simulator instruction rate (inst/s) -host_op_rate 226980 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4795719535 # Simulator tick rate (ticks/s) -host_mem_usage 583724 # Number of bytes of host memory used -host_seconds 596.05 # Real time elapsed on the host +host_inst_rate 171882 # Simulator instruction rate (inst/s) +host_op_rate 207819 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4390877747 # Simulator tick rate (ticks/s) +host_mem_usage 578076 # Number of bytes of host memory used +host_seconds 651.01 # Real time elapsed on the host sim_insts 111897168 # Number of instructions simulated sim_ops 135292215 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 9ae10924b..8cc8c8d31 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.832863 # Nu sim_ticks 2832862976500 # Number of ticks simulated final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87854 # Simulator instruction rate (inst/s) -host_op_rate 106560 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2200515158 # Simulator tick rate (ticks/s) -host_mem_usage 584732 # Number of bytes of host memory used -host_seconds 1287.36 # Real time elapsed on the host +host_inst_rate 92547 # Simulator instruction rate (inst/s) +host_op_rate 112251 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2318051416 # Simulator tick rate (ticks/s) +host_mem_usage 579360 # Number of bytes of host memory used +host_seconds 1222.09 # Real time elapsed on the host sim_insts 113100501 # Number of instructions simulated sim_ops 137180951 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index b0a0917e9..fccb40933 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,166 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.837405 # Number of seconds simulated -sim_ticks 2837404742000 # Number of ticks simulated -final_tick 2837404742000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.825951 # Number of seconds simulated +sim_ticks 2825951018000 # Number of ticks simulated +final_tick 2825951018000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116559 # Simulator instruction rate (inst/s) -host_op_rate 141347 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2740803117 # Simulator tick rate (ticks/s) -host_mem_usage 620980 # Number of bytes of host memory used -host_seconds 1035.25 # Real time elapsed on the host -sim_insts 120667663 # Number of instructions simulated -sim_ops 146328933 # Number of ops (including micro ops) simulated +host_inst_rate 126581 # Simulator instruction rate (inst/s) +host_op_rate 153564 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2973571752 # Simulator tick rate (ticks/s) +host_mem_usage 617520 # Number of bytes of host memory used +host_seconds 950.36 # Real time elapsed on the host +sim_insts 120297223 # Number of instructions simulated +sim_ops 145940268 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1294720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1292968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8487552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1286144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1281192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8384576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 177584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 590804 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 372608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 188912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 582932 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 428544 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12219756 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1294720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 177584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1472304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8624448 # Number of bytes written to this memory +system.physmem.bytes_read::total 12155436 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1286144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 188912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1475056 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8692480 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8642012 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22477 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20723 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 132618 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8710044 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22343 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20539 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 131009 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2843 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9252 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5822 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9129 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6696 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193790 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 134757 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192785 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 135820 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 139148 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 90 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 456304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 455687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2991308 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 180 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 140211 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 455119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 453367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2966993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 113 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 62587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 208220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 131320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4306667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 456304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 62587 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3039555 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 66849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 206278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 151646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4301361 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 455119 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 66849 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 521968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3075949 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6201 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3045745 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3039555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 90 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 456304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 461863 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2991308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3082164 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3075949 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 455119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 459568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2966993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 62587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 208234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 131320 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7352412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 193791 # Number of read requests accepted -system.physmem.writeReqs 139148 # Number of write requests accepted -system.physmem.readBursts 193791 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 139148 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12392320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10304 # Total number of bytes read from write queue -system.physmem.bytesWritten 8655168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12219820 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8642012 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu1.inst 66849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 206292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 151646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7383525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 192786 # Number of read requests accepted +system.physmem.writeReqs 140211 # Number of write requests accepted +system.physmem.readBursts 192786 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 140211 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12328960 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue +system.physmem.bytesWritten 8722752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12155500 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8710044 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12077 # Per bank write bursts -system.physmem.perBankRdBursts::1 11849 # Per bank write bursts -system.physmem.perBankRdBursts::2 12654 # Per bank write bursts -system.physmem.perBankRdBursts::3 12755 # Per bank write bursts -system.physmem.perBankRdBursts::4 14933 # Per bank write bursts -system.physmem.perBankRdBursts::5 12164 # Per bank write bursts -system.physmem.perBankRdBursts::6 12136 # Per bank write bursts -system.physmem.perBankRdBursts::7 11937 # Per bank write bursts -system.physmem.perBankRdBursts::8 12161 # Per bank write bursts -system.physmem.perBankRdBursts::9 11860 # Per bank write bursts -system.physmem.perBankRdBursts::10 11714 # Per bank write bursts -system.physmem.perBankRdBursts::11 10962 # Per bank write bursts -system.physmem.perBankRdBursts::12 11429 # Per bank write bursts -system.physmem.perBankRdBursts::13 12078 # Per bank write bursts -system.physmem.perBankRdBursts::14 11741 # Per bank write bursts -system.physmem.perBankRdBursts::15 11180 # Per bank write bursts -system.physmem.perBankWrBursts::0 8714 # Per bank write bursts -system.physmem.perBankWrBursts::1 8695 # Per bank write bursts -system.physmem.perBankWrBursts::2 9246 # Per bank write bursts +system.physmem.perBankRdBursts::0 11498 # Per bank write bursts +system.physmem.perBankRdBursts::1 11843 # Per bank write bursts +system.physmem.perBankRdBursts::2 12508 # Per bank write bursts +system.physmem.perBankRdBursts::3 12790 # Per bank write bursts +system.physmem.perBankRdBursts::4 14191 # Per bank write bursts +system.physmem.perBankRdBursts::5 11869 # Per bank write bursts +system.physmem.perBankRdBursts::6 11798 # Per bank write bursts +system.physmem.perBankRdBursts::7 11857 # Per bank write bursts +system.physmem.perBankRdBursts::8 12385 # Per bank write bursts +system.physmem.perBankRdBursts::9 12638 # Per bank write bursts +system.physmem.perBankRdBursts::10 11524 # Per bank write bursts +system.physmem.perBankRdBursts::11 10795 # Per bank write bursts +system.physmem.perBankRdBursts::12 11419 # Per bank write bursts +system.physmem.perBankRdBursts::13 12202 # Per bank write bursts +system.physmem.perBankRdBursts::14 11695 # Per bank write bursts +system.physmem.perBankRdBursts::15 11628 # Per bank write bursts +system.physmem.perBankWrBursts::0 8335 # Per bank write bursts +system.physmem.perBankWrBursts::1 8752 # Per bank write bursts +system.physmem.perBankWrBursts::2 9292 # Per bank write bursts system.physmem.perBankWrBursts::3 9229 # Per bank write bursts -system.physmem.perBankWrBursts::4 8656 # Per bank write bursts -system.physmem.perBankWrBursts::5 8632 # Per bank write bursts -system.physmem.perBankWrBursts::6 8647 # Per bank write bursts -system.physmem.perBankWrBursts::7 8231 # Per bank write bursts -system.physmem.perBankWrBursts::8 8368 # Per bank write bursts -system.physmem.perBankWrBursts::9 8311 # Per bank write bursts -system.physmem.perBankWrBursts::10 8380 # Per bank write bursts -system.physmem.perBankWrBursts::11 8024 # Per bank write bursts -system.physmem.perBankWrBursts::12 8294 # Per bank write bursts -system.physmem.perBankWrBursts::13 8191 # Per bank write bursts -system.physmem.perBankWrBursts::14 8117 # Per bank write bursts -system.physmem.perBankWrBursts::15 7502 # Per bank write bursts +system.physmem.perBankWrBursts::4 7962 # Per bank write bursts +system.physmem.perBankWrBursts::5 8394 # Per bank write bursts +system.physmem.perBankWrBursts::6 8300 # Per bank write bursts +system.physmem.perBankWrBursts::7 8278 # Per bank write bursts +system.physmem.perBankWrBursts::8 8796 # Per bank write bursts +system.physmem.perBankWrBursts::9 9162 # Per bank write bursts +system.physmem.perBankWrBursts::10 8546 # Per bank write bursts +system.physmem.perBankWrBursts::11 8147 # Per bank write bursts +system.physmem.perBankWrBursts::12 8256 # Per bank write bursts +system.physmem.perBankWrBursts::13 8410 # Per bank write bursts +system.physmem.perBankWrBursts::14 8295 # Per bank write bursts +system.physmem.perBankWrBursts::15 8139 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 16 # Number of times write queue was full causing retry -system.physmem.totGap 2837404463500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 2825950731000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3087 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 190125 # Read request sizes (log2) +system.physmem.readPktSize::6 189120 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 134757 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 61827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 74131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 813 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 135820 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 58633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 71115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 653 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -188,160 +188,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 60 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87851 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 239.580927 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 135.192901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 302.402140 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47357 53.91% 53.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17068 19.43% 73.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5804 6.61% 79.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3391 3.86% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2670 3.04% 86.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1518 1.73% 88.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 937 1.07% 89.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 934 1.06% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8172 9.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87851 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6505 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.766180 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 576.399644 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6503 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6505 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6505 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.789700 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.910113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.034203 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5345 82.17% 82.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 508 7.81% 89.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 102 1.57% 91.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 40 0.61% 92.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 39 0.60% 92.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 25 0.38% 93.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 50 0.77% 93.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 17 0.26% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 116 1.78% 95.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 12 0.18% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.11% 96.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 11 0.17% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 77 1.18% 97.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.11% 97.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.08% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 26 0.40% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 87 1.34% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.05% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 9 0.14% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.08% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6505 # Writes before turning the bus around for reads -system.physmem.totQLat 6373061511 # Total ticks spent queuing -system.physmem.totMemAccLat 10003624011 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 968150000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32913.61 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 88838 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 236.966703 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.563892 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.532977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 48504 54.60% 54.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17119 19.27% 73.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5692 6.41% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3330 3.75% 84.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2666 3.00% 87.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1452 1.63% 88.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 904 1.02% 89.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1002 1.13% 90.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8169 9.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88838 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6725 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.644610 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 576.008815 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6723 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6725 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6725 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.266617 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.732165 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.286650 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5583 83.02% 83.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 392 5.83% 88.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 83 1.23% 90.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 55 0.82% 90.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 273 4.06% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 27 0.40% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 22 0.33% 95.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 18 0.27% 95.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 21 0.31% 96.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 12 0.18% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 9 0.13% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 9 0.13% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 148 2.20% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 9 0.13% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.10% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 7 0.10% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 12 0.18% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.04% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 4 0.06% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.16% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6725 # Writes before turning the bus around for reads +system.physmem.totQLat 6328126220 # Total ticks spent queuing +system.physmem.totMemAccLat 9940126220 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 963200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32849.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51663.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.05 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51599.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.09 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.30 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.08 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing -system.physmem.readRowHits 161607 # Number of row buffer hits during reads -system.physmem.writeRowHits 79408 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.71 # Row buffer hit rate for writes -system.physmem.avgGap 8522295.27 # Average gap between requests -system.physmem.pageHitRate 73.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 346988880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 189329250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 783931200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 453924000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185325366720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 80760068955 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1631599751250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1899459360255 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.435829 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2714212324269 # Time in different power states -system.physmem_0.memoryStateTime::REF 94747120000 # Time in different power states +system.physmem.avgWrQLen 21.86 # Average write queue length when enqueuing +system.physmem.readRowHits 160949 # Number of row buffer hits during reads +system.physmem.writeRowHits 79145 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.06 # Row buffer hit rate for writes +system.physmem.avgGap 8486414.99 # Average gap between requests +system.physmem.pageHitRate 72.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 340562880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 185823000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 767153400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 444152160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184577274960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 79601761125 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625743658250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1891660385775 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.389284 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2704476978140 # Time in different power states +system.physmem_0.memoryStateTime::REF 94364660000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28445283231 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27109359860 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 317164680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 173056125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 726375000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 422411760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185325366720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80003948850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1632263014500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1899231337635 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.355466 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2715316377598 # Time in different power states -system.physmem_1.memoryStateTime::REF 94747120000 # Time in different power states +system.physmem_1.actEnergy 331052400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 180633750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 735430800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 439026480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184577274960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79228268055 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626071283750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1891562970195 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.354813 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2705022466825 # Time in different power states +system.physmem_1.memoryStateTime::REF 94364660000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27339711152 # Time in different power states +system.physmem_1.memoryStateTime::ACT 26562494425 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory @@ -352,13 +354,13 @@ system.realview.nvmem.bytes_inst_read::total 288 system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 39 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 39 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 39 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). @@ -367,19 +369,19 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 53928985 # Number of BP lookups -system.cpu0.branchPred.condPredicted 24980647 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 980964 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 32646997 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 14259525 # Number of BTB hits +system.cpu0.branchPred.lookups 23820996 # Number of BP lookups +system.cpu0.branchPred.condPredicted 15588859 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 920395 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 14518297 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 9504336 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 43.677907 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15577797 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 34581 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 10158007 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 9989505 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 168502 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 52676 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 65.464538 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3840995 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33136 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 1356781 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 1203053 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 153728 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 48358 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -410,86 +412,82 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 71164 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 71164 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25792 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21511 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 23861 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 47303 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 513.360675 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3057.570781 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 45975 97.19% 97.19% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 952 2.01% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 188 0.40% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 150 0.32% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 13 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 66654 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 66654 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25108 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18968 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 22578 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 44076 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 460.137036 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 2988.406264 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 42948 97.44% 97.44% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 855 1.94% 99.38% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 123 0.28% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 110 0.25% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 6 0.01% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 13 0.03% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 47303 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 18252 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 10854.262547 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9468.640105 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6407.913673 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 18169 99.55% 99.55% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 76 0.42% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 6 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 18252 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 80034835468 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.679509 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.477500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 25803805568 32.24% 32.24% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 54166837400 67.68% 99.92% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2 30476500 0.04% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::3 15818500 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4 5905000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::5 3281500 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6 3666500 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::7 1298500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8 960000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::9 729000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10 669000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::11 276500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12 755500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::13 113500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14 120500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::15 122000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 80034835468 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5842 79.40% 79.40% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1516 20.60% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 7358 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71164 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 44076 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 16898 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11121.375311 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9757.603879 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6791.562531 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 15594 92.28% 92.28% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1190 7.04% 99.33% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 80 0.47% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 11 0.07% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 8 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 13 0.08% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-245759 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 16898 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 90055870948 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.547875 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.509370 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 89997968948 99.94% 99.94% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 40556500 0.05% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 7037000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 4893500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 1776500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 1132500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 1239500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 1264500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 2000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 90055870948 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5227 78.38% 78.38% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1442 21.62% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6669 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66654 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71164 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7358 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66654 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6669 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7358 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 78522 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6669 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 73323 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 24435903 # DTB read hits -system.cpu0.dtb.read_misses 60770 # DTB read misses -system.cpu0.dtb.write_hits 18100495 # DTB write hits -system.cpu0.dtb.write_misses 10394 # DTB write misses +system.cpu0.dtb.read_hits 17666854 # DTB read hits +system.cpu0.dtb.read_misses 56136 # DTB read misses +system.cpu0.dtb.write_hits 14559303 # DTB write hits +system.cpu0.dtb.write_misses 10518 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3811 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 278 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2366 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3504 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 145 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2262 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 972 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24496673 # DTB read accesses -system.cpu0.dtb.write_accesses 18110889 # DTB write accesses +system.cpu0.dtb.perms_faults 861 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17722990 # DTB read accesses +system.cpu0.dtb.write_accesses 14569821 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 42536398 # DTB hits -system.cpu0.dtb.misses 71164 # DTB misses -system.cpu0.dtb.accesses 42607562 # DTB accesses +system.cpu0.dtb.hits 32226157 # DTB hits +system.cpu0.dtb.misses 66654 # DTB misses +system.cpu0.dtb.accesses 32292811 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -519,55 +517,58 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 11512 # Table walker walks requested -system.cpu0.itb.walker.walksShort 11512 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3903 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6443 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 1166 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 10346 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 443.263097 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2195.478359 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9924 95.92% 95.92% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 200 1.93% 97.85% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 136 1.31% 99.17% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 57 0.55% 99.72% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 9 0.09% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 14 0.14% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 10841 # Table walker walks requested +system.cpu0.itb.walker.walksShort 10841 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3909 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5864 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 1068 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 9773 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 421.927760 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2234.177799 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9414 96.33% 96.33% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 161 1.65% 97.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 108 1.11% 99.08% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 59 0.60% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 8 0.08% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 12 0.12% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.95% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 10346 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 4037 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 11847.659153 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 10978.083476 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5361.043324 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 3811 94.40% 94.40% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 205 5.08% 99.48% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 19 0.47% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::147456-163839 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 4037 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 19905249824 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.798667 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.401122 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 4008511500 20.14% 20.14% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 15895875324 79.86% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 9773 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3645 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12199.451303 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11419.234768 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4654.618910 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 570 15.64% 15.64% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 2859 78.44% 94.07% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 148 4.06% 98.13% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 43 1.18% 99.31% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 22 0.60% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 3645 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 21336382212 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.847765 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.359386 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 3249113500 15.23% 15.23% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 18086389212 84.77% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::2 793000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 19905249824 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2512 87.50% 87.50% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 359 12.50% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2871 # Table walker page sizes translated +system.cpu0.itb.walker.walksPending::3 86500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 21336382212 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2247 87.19% 87.19% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 330 12.81% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2577 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11512 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11512 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10841 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10841 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2871 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2871 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 14383 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 74030113 # ITB inst hits -system.cpu0.itb.inst_misses 11512 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2577 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2577 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 13418 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 37363257 # ITB inst hits +system.cpu0.itb.inst_misses 10841 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -576,1016 +577,1022 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2605 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2348 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 2155 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1915 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74041625 # ITB inst accesses -system.cpu0.itb.hits 74030113 # DTB hits -system.cpu0.itb.misses 11512 # DTB misses -system.cpu0.itb.accesses 74041625 # DTB accesses -system.cpu0.numCycles 210680851 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 37374098 # ITB inst accesses +system.cpu0.itb.hits 37363257 # DTB hits +system.cpu0.itb.misses 10841 # DTB misses +system.cpu0.itb.accesses 37374098 # DTB accesses +system.cpu0.numCycles 130634754 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 21171726 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 200049751 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 53928985 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 39826827 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 180241612 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 5811272 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 155130 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 70350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 431363 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 450452 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 103873 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 74029415 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 271959 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 5637 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 205530142 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.189019 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.306227 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 18759180 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 111594210 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 23820996 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 14548384 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 105958075 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2723782 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 147803 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 57411 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 403538 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 420731 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 91570 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 37362977 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 256682 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 5313 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 127200199 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.057439 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.258294 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 98403220 47.88% 47.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 31059279 15.11% 62.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 14883047 7.24% 70.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 61184596 29.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 65301995 51.34% 51.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 21243041 16.70% 68.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 8702131 6.84% 74.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 31953032 25.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 205530142 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.255975 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.949539 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26358424 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 111125063 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 60339651 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 5146338 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2560666 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3166290 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 349435 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 158330686 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3996082 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 2560666 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 35191325 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 13316748 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 85113900 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 56510449 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 12837054 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 141455630 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1082284 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1522598 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 176451 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 63363 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 8486313 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 145805955 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 652241827 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 157050612 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 10963 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 133960988 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11844956 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 2734835 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 2587650 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 23017642 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 25406580 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 19629611 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1770048 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2573383 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 138387691 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1764615 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 136383682 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 482804 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11087380 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 22916211 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 126267 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 205530142 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.663570 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.962312 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 127200199 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.182348 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.854246 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19580299 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 60730761 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 40895062 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4960019 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1034058 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3027631 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 331959 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 109730420 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3757258 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1034058 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 25213970 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12473804 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 37385885 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 40084231 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11008251 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 104776923 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1005898 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1454281 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 163264 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 59868 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 6802738 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 108917617 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 478329249 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 119800886 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9453 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 97884799 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11032807 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1224750 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1083467 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12359769 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 18590109 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 16025944 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1692928 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2223672 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 101900058 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1687234 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 100089682 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 451563 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 8991464 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 21250511 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 118873 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 127200199 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.786867 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.029325 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 126796339 61.69% 61.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 34494575 16.78% 78.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 31991292 15.57% 94.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 11085283 5.39% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1162591 0.57% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 62 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 71273767 56.03% 56.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 23216726 18.25% 74.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 22358125 17.58% 91.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 9249672 7.27% 99.13% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1101855 0.87% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 54 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 205530142 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 127200199 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 11095363 43.83% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 72 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5922142 23.40% 67.23% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8295120 32.77% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 9294441 40.55% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 68 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5565368 24.28% 64.83% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8061478 35.17% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2315 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 91932498 67.41% 67.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 113960 0.08% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.49% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8109 0.01% 67.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.50% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.50% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 25157178 18.45% 85.94% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 19169621 14.06% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 66026932 65.97% 65.97% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 92216 0.09% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8071 0.01% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 18353253 18.34% 84.41% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 15606936 15.59% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 136383682 # Type of FU issued -system.cpu0.iq.rate 0.647347 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 25312697 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.185599 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 504054876 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 151247362 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 132748931 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 38130 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 13196 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 11435 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 161669314 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 24750 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 382212 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 100089682 # Type of FU issued +system.cpu0.iq.rate 0.766180 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 22921355 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.229008 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 350720067 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 112586232 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 98062666 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 32413 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11362 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 9718 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 122987773 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 20991 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 362703 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2031269 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2587 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 20948 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 944545 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1887830 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2440 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18911 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 876012 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 125569 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 392740 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 109448 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 364606 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2560666 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1904881 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 242910 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 140340084 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 1034058 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1622257 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 187065 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 103740401 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 25406580 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 19629611 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 903245 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 30849 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 186908 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 20948 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 273967 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 422470 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 696437 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 135301485 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 24689718 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1011162 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 18590109 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 16025944 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 873149 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 28190 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 135133 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18911 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 251727 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 397563 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 649290 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 99070135 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 17913102 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 953014 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 187778 # number of nop insts executed -system.cpu0.iew.exec_refs 43692090 # number of memory reference insts executed -system.cpu0.iew.exec_branches 26150301 # Number of branches executed -system.cpu0.iew.exec_stores 19002372 # Number of stores executed -system.cpu0.iew.exec_rate 0.642211 # Inst execution rate -system.cpu0.iew.wb_sent 134704568 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 132760366 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 67768009 # num instructions producing a value -system.cpu0.iew.wb_consumers 109468646 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.630149 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.619063 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 10008673 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1638348 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 635994 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 202285941 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.638783 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.339502 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 153109 # number of nop insts executed +system.cpu0.iew.exec_refs 33359413 # number of memory reference insts executed +system.cpu0.iew.exec_branches 16770669 # Number of branches executed +system.cpu0.iew.exec_stores 15446311 # Number of stores executed +system.cpu0.iew.exec_rate 0.758375 # Inst execution rate +system.cpu0.iew.wb_sent 98522156 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 98072384 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 51087973 # num instructions producing a value +system.cpu0.iew.wb_consumers 84406715 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.750737 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.605260 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 7992419 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1568361 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 592562 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 125525573 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.754570 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.472389 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 140398916 69.41% 69.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 34201466 16.91% 86.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 12970060 6.41% 92.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3407217 1.68% 94.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 4957947 2.45% 96.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 2836864 1.40% 98.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1346808 0.67% 98.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 576737 0.29% 99.21% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1589926 0.79% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 81342054 64.80% 64.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 24610935 19.61% 84.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 8228457 6.56% 90.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3212332 2.56% 93.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 3423017 2.73% 96.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 1492381 1.19% 97.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1160319 0.92% 98.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 551485 0.44% 98.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1504593 1.20% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 202285941 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 106719327 # Number of instructions committed -system.cpu0.commit.committedOps 129216760 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 125525573 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 78721743 # Number of instructions committed +system.cpu0.commit.committedOps 94717871 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 42060376 # Number of memory references committed -system.cpu0.commit.loads 23375310 # Number of loads committed -system.cpu0.commit.membars 665131 # Number of memory barriers committed -system.cpu0.commit.branches 25508530 # Number of branches committed -system.cpu0.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 112737159 # Number of committed integer instructions. -system.cpu0.commit.function_calls 4888773 # Number of function calls committed. +system.cpu0.commit.refs 31852210 # Number of memory references committed +system.cpu0.commit.loads 16702278 # Number of loads committed +system.cpu0.commit.membars 645830 # Number of memory barriers committed +system.cpu0.commit.branches 16170329 # Number of branches committed +system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 81695650 # Number of committed integer instructions. +system.cpu0.commit.function_calls 1925626 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 87036683 67.36% 67.36% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 111592 0.09% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8109 0.01% 67.45% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.45% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.45% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.45% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 23375310 18.09% 85.54% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 18685066 14.46% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 62767692 66.27% 66.27% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 89898 0.09% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.36% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8071 0.01% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 16702278 17.63% 84.01% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 15149932 15.99% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 129216760 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1589926 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 316533140 # The number of ROB reads -system.cpu0.rob.rob_writes 281685162 # The number of ROB writes -system.cpu0.timesIdled 132617 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5150709 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5464128831 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 106567484 # Number of Instructions Simulated -system.cpu0.committedOps 129064917 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.976971 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.976971 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.505824 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.505824 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 146676309 # number of integer regfile reads -system.cpu0.int_regfile_writes 83772418 # number of integer regfile writes -system.cpu0.fp_regfile_reads 9577 # number of floating regfile reads -system.cpu0.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu0.cc_regfile_reads 477802916 # number of cc regfile reads -system.cpu0.cc_regfile_writes 51327219 # number of cc regfile writes -system.cpu0.misc_regfile_reads 282498014 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1261276 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 747573 # number of replacements -system.cpu0.dcache.tags.tagsinuse 499.341020 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 38792744 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 748085 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.856064 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.341020 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975275 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.975275 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 94717871 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1504593 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 222549197 # The number of ROB reads +system.cpu0.rob.rob_writes 207085893 # The number of ROB writes +system.cpu0.timesIdled 123342 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3434555 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5521267593 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 78599691 # Number of Instructions Simulated +system.cpu0.committedOps 94595819 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.662026 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.662026 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.601675 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.601675 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 110021691 # number of integer regfile reads +system.cpu0.int_regfile_writes 59386115 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8176 # number of floating regfile reads +system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes +system.cpu0.cc_regfile_reads 349047979 # number of cc regfile reads +system.cpu0.cc_regfile_writes 40883845 # number of cc regfile writes +system.cpu0.misc_regfile_reads 177564457 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1222085 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 709600 # number of replacements +system.cpu0.dcache.tags.tagsinuse 499.965510 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 28702051 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 710112 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 40.419048 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 278078500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.965510 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.976495 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.976495 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 334 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 83715991 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 83715991 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 22140887 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 22140887 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15403032 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15403032 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 315432 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 315432 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 371543 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 371543 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 369802 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 369802 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 37543919 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 37543919 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 37859351 # number of overall hits -system.cpu0.dcache.overall_hits::total 37859351 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 684637 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 684637 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1972030 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1972030 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 153419 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 153419 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25627 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 25627 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20274 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20274 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2656667 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2656667 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2810086 # number of overall misses -system.cpu0.dcache.overall_misses::total 2810086 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9946449500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 9946449500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36588625370 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 36588625370 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 415520500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 415520500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 535292500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 535292500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 777000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 777000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 46535074870 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 46535074870 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 46535074870 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 46535074870 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 22825524 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 22825524 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17375062 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17375062 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 468851 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 468851 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397170 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 397170 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390076 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 390076 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 40200586 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 40200586 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 40669437 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 40669437 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029994 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029994 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113498 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.113498 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.327223 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.327223 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064524 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064524 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051974 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051974 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.066085 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.066085 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069096 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.069096 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14528.063047 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14528.063047 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18553.787402 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18553.787402 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16214.168650 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16214.168650 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26402.905199 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26402.905199 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63247390 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63247390 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15498209 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15498209 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 11982969 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 11982969 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307264 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 307264 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 362251 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 362251 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360359 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 360359 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 27481178 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 27481178 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 27788442 # number of overall hits +system.cpu0.dcache.overall_hits::total 27788442 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 646938 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 646938 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1889976 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1889976 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147980 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 147980 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25182 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 25182 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20295 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20295 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2536914 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2536914 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2684894 # number of overall misses +system.cpu0.dcache.overall_misses::total 2684894 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8613079000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8613079000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29673912872 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 29673912872 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 399362500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 399362500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 493278500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 493278500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 493500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 493500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 38286991872 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 38286991872 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 38286991872 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 38286991872 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16145147 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16145147 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13872945 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13872945 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 455244 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 455244 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387433 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 387433 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 380654 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 380654 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30018092 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30018092 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30473336 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30473336 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040070 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.040070 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136235 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.136235 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325056 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325056 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064997 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064997 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053316 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053316 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084513 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.084513 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088106 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.088106 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13313.608105 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13313.608105 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15700.682375 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15700.682375 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15859.046144 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15859.046144 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24305.420054 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24305.420054 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17516.337151 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 17516.337151 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16560.018046 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 16560.018046 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1975 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5610717 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 47 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 211787 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 42.021277 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 26.492263 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 747573 # number of writebacks -system.cpu0.dcache.writebacks::total 747573 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276373 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 276373 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1635448 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1635448 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18943 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18943 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1911821 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1911821 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1911821 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1911821 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 408264 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 408264 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 336582 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 336582 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106895 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 106895 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6684 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6684 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20274 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20274 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 744846 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 744846 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 851741 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 851741 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31822 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31822 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28485 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28485 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60307 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60307 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5115635000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5115635000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7714022398 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7714022398 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1800093000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1800093000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 106991500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 106991500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 515034500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 515034500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 761000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 761000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12829657398 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12829657398 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14629750398 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14629750398 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6627444500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6627444500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6627444500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6627444500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017886 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017886 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019372 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019372 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.227994 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227994 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016829 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016829 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051974 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051974 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018528 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.018528 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020943 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020943 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12530.213293 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12530.213293 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22918.701529 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22918.701529 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16839.824126 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16839.824126 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16007.106523 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16007.106523 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25403.694387 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25403.694387 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15091.954978 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15091.954978 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14260.150260 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14260.150260 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1062 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4223116 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 45 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 202030 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.600000 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 20.903410 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 709603 # number of writebacks +system.cpu0.dcache.writebacks::total 709603 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260771 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 260771 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1564893 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1564893 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18568 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18568 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1825664 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1825664 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1825664 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1825664 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 386167 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386167 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325083 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325083 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102058 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 102058 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6614 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6614 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20295 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20295 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 711250 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 711250 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 813308 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 813308 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20340 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20340 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19033 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19033 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39373 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39373 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4553087000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4553087000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6070046902 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6070046902 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1659761500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1659761500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 103454000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103454000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 472996500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 472996500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 480500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 480500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10623133902 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10623133902 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12282895402 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12282895402 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4534665000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4534665000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4534665000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4534665000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023918 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023918 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023433 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023433 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224183 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224183 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017071 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017071 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053316 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053316 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023694 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023694 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026689 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026689 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11790.461122 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11790.461122 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18672.298773 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18672.298773 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16262.924024 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16262.924024 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15641.669187 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15641.669187 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23306.060606 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23306.060606 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17224.577158 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17224.577158 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17176.289973 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17176.289973 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208266.120923 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208266.120923 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109895.111679 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109895.111679 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 1304852 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.377336 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 72663769 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1305364 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 55.665522 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8205905000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.377336 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998784 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998784 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14935.864889 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14935.864889 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15102.390979 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15102.390979 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222943.215339 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222943.215339 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115171.945242 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115171.945242 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 1244973 # 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Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 149356824 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 149356824 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 72663769 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 72663769 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 72663769 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 72663769 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 72663769 # number of overall hits -system.cpu0.icache.overall_hits::total 72663769 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1361937 # 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miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10955.670569 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10955.670569 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10955.670569 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10955.670569 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10955.670569 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10955.670569 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1976630 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1824 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 119804 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.498865 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 121.600000 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1304852 # number of writebacks -system.cpu0.icache.writebacks::total 1304852 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56524 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 56524 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 56524 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 56524 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 56524 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 56524 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1305413 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1305413 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1305413 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1305413 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1305413 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1305413 # number of overall MSHR misses +system.cpu0.icache.tags.tag_accesses 75964361 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 75964361 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 36061117 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36061117 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36061117 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36061117 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36061117 # number of overall hits +system.cpu0.icache.overall_hits::total 36061117 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1298298 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1298298 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1298298 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1298298 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1298298 # number of overall misses +system.cpu0.icache.overall_misses::total 1298298 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13095750432 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13095750432 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13095750432 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13095750432 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13095750432 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13095750432 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 37359415 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 37359415 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 37359415 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 37359415 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 37359415 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 37359415 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034752 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.034752 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034752 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.034752 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034752 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.034752 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10086.860206 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10086.860206 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10086.860206 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10086.860206 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10086.860206 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10086.860206 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1564537 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 822 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 111550 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.025433 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 74.727273 # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 1244973 # number of writebacks +system.cpu0.icache.writebacks::total 1244973 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 52766 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 52766 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 52766 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 52766 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 52766 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 52766 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1245532 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1245532 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1245532 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1245532 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1245532 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1245532 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13391499134 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 13391499134 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13391499134 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 13391499134 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13391499134 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 13391499134 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420576498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420576498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420576498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 420576498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017635 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017635 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017635 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.017635 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017635 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.017635 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10258.438620 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10258.438620 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10258.438620 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10258.438620 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10258.438620 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10258.438620 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140052.113886 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140052.113886 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140052.113886 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140052.113886 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1921401 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1924253 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2599 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11887458427 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11887458427 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11887458427 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11887458427 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11887458427 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11887458427 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 269145498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 269145498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 269145498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 269145498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033339 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033339 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033339 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.033339 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033339 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.033339 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9544.081105 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9544.081105 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9544.081105 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9544.081105 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9544.081105 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9544.081105 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1836444 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1838932 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 2249 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 246531 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 284359 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16097.390005 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3405020 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 300497 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.331294 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 237260 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 275777 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16077.094616 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3264993 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 291873 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 11.186348 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14688.513215 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.811138 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.794692 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1396.270960 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.896516 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000721 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000049 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.085222 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.982507 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 968 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15161 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 20 # 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number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4081426997 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15061119493 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 21578889990 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 246621000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4371667500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4618288500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 246621000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4371667500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4618288500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007253 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010796 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.007934 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackDirty accesses +system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackDirty accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.151684 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.151684 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042866 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042866 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.185948 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.185948 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.005868 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.006838 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042866 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.173957 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.089817 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.005868 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.006838 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042866 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.173957 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158659 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158659 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041868 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041868 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.193325 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.193325 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007253 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.010796 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041868 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181091 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.091906 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007253 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.010796 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041868 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181091 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.208656 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27335.211268 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21838.541667 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26165.188470 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83862.236822 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83862.236822 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26242.593388 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26242.593388 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.536352 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17849.536352 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.214963 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21942.542787 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17851.724138 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20871.841155 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58846.520042 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58846.520042 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19508.249932 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19508.249932 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15749.248534 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15749.248534 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57928.589870 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57928.589870 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 62123.918793 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62123.918793 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28665.101564 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28665.101564 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27335.211268 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21838.541667 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 62123.918793 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37595.119561 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44570.615622 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27335.211268 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21838.541667 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62123.918793 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37595.119561 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83862.236822 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66949.015881 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200256.850606 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194418.549892 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105668.885867 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 106944.021482 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 4258986 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2151003 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32472 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 329266 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 324071 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5195 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 120454 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1996565 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28485 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28485 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 738714 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1547561 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 211301 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 317009 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 86208 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42633 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113720 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 299261 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 296052 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1305413 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 592862 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3357 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3921638 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2727487 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 30828 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 129308 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6809261 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 167102064 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103511640 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 56156 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 241976 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 270911836 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1020612 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3240855 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.120146 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.330026 # Request fanout histogram +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41371.784988 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41371.784988 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46498.945289 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46498.945289 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24156.760003 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24156.760003 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21942.542787 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17851.724138 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46498.945289 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29479.429375 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34097.496205 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21942.542787 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17851.724138 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46498.945289 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29479.429375 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58846.520042 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48265.203852 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 214929.572271 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197844.685773 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111032.115917 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 108983.587408 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 4059553 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2049525 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31130 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 322631 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 318742 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3889 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 102054 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1891052 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19033 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19033 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 711408 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1472505 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 201922 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 326386 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87454 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42857 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113442 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 28 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 288333 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284690 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1245532 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 576445 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3297 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3742005 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2570285 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29068 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119436 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6460794 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 159437936 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98528220 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53724 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 225568 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 258245448 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1026066 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3122672 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.120692 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.329569 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2856673 88.15% 88.15% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 378987 11.69% 99.84% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 5195 0.16% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2749681 88.06% 88.06% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 369102 11.82% 99.88% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 3889 0.12% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3240855 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 4259428994 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115114135 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3122672 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 4044815993 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114413841 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1961743252 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1871838919 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1289450748 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1215906771 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 16799978 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 15648976 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 68856412 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 63082921 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 3975194 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2297364 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 224488 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2012976 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1308063 # Number of BTB hits +system.cpu1.branchPred.lookups 34009026 # Number of BP lookups +system.cpu1.branchPred.condPredicted 11598982 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 286954 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 18822923 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 6035110 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 64.981550 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 784876 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 5668 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 213732 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 189273 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 24459 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 5870 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 32.062555 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 12529712 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7339 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 9024222 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 8987643 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 36579 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 11117 # Number of mispredicted indirect branches. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1615,90 +1622,93 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 15858 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 15858 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8476 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3068 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 4314 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 11544 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 612.006237 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3319.733995 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 11004 95.32% 95.32% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 170 1.47% 96.79% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 217 1.88% 98.67% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 35 0.30% 98.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 27 0.23% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 16 0.14% 99.35% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 4 0.03% 99.38% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 61 0.53% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 4 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::45056-49151 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 11544 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 3223 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11620.074465 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10250.129632 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7588.563203 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 2748 85.26% 85.26% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 431 13.37% 98.63% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 35 1.09% 99.72% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 6 0.19% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-147455 2 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 3223 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 88338958560 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.197151 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.399884 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 70951902092 80.32% 80.32% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 17371924968 19.67% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2 10393500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::3 1802000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4 890500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::5 405500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6 991000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::7 249000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8 24000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::9 135000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10 9000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::11 41000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12 36000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::13 10500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14 6000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::15 138500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 88338958560 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1231 73.23% 73.23% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 450 26.77% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1681 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15858 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 22019 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 22019 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8988 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5922 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 7109 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 14910 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 597.183099 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3274.563107 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 14271 95.71% 95.71% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 175 1.17% 96.89% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 226 1.52% 98.40% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 97 0.65% 99.05% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 36 0.24% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 18 0.12% 99.42% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 9 0.06% 99.48% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 63 0.42% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 6 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 4 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::53248-57343 3 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 14910 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5586 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11231.919083 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9899.070869 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6145.006909 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1859 33.28% 33.28% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3110 55.67% 88.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 395 7.07% 96.03% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 162 2.90% 98.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 30 0.54% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 25 0.45% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5586 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 72596800264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.178979 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.387926 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 59651088264 82.17% 82.17% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 12923549000 17.80% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 13278500 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 4124000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 1159000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 892500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 1267000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 399000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 261000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 175000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 102500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 47000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 179500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 63000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 38500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 176500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 72596800264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1935 74.77% 74.77% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 653 25.23% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 22019 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15858 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1681 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 22019 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1681 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 17539 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 24607 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3568678 # DTB read hits -system.cpu1.dtb.read_misses 13961 # DTB read misses -system.cpu1.dtb.write_hits 3021632 # DTB write hits -system.cpu1.dtb.write_misses 1897 # DTB write misses +system.cpu1.dtb.read_hits 10217146 # DTB read hits +system.cpu1.dtb.read_misses 19031 # DTB read misses +system.cpu1.dtb.write_hits 6545704 # DTB write hits +system.cpu1.dtb.write_misses 2988 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1646 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 39 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 351 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2034 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 49 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 375 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 252 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3582639 # DTB read accesses -system.cpu1.dtb.write_accesses 3023529 # DTB write accesses +system.cpu1.dtb.perms_faults 389 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10236177 # DTB read accesses +system.cpu1.dtb.write_accesses 6548692 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6590310 # DTB hits -system.cpu1.dtb.misses 15858 # DTB misses -system.cpu1.dtb.accesses 6606168 # DTB accesses +system.cpu1.dtb.hits 16762850 # DTB hits +system.cpu1.dtb.misses 22019 # DTB misses +system.cpu1.dtb.accesses 16784869 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1728,56 +1738,58 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 5405 # Table walker walks requested -system.cpu1.itb.walker.walksShort 5405 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2736 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2193 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 476 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 4929 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 233.921688 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 1867.315872 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-4095 4828 97.95% 97.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-8191 62 1.26% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-12287 17 0.34% 99.55% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-16383 7 0.14% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-20479 2 0.04% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-28671 8 0.16% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::28672-32767 2 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-36863 3 0.06% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 4929 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1313 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11012.566641 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10237.942197 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4989.359306 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 243 18.51% 18.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 995 75.78% 94.29% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 50 3.81% 98.10% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 10 0.76% 98.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 8 0.61% 99.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 4 0.30% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.15% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::81920-90111 1 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1313 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 15319490028 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.914748 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.279455 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1306821764 8.53% 8.53% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 14011918764 91.46% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 701000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 48500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 15319490028 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 694 82.92% 82.92% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 143 17.08% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 837 # Table walker page sizes translated +system.cpu1.itb.walker.walks 6065 # Table walker walks requested +system.cpu1.itb.walker.walksShort 6065 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2849 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2599 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 617 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 300.018355 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 2054.443929 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-4095 5317 97.60% 97.60% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-8191 57 1.05% 98.64% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-12287 30 0.55% 99.19% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-16383 22 0.40% 99.60% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-20479 8 0.15% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.07% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-28671 5 0.09% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::28672-32767 3 0.06% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-36863 2 0.04% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1777 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11882.104671 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10854.352895 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5876.427895 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 298 16.77% 16.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1356 76.31% 93.08% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 64 3.60% 96.68% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 25 1.41% 98.09% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 23 1.29% 99.38% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 4 0.23% 99.61% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-57343 3 0.17% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-65535 3 0.17% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1777 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 16742440916 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.881191 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.323702 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1989886764 11.89% 11.89% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 14751845152 88.11% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 691000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 18000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 16742440916 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 988 85.17% 85.17% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 172 14.83% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1160 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5405 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5405 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6065 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6065 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 837 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 837 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 6242 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 7144027 # ITB inst hits -system.cpu1.itb.inst_misses 5405 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1160 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1160 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 7225 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 43720811 # ITB inst hits +system.cpu1.itb.inst_misses 6065 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1786,1008 +1798,1009 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 901 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1192 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 383 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 560 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7149432 # ITB inst accesses -system.cpu1.itb.hits 7144027 # DTB hits -system.cpu1.itb.misses 5405 # DTB misses -system.cpu1.itb.accesses 7149432 # DTB accesses -system.cpu1.numCycles 32549087 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 43726876 # ITB inst accesses +system.cpu1.itb.hits 43720811 # DTB hits +system.cpu1.itb.misses 6065 # DTB misses +system.cpu1.itb.accesses 43726876 # DTB accesses +system.cpu1.numCycles 106544770 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8029847 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 21178907 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3975194 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2282212 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 22801485 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 668344 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 75754 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 30605 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 165807 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 282475 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 16137 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7143243 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 97050 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 1864 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 31736282 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.814476 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.191251 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 10285169 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 109329590 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 34009026 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 27552465 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 93003678 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3760962 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 80448 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 30144 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 178688 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 297988 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23992 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 43719656 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 111494 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2187 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 105780588 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.280193 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.339076 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 19759016 62.26% 62.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 4355316 13.72% 75.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1372720 4.33% 80.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 6249230 19.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 48754447 46.09% 46.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 14049982 13.28% 59.37% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7558912 7.15% 66.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 35417247 33.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 31736282 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.122129 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.650676 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 6554868 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16518365 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 7517718 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 925247 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 220084 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 615416 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 116450 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 19951417 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 870614 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 220084 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 7767251 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2357969 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11576087 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 7215568 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2599323 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 18979477 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 138008 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 212778 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 28608 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 12545 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1724298 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 18792497 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 88805063 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 21879536 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 8 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 17041996 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1750501 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 370474 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 302824 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2489623 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 3780648 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 3305194 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 561156 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 470424 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 18301855 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 511708 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 18248720 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 63617 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1549546 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 3571368 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 37688 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 31736282 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.575011 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.923740 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 105780588 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.319199 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.026138 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 13239589 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 62906745 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 26778529 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1104926 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1750799 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 750846 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 132411 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 68206477 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1115402 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1750799 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17653779 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2374666 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 57902702 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 23447751 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2650891 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 55293666 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 220143 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 265669 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 37332 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 18647 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1622767 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 55225885 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 261143833 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 58792741 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 1698 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 52650074 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2575811 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1881943 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1808403 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 13140602 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10477180 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6893389 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 629902 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 660425 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 54420167 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 587049 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 54175023 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 95968 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 3662766 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 5235414 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 44205 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 105780588 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.512145 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.849831 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 20906070 65.87% 65.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 5429676 17.11% 82.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3608533 11.37% 94.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1566039 4.93% 99.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 225959 0.71% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 5 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 72358023 68.40% 68.40% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 16614078 15.71% 84.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 13151335 12.43% 96.54% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3370344 3.19% 99.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 286797 0.27% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 11 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 31736282 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 105780588 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 1149585 28.00% 28.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 664 0.02% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 28.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1347729 32.82% 60.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1608151 39.16% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2941757 45.24% 45.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 670 0.01% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1685952 25.93% 71.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1873492 28.81% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 24 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 11270903 61.76% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 26506 0.15% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.91% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3164 0.02% 61.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.93% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.93% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 3745042 20.52% 82.45% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 3203081 17.55% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36944686 68.20% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46486 0.09% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3329 0.01% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 10429510 19.25% 87.54% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6750946 12.46% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 18248720 # Type of FU issued -system.cpu1.iq.rate 0.560652 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4106129 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.225009 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 72403468 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 20371628 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 17886914 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 22354825 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 72854 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 54175023 # Type of FU issued +system.cpu1.iq.rate 0.508472 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 6501871 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.120016 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 220722500 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58678222 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 52198206 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 5973 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2102 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 1789 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 60672989 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 3839 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 91219 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 302030 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 600 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 8546 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 208715 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 444760 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 748 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 10369 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 281379 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 35721 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 53336 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 52226 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 78419 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 220084 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 521586 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 152596 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 18819577 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 1750799 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 547306 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 107318 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 55048106 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 3780648 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 3305194 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 269579 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 5003 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 142623 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 8546 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 21067 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 96357 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 117424 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 18070032 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 3674514 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 162831 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 10477180 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6893389 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 299581 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 8072 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 92519 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 10369 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 45476 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 122774 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 168250 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 53925594 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10330118 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 227431 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 6014 # number of nop insts executed -system.cpu1.iew.exec_refs 6835502 # number of memory reference insts executed -system.cpu1.iew.exec_branches 2611240 # Number of branches executed -system.cpu1.iew.exec_stores 3160988 # Number of stores executed -system.cpu1.iew.exec_rate 0.555162 # Inst execution rate -system.cpu1.iew.wb_sent 17973633 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 17886914 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 8930641 # num instructions producing a value -system.cpu1.iew.wb_consumers 13891389 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.549537 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.642890 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1385631 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 474020 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 110400 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 31408226 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.549763 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.309086 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 40890 # number of nop insts executed +system.cpu1.iew.exec_refs 17028825 # number of memory reference insts executed +system.cpu1.iew.exec_branches 11888375 # Number of branches executed +system.cpu1.iew.exec_stores 6698707 # Number of stores executed +system.cpu1.iew.exec_rate 0.506131 # Inst execution rate +system.cpu1.iew.wb_sent 53782194 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 52199995 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 25393405 # num instructions producing a value +system.cpu1.iew.wb_consumers 38775074 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.489935 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.654890 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 3417074 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 542844 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 157272 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 103878319 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.494591 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.150147 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 23101421 73.55% 73.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 4945584 15.75% 89.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1441278 4.59% 93.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 545057 1.74% 95.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 459061 1.46% 97.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 290803 0.93% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 192288 0.61% 98.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 102090 0.33% 98.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 330644 1.05% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 77963106 75.05% 75.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 14542376 14.00% 89.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6113605 5.89% 94.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 710011 0.68% 95.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1999110 1.92% 97.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 1749013 1.68% 99.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 272868 0.26% 99.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 126868 0.12% 99.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 401362 0.39% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 31408226 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 14103243 # Number of instructions committed -system.cpu1.commit.committedOps 17267080 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 103878319 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 41730387 # Number of instructions committed +system.cpu1.commit.committedOps 51377304 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 6575097 # Number of memory references committed -system.cpu1.commit.loads 3478618 # Number of loads committed -system.cpu1.commit.membars 192402 # Number of memory barriers committed -system.cpu1.commit.branches 2497510 # Number of branches committed -system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 15405118 # Number of committed integer instructions. -system.cpu1.commit.function_calls 417187 # Number of function calls committed. +system.cpu1.commit.refs 16644430 # Number of memory references committed +system.cpu1.commit.loads 10032420 # Number of loads committed +system.cpu1.commit.membars 210881 # Number of memory barriers committed +system.cpu1.commit.branches 11730295 # Number of branches committed +system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 46164743 # Number of committed integer instructions. +system.cpu1.commit.function_calls 3380868 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 10663290 61.76% 61.76% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 25529 0.15% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3164 0.02% 61.92% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.92% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.92% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.92% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 3478618 20.15% 82.07% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 3096479 17.93% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 34684147 67.51% 67.51% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 45398 0.09% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3329 0.01% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 10032420 19.53% 87.13% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6612010 12.87% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 17267080 # Class of committed instruction -system.cpu1.commit.bw_lim_events 330644 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 48838333 # The number of ROB reads -system.cpu1.rob.rob_writes 37625273 # The number of ROB writes -system.cpu1.timesIdled 48215 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 812805 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5641687887 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 14100179 # Number of Instructions Simulated -system.cpu1.committedOps 17264016 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.308417 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.308417 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.433197 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.433197 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 20251179 # number of integer regfile reads -system.cpu1.int_regfile_writes 11682425 # number of integer regfile writes -system.cpu1.cc_regfile_reads 64899787 # number of cc regfile reads -system.cpu1.cc_regfile_writes 5579511 # number of cc regfile writes -system.cpu1.misc_regfile_reads 46382322 # number of misc regfile reads -system.cpu1.misc_regfile_writes 351060 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 151453 # number of replacements -system.cpu1.dcache.tags.tagsinuse 475.445915 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 5884950 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 151796 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 38.768808 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 94652365000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.445915 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.928605 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.928605 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 12967805 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 12967805 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3097715 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3097715 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2551654 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2551654 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42598 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 42598 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69930 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 69930 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61845 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 61845 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5649369 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5649369 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5691967 # number of overall hits -system.cpu1.dcache.overall_hits::total 5691967 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 178499 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 178499 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 318856 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 318856 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23937 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 23937 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17809 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17809 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23272 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23272 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 497355 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 497355 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 521292 # number of overall misses -system.cpu1.dcache.overall_misses::total 521292 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3304865000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3304865000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11283001947 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 11283001947 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 363785500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 363785500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 633675000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 633675000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1492000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1492000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 14587866947 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 14587866947 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 14587866947 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 14587866947 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3276214 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3276214 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2870510 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2870510 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66535 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 66535 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87739 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 87739 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85117 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 85117 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 6146724 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6146724 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 6213259 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 6213259 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.054483 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.054483 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.111080 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.111080 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.359766 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.359766 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.202977 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.202977 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.273412 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273412 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.080914 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.080914 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.083900 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.083900 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18514.753584 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 18514.753584 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35385.885625 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 35385.885625 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20427.059352 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20427.059352 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27229.073565 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27229.073565 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 51377304 # Class of committed instruction +system.cpu1.commit.bw_lim_events 401362 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 138158228 # The number of ROB reads +system.cpu1.rob.rob_writes 111482281 # The number of ROB writes +system.cpu1.timesIdled 55620 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 764182 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5544797786 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 41697532 # Number of Instructions Simulated +system.cpu1.committedOps 51344449 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.555182 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.555182 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.391362 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.391362 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 56568285 # number of integer regfile reads +system.cpu1.int_regfile_writes 35909809 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1388 # number of floating regfile reads +system.cpu1.fp_regfile_writes 516 # number of floating regfile writes +system.cpu1.cc_regfile_reads 192177585 # number of cc regfile reads +system.cpu1.cc_regfile_writes 15728126 # number of cc regfile writes +system.cpu1.misc_regfile_reads 146901400 # number of misc regfile reads +system.cpu1.misc_regfile_writes 390692 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 191412 # number of replacements +system.cpu1.dcache.tags.tagsinuse 467.958660 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 15830019 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 191751 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 82.555079 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 89229031500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 467.958660 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.913982 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.913982 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 339 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 338 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.662109 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 33166441 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 33166441 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 9618480 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9618480 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5953541 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5953541 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50151 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50151 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79497 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 79497 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71560 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71560 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 15572021 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15572021 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15622172 # number of overall hits +system.cpu1.dcache.overall_hits::total 15622172 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 219751 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 219751 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 400027 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 400027 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30362 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30362 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18466 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18466 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23631 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23631 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 619778 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 619778 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 650140 # number of overall misses +system.cpu1.dcache.overall_misses::total 650140 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3494026000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3494026000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9769416956 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 9769416956 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 360558000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 360558000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 577732000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 577732000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 853500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 853500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13263442956 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13263442956 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13263442956 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13263442956 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9838231 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9838231 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6353568 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6353568 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80513 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80513 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97963 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97963 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95191 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95191 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16191799 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16191799 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16272312 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16272312 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022336 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.022336 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062961 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.062961 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377107 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377107 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.188500 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.188500 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248248 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248248 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038277 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.038277 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039954 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.039954 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15899.932196 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15899.932196 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24421.893912 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24421.893912 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19525.506336 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19525.506336 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24448.055520 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24448.055520 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29330.894325 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 29330.894325 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27984.060655 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 27984.060655 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 243 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1664555 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 21 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 30437 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.571429 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 54.688537 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 151454 # number of writebacks -system.cpu1.dcache.writebacks::total 151454 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 61419 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 61419 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 240138 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 240138 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12559 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12559 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 301557 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 301557 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 301557 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 301557 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117080 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 117080 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78718 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 78718 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23077 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 23077 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5250 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5250 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23272 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23272 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 195798 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 195798 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 218875 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 218875 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3052 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3052 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2407 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2407 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5459 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5459 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1724704000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1724704000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2823186957 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2823186957 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 411595000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 411595000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 99724500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 99724500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 610417000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 610417000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1478000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1478000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4547890957 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4547890957 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4959485957 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4959485957 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 433858500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 433858500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 433858500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 433858500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035736 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035736 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027423 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027423 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.346840 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.346840 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059837 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.059837 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.273412 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.273412 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031854 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031854 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035227 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035227 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14730.987359 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14730.987359 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35864.566643 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35864.566643 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17835.723881 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17835.723881 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18995.142857 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18995.142857 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26229.675146 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26229.675146 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21400.312622 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 21400.312622 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20400.902815 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20400.902815 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 349 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1422803 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 40164 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.633333 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 35.424833 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 191413 # number of writebacks +system.cpu1.dcache.writebacks::total 191413 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 80045 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 80045 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 309351 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 309351 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13126 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13126 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 389396 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 389396 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 389396 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 389396 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139706 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 139706 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90676 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 90676 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28955 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 28955 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5340 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5340 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23631 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23631 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 230382 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 230382 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 259337 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 259337 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14528 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14528 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11864 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11864 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26392 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26392 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1929657000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1929657000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2407624467 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2407624467 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 488405000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 488405000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91592000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91592000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 554116000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 554116000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 838500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 838500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4337281467 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4337281467 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4825686467 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4825686467 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2529035000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2529035000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2529035000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2529035000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014200 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014272 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014272 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359631 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359631 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054510 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054510 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248248 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248248 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014228 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.014228 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015937 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.015937 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13812.270053 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13812.270053 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26551.948333 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26551.948333 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16867.725781 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16867.725781 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17152.059925 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17152.059925 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23448.690280 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23448.690280 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23227.463799 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23227.463799 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22658.987810 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22658.987810 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142155.471822 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142155.471822 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79475.819747 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79475.819747 # average overall mshr uncacheable latency -system.cpu1.icache.tags.replacements 550819 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.430777 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6572284 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 551331 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.920759 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 79423447000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.430777 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975451 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975451 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18826.477186 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18826.477186 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18607.782411 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18607.782411 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174080.052313 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174080.052313 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95825.818430 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95825.818430 # average overall mshr uncacheable latency +system.cpu1.icache.tags.replacements 601488 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.448304 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 43094812 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 602000 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 71.586066 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 79058224000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448304 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975485 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975485 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 493 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 14837444 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 14837444 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 6572284 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6572284 # 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number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 43719398 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 43719398 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 43719398 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 43719398 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014286 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014286 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014286 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014286 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014286 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014286 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8997.088941 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8997.088941 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8997.088941 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8997.088941 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8997.088941 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8997.088941 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 497106 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 2 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 41763 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.058886 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 114 # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 550819 # number of writebacks -system.cpu1.icache.writebacks::total 550819 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19437 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 19437 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 19437 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 19437 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 19437 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 19437 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 551334 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 551334 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 551334 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 551334 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 551334 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 551334 # number of overall MSHR misses +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.903024 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 2 # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 601488 # number of writebacks +system.cpu1.icache.writebacks::total 601488 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22580 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 22580 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 22580 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 22580 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 22580 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 22580 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 602006 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 602006 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 602006 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 602006 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 602006 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 602006 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4760291519 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4760291519 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4760291519 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4760291519 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4760291519 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4760291519 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13829000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13829000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13829000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 13829000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.077185 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.077185 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.077185 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.077185 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.077185 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.077185 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8634.133790 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8634.133790 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8634.133790 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8634.133790 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8634.133790 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8634.133790 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135578.431373 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135578.431373 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135578.431373 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135578.431373 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.num_hwpf_issued 116080 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 116662 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 527 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5157000587 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5157000587 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5157000587 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5157000587 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5157000587 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5157000587 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9463000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9463000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9463000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9463000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013770 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013770 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013770 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013770 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013770 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013770 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8566.360779 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8566.360779 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8566.360779 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8566.360779 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8566.360779 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8566.360779 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92774.509804 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92774.509804 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92774.509804 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92774.509804 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.num_hwpf_issued 196563 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 197115 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 493 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 50226 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 32901 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15108.183095 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1229209 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 48015 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 25.600521 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 59469 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 47848 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15152.810983 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1369588 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 62482 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 21.919721 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14647.178223 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.951767 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.912776 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 448.140330 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.893993 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000607 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000178 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027352 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.922130 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 986 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14072 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 621 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 357 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14657.752176 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.247040 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.961226 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 482.850541 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.894638 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000564 # 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number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2600653999 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3176484999 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7348000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3846500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 564636500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2600653999 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1151290913 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4327775912 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13064000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 409389000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 422453000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13064000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 409389000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 422453000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.035274 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.045106 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.038393 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackClean accesses -system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackClean accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26392 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26494 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6919000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3801000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10720000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1003077137 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1003077137 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 504358500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 504358500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 376609000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 376609000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 725499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 725499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1128947000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1128947000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 579803500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 579803500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1128190999 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1128190999 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6919000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3801000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 579803500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2257137999 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2847661499 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6919000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3801000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 579803500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2257137999 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1003077137 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3850738636 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8698000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2412762500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2421460500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8698000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2412762500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2421460500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024551 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.037841 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028165 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999957 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999957 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.631148 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.631148 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018847 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018847 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.443346 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.443346 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.035274 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.045106 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018847 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.491517 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140086 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.035274 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.045106 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018847 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.491517 # mshr miss rate for overall accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548437 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548437 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027397 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027397 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.395683 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.395683 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024551 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.037841 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027397 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.435584 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.138947 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024551 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.037841 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027397 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.435584 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.165930 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16475.336323 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14515.094340 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15744.725738 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58201.855973 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58201.855973 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20558.694610 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20558.694610 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18719.049461 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18719.049461 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47844.720301 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47844.720301 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54338.995284 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54338.995284 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16845.911593 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16845.911593 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16475.336323 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14515.094340 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54338.995284 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27055.762458 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29624.757508 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16475.336323 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14515.094340 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54338.995284 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27055.762458 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58201.855973 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34075.634125 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 128078.431373 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134137.942333 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133941.978440 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 128078.431373 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 74993.405386 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75967.092250 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1509011 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 762131 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11245 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 172130 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 169820 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2310 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 24888 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 759622 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2407 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2407 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 121244 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 608400 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 89967 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 23852 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 71187 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41516 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85044 # Transaction distribution +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168407 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15869.266055 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15143.426295 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15604.075691 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39505.223780 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39505.223780 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16903.793947 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16903.793947 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15939.097681 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15939.097681 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 241833 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 241833 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33464.162912 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33464.162912 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35154.520099 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35154.520099 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16388.358667 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16388.358667 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15869.266055 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15143.426295 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35154.520099 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22004.328446 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23778.664287 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15869.266055 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15143.426295 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35154.520099 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22004.328446 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39505.223780 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26529.739549 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85274.509804 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166076.713932 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165513.362953 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85274.509804 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91420.222037 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91396.561486 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1693819 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 856333 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12567 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 183235 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 181854 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1381 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 43509 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 857970 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11864 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11864 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 150213 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 676407 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 108999 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 30864 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 72606 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41945 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86317 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 57431 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 54716 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 551334 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 224940 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 24 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1653690 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 733597 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12997 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 27256 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2427540 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 70539360 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24952640 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 23500 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50576 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 95566076 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 366639 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1114936 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.173156 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.383819 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 28 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 68814 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66024 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 602006 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 255355 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 206 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1805701 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 897982 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14680 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38591 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2756954 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 77025056 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30176714 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 26532 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 71036 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 107299338 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 403916 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1269906 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.163115 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.372403 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 924188 82.89% 82.89% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 188438 16.90% 99.79% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 2310 0.21% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1064146 83.80% 83.80% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 204379 16.09% 99.89% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1381 0.11% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1114936 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1467946497 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1269906 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1668457495 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80180559 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80964876 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 827154896 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 903243234 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 324971252 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 401728937 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 7123996 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 8056980 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 14622978 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 20851461 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31018 # Transaction distribution -system.iobus.trans_dist::ReadResp 31018 # Transaction distribution -system.iobus.trans_dist::WriteReq 59424 # Transaction distribution -system.iobus.trans_dist::WriteResp 59424 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31007 # Transaction distribution +system.iobus.trans_dist::ReadResp 31007 # Transaction distribution +system.iobus.trans_dist::WriteReq 59421 # Transaction distribution +system.iobus.trans_dist::WriteResp 59421 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2806,11 +2819,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180884 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180856 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2829,37 +2842,37 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40401000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484002 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40388000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 330000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 89000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 585000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 574500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) @@ -2867,54 +2880,54 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6085000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6116000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 34109000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33795000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187090970 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187654365 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36766000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.555535 # Cycle average of tags in use +system.iocache.tags.replacements 36453 # number of replacements +system.iocache.tags.tagsinuse 14.555427 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 256148567000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.555535 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.909721 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.909721 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 255133996000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.555427 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909714 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909714 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328284 # Number of tag accesses -system.iocache.tags.data_accesses 328284 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses -system.iocache.ReadReq_misses::total 252 # number of ReadReq misses +system.iocache.tags.tag_accesses 328239 # Number of tag accesses +system.iocache.tags.data_accesses 328239 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses +system.iocache.ReadReq_misses::total 247 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses -system.iocache.demand_misses::total 36476 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36476 # number of overall misses -system.iocache.overall_misses::total 36476 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32635877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32635877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4576397093 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4576397093 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4609032970 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4609032970 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4609032970 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4609032970 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36471 # number of demand (read+write) misses +system.iocache.demand_misses::total 36471 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36471 # number of overall misses +system.iocache.overall_misses::total 36471 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 32034877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32034877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4302643488 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4302643488 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4334678365 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4334678365 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4334678365 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4334678365 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36471 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36471 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36471 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36471 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2923,38 +2936,38 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129507.448413 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129507.448413 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126336.050491 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126336.050491 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 126357.960577 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126357.960577 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 126357.960577 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126357.960577 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129695.858300 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129695.858300 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118778.806537 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118778.806537 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118852.742316 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118852.742316 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118852.742316 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118852.742316 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 247 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 247 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36476 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20035877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20035877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2763475432 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2763475432 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2783511309 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2783511309 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2783511309 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2783511309 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36471 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36471 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36471 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36471 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19684877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19684877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2489128459 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2489128459 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2508813336 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2508813336 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2508813336 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2508813336 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2963,590 +2976,599 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79507.448413 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79507.448413 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76288.522306 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76288.522306 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76310.760747 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76310.760747 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76310.760747 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76310.760747 # average overall mshr miss latency -system.l2c.tags.replacements 125494 # number of replacements -system.l2c.tags.tagsinuse 63202.959531 # Cycle average of tags in use -system.l2c.tags.total_refs 439435 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 189556 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.318233 # Average number of references to valid blocks. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79695.858300 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 79695.858300 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68714.897830 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68714.897830 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68789.266431 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68789.266431 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68789.266431 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68789.266431 # average overall mshr miss latency +system.l2c.tags.replacements 126939 # number of replacements +system.l2c.tags.tagsinuse 63214.740893 # Cycle average of tags in use +system.l2c.tags.total_refs 439035 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 190800 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.301022 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13071.247488 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.199813 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.970724 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8317.166173 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2997.468102 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34883.534763 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.576740 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910038 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1686.284360 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 475.918503 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1747.682827 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.199451 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000232 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000030 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.126910 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.045738 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.532280 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000085 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 13659.794415 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.383881 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.061858 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8032.623601 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2877.626716 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34705.867730 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 3.664427 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910014 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1967.326736 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 460.362743 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1490.118772 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.208432 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000235 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.122568 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043909 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.529570 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000056 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025731 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.007262 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.026668 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.964401 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 30884 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 33156 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 128 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5810 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 24946 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 618 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4320 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 28181 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.471252 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.505920 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6014054 # Number of tag accesses -system.l2c.tags.data_accesses 6014054 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 259619 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 259619 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32746 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1957 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34703 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2097 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 869 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2966 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3978 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1360 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5338 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 199 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 64 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 36469 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 49080 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47369 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 28 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 11 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 7634 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 4971 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3115 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 148940 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 199 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 64 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 36469 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 53058 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 47369 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 28 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7634 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 6331 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 3115 # 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number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12596 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 841 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1321 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2162 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11292 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8274 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19566 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 27 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 4 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 19487 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 9131 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 132775 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 8 # number of ReadSharedReq misses +system.l2c.tags.occ_percent::cpu1.inst 0.030019 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.007025 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022737 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.964580 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 29285 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 34558 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 182 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5757 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 23342 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 17 # 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average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25783.562108 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24851.168048 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25201.035311 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92918.746087 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74219.366018 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 85024.418656 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 84520 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73068.269096 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 81014.079174 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98383.948531 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 94500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75532.434961 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83450.785340 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122531.929211 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 95051.515994 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84520 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73068.269096 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87591.441469 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98383.948531 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 94500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75532.434961 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75185.609491 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122531.929211 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 94027.835356 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84520 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73068.269096 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87591.441469 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98383.948531 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 94500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75532.434961 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75185.609491 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122531.929211 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 94027.835356 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196927.630334 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67264.705882 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148107.160138 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167400.368765 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101732.354685 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67264.705882 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81520.955739 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92296.629765 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 514606 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 294659 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 567 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 37970 # Transaction distribution +system.membus.trans_dist::ReadResp 208402 # Transaction distribution +system.membus.trans_dist::WriteReq 30897 # Transaction distribution +system.membus.trans_dist::WriteResp 30897 # Transaction distribution +system.membus.trans_dist::WritebackDirty 135820 # Transaction distribution +system.membus.trans_dist::CleanEvict 15995 # Transaction distribution +system.membus.trans_dist::UpgradeReq 76425 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40810 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 39381 # Transaction distribution -system.membus.trans_dist::ReadExResp 19462 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 171233 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 38865 # Transaction distribution +system.membus.trans_dist::ReadExResp 19252 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 170433 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 645275 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 766897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839846 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13670 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 646867 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 768487 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 841426 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18543624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18734032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27340 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18547336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18737758 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21052176 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 120651 # Total snoops (count) -system.membus.snoop_fanout::samples 580873 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size::total 21055902 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 122883 # Total snoops (count) +system.membus.snoop_fanout::samples 431628 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011899 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.108432 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 580873 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 426492 98.81% 98.81% # Request fanout histogram +system.membus.snoop_fanout::1 5136 1.19% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 580873 # Request fanout histogram -system.membus.reqLayer0.occupancy 81906000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 431628 # Request fanout histogram +system.membus.reqLayer0.occupancy 81611500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11549500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11561000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 984548482 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 995379161 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1099659305 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1093943847 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1332381 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1316877 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3589,57 +3611,56 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 989892 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 534223 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 146584 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 20158 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 19282 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 876 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 37979 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 475706 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30892 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30892 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 394392 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 117024 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 109072 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43515 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 152587 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50322 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50322 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 437743 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1265601 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 259494 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1525095 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35019900 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3939924 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 38959824 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 441873 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 907771 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.341587 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.476273 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 1005681 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 545297 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 156423 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20020 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 19070 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 950 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 37973 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 482978 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30897 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30897 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 361408 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 120637 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 111235 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43898 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 155133 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 28 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50623 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50623 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 445008 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4567 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1196695 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 348487 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1545182 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34087104 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5287070 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39374174 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 380983 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 851193 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.382254 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.488230 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 598564 65.94% 65.94% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 308331 33.97% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 876 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 526771 61.89% 61.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 323472 38.00% 99.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 950 0.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 907771 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 872211768 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 851193 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 876200249 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 348123 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 658378956 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 630764010 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 205665017 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 246030993 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1873 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 1a957c7d0..6a568c6cc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.832863 # Nu sim_ticks 2832862976500 # Number of ticks simulated final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118929 # Simulator instruction rate (inst/s) -host_op_rate 144250 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2978848657 # Simulator tick rate (ticks/s) -host_mem_usage 586012 # Number of bytes of host memory used -host_seconds 950.99 # Real time elapsed on the host +host_inst_rate 116306 # Simulator instruction rate (inst/s) +host_op_rate 141069 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2913147103 # Simulator tick rate (ticks/s) +host_mem_usage 578076 # Number of bytes of host memory used +host_seconds 972.44 # Real time elapsed on the host sim_insts 113100501 # Number of instructions simulated sim_ops 137180951 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 53535ebf9..16738d5e3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,164 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.824845 # Number of seconds simulated -sim_ticks 2824844935500 # Number of ticks simulated -final_tick 2824844935500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.823729 # Number of seconds simulated +sim_ticks 2823728611500 # Number of ticks simulated +final_tick 2823728611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 301818 # Simulator instruction rate (inst/s) -host_op_rate 366127 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6933711439 # Simulator tick rate (ticks/s) -host_mem_usage 588164 # Number of bytes of host memory used -host_seconds 407.41 # Real time elapsed on the host -sim_insts 122962678 # Number of instructions simulated -sim_ops 149162687 # Number of ops (including micro ops) simulated +host_inst_rate 263665 # Simulator instruction rate (inst/s) +host_op_rate 319829 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6058824639 # Simulator tick rate (ticks/s) +host_mem_usage 584988 # Number of bytes of host memory used +host_seconds 466.05 # Real time elapsed on the host +sim_insts 122881667 # Number of instructions simulated +sim_ops 149056790 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 540004 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4201700 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 538276 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3140708 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 117312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 902784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 307648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1658880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 4224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 418176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 2992192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 122816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 897088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 339840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2003776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 4480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 386816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 3512832 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11145864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 540004 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 117312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 307648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 418176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1383140 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8393280 # Number of bytes written to this memory +system.physmem.bytes_read::total 10950024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 538276 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 122816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 339840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 386816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1387748 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8235776 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8410804 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16891 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 66171 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8253300 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16864 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 49593 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1833 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 14106 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 26 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4807 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 25920 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 66 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 6534 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 46753 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1919 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 28 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5310 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 31309 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 70 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 6044 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 54888 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 183127 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131145 # Number of write requests responded to by this memory +system.physmem.num_reads::total 180067 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 128684 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135526 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 68 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 191162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1487409 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 133065 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 190626 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1112256 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 41529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 319587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 589 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 108908 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 587246 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 148035 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 1059241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 317696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 120352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 709621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 136988 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 1244040 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3945655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 191162 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 41529 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 108908 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 148035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 489634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2971236 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6204 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2977439 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2971236 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 68 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 191162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1493613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3877860 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 190626 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43494 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 120352 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 136988 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 491459 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2916632 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6206 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2922838 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2916632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 190626 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1118462 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 41529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 319587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 589 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 108908 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 587246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 148035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 1059241 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 317696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 120352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 709621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 136988 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 1244040 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6923094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 100046 # Number of read requests accepted -system.physmem.writeReqs 68732 # Number of write requests accepted -system.physmem.readBursts 100046 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 68732 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6396992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue -system.physmem.bytesWritten 4397632 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6402944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4398848 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6800697 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 113588 # Number of read requests accepted +system.physmem.writeReqs 68931 # Number of write requests accepted +system.physmem.readBursts 113588 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 68931 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 7262464 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue +system.physmem.bytesWritten 4410816 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 7269632 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4411584 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6841 # Per bank write bursts -system.physmem.perBankRdBursts::1 6294 # Per bank write bursts -system.physmem.perBankRdBursts::2 6670 # Per bank write bursts -system.physmem.perBankRdBursts::3 6264 # Per bank write bursts -system.physmem.perBankRdBursts::4 6125 # Per bank write bursts -system.physmem.perBankRdBursts::5 5943 # Per bank write bursts -system.physmem.perBankRdBursts::6 6707 # Per bank write bursts -system.physmem.perBankRdBursts::7 6704 # Per bank write bursts -system.physmem.perBankRdBursts::8 6491 # Per bank write bursts -system.physmem.perBankRdBursts::9 6555 # Per bank write bursts -system.physmem.perBankRdBursts::10 6154 # Per bank write bursts -system.physmem.perBankRdBursts::11 5521 # Per bank write bursts -system.physmem.perBankRdBursts::12 5628 # Per bank write bursts -system.physmem.perBankRdBursts::13 6555 # Per bank write bursts -system.physmem.perBankRdBursts::14 6152 # Per bank write bursts -system.physmem.perBankRdBursts::15 5349 # Per bank write bursts -system.physmem.perBankWrBursts::0 4568 # Per bank write bursts -system.physmem.perBankWrBursts::1 4266 # Per bank write bursts -system.physmem.perBankWrBursts::2 4764 # Per bank write bursts -system.physmem.perBankWrBursts::3 4205 # Per bank write bursts -system.physmem.perBankWrBursts::4 4158 # Per bank write bursts -system.physmem.perBankWrBursts::5 4117 # Per bank write bursts -system.physmem.perBankWrBursts::6 4748 # Per bank write bursts -system.physmem.perBankWrBursts::7 4286 # Per bank write bursts -system.physmem.perBankWrBursts::8 4452 # Per bank write bursts -system.physmem.perBankWrBursts::9 4767 # Per bank write bursts -system.physmem.perBankWrBursts::10 4196 # Per bank write bursts -system.physmem.perBankWrBursts::11 3943 # Per bank write bursts -system.physmem.perBankWrBursts::12 3845 # Per bank write bursts -system.physmem.perBankWrBursts::13 4709 # Per bank write bursts -system.physmem.perBankWrBursts::14 4129 # Per bank write bursts -system.physmem.perBankWrBursts::15 3560 # Per bank write bursts +system.physmem.perBankRdBursts::0 7537 # Per bank write bursts +system.physmem.perBankRdBursts::1 6789 # Per bank write bursts +system.physmem.perBankRdBursts::2 7399 # Per bank write bursts +system.physmem.perBankRdBursts::3 7485 # Per bank write bursts +system.physmem.perBankRdBursts::4 7337 # Per bank write bursts +system.physmem.perBankRdBursts::5 7010 # Per bank write bursts +system.physmem.perBankRdBursts::6 7617 # Per bank write bursts +system.physmem.perBankRdBursts::7 7715 # Per bank write bursts +system.physmem.perBankRdBursts::8 6869 # Per bank write bursts +system.physmem.perBankRdBursts::9 7528 # Per bank write bursts +system.physmem.perBankRdBursts::10 7086 # Per bank write bursts +system.physmem.perBankRdBursts::11 6373 # Per bank write bursts +system.physmem.perBankRdBursts::12 6401 # Per bank write bursts +system.physmem.perBankRdBursts::13 7208 # Per bank write bursts +system.physmem.perBankRdBursts::14 6839 # Per bank write bursts +system.physmem.perBankRdBursts::15 6283 # Per bank write bursts +system.physmem.perBankWrBursts::0 4402 # Per bank write bursts +system.physmem.perBankWrBursts::1 3960 # Per bank write bursts +system.physmem.perBankWrBursts::2 4483 # Per bank write bursts +system.physmem.perBankWrBursts::3 4623 # Per bank write bursts +system.physmem.perBankWrBursts::4 4313 # Per bank write bursts +system.physmem.perBankWrBursts::5 4310 # Per bank write bursts +system.physmem.perBankWrBursts::6 4616 # Per bank write bursts +system.physmem.perBankWrBursts::7 4482 # Per bank write bursts +system.physmem.perBankWrBursts::8 4162 # Per bank write bursts +system.physmem.perBankWrBursts::9 4849 # Per bank write bursts +system.physmem.perBankWrBursts::10 4455 # Per bank write bursts +system.physmem.perBankWrBursts::11 3923 # Per bank write bursts +system.physmem.perBankWrBursts::12 3821 # Per bank write bursts +system.physmem.perBankWrBursts::13 4641 # Per bank write bursts +system.physmem.perBankWrBursts::14 4142 # Per bank write bursts +system.physmem.perBankWrBursts::15 3737 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 2823278667500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2822156484500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 100046 # Read request sizes (log2) +system.physmem.readPktSize::6 113588 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 68732 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 76462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 20947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 68931 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 85837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 24551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,170 +194,173 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 65 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3963 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39183 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 275.487635 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.171837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.896605 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16209 41.37% 41.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9498 24.24% 65.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3856 9.84% 75.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2020 5.16% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1646 4.20% 84.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1041 2.66% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 570 1.45% 88.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 566 1.44% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3777 9.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39183 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3537 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.251343 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 474.824507 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 3535 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3537 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3537 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.426915 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.022626 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.137247 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 7 0.20% 0.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 2 0.06% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 2 0.06% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 5 0.14% 0.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3142 88.83% 89.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 84 2.37% 91.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 38 1.07% 92.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 37 1.05% 93.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 22 0.62% 94.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 9 0.25% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 25 0.71% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.17% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 52 1.47% 97.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.23% 97.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.14% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 10 0.28% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 31 0.88% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.03% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.03% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 15 0.42% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 29 0.82% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 1 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 3 0.08% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3537 # Writes before turning the bus around for reads -system.physmem.totQLat 1310437500 # Total ticks spent queuing -system.physmem.totMemAccLat 3184556250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 499765000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13110.54 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::5 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 60 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39396 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.306224 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.340600 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.184189 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15747 39.97% 39.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9259 23.50% 63.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3829 9.72% 73.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2133 5.41% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1523 3.87% 82.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 982 2.49% 84.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 643 1.63% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 644 1.63% 88.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4636 11.77% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39396 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3632 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 31.238987 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 631.062126 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 3630 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-38911 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3632 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3632 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.975496 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.811099 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.084616 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 8 0.22% 0.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 2 0.06% 0.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 2 0.06% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 6 0.17% 0.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3236 89.10% 89.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 53 1.46% 91.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 53 1.46% 92.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 39 1.07% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 77 2.12% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 40 1.10% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 9 0.25% 97.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.28% 97.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 6 0.17% 97.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.17% 97.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.08% 97.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.08% 97.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 57 1.57% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.06% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.11% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.08% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.03% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.03% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.06% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.14% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3632 # Writes before turning the bus around for reads +system.physmem.totQLat 1343217000 # Total ticks spent queuing +system.physmem.totMemAccLat 3470892000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 567380000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11837.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31860.54 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30587.01 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.57 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.57 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 28.41 # Average write queue length when enqueuing -system.physmem.readRowHits 80619 # Number of row buffer hits during reads -system.physmem.writeRowHits 48863 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.09 # Row buffer hit rate for writes -system.physmem.avgGap 16727764.68 # Average gap between requests -system.physmem.pageHitRate 76.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 156219840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 85098750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 402051000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 227525760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 179782062720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 73199813535 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1622867858250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1876720629855 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.445270 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2640465319000 # Time in different power states -system.physmem_0.memoryStateTime::REF 91913120000 # Time in different power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.43 # Average write queue length when enqueuing +system.physmem.readRowHits 93570 # Number of row buffer hits during reads +system.physmem.writeRowHits 49429 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.46 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.71 # Row buffer hit rate for writes +system.physmem.avgGap 15462261.38 # Average gap between requests +system.physmem.pageHitRate 78.40 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 157845240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 85919625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 459334200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 228024720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 179708830080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 71920019610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1621544120250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1874104093725 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.482603 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2641247036500 # Time in different power states +system.physmem_0.memoryStateTime::REF 91875680000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 20214084000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 18345228000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 140003640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76213500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 377559000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 217734480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 179782062720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72425693970 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1619952048750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1872971316060 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.534243 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2641598541500 # Time in different power states -system.physmem_1.memoryStateTime::REF 91913120000 # Time in different power states +system.physmem_1.actEnergy 139988520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76201125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 425778600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 218570400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 179708830080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 71085149730 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1620445707000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1872100225455 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.494295 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2642466728000 # Time in different power states +system.physmem_1.memoryStateTime::REF 91875680000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 19069290500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17119309500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -399,47 +410,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 4956 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 4956 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 4956 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 4956 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 4956 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 57378111376 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.254714 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -14615003624 -25.47% -25.47% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 71993115000 125.47% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 57378111376 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 2714 66.86% 66.86% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1345 33.14% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4059 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4956 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 4971 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 4971 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 4971 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 4971 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 4971 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 56876140626 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.265788 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -15117011624 -26.58% -26.58% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 71993152250 126.58% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 56876140626 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 2795 68.19% 68.19% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1304 31.81% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4099 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4971 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4956 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4059 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4971 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4099 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4059 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9015 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4099 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9070 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12035291 # DTB read hits -system.cpu0.dtb.read_misses 4159 # DTB read misses -system.cpu0.dtb.write_hits 9387286 # DTB write hits -system.cpu0.dtb.write_misses 797 # DTB write misses -system.cpu0.dtb.flush_tlb 170 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 344 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 12098970 # DTB read hits +system.cpu0.dtb.read_misses 4249 # DTB read misses +system.cpu0.dtb.write_hits 9143698 # DTB write hits +system.cpu0.dtb.write_misses 722 # DTB write misses +system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2853 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2823 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 725 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 830 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 165 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12039450 # DTB read accesses -system.cpu0.dtb.write_accesses 9388083 # DTB write accesses +system.cpu0.dtb.perms_faults 174 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12103219 # DTB read accesses +system.cpu0.dtb.write_accesses 9144420 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21422577 # DTB hits -system.cpu0.dtb.misses 4956 # DTB misses -system.cpu0.dtb.accesses 21427533 # DTB accesses +system.cpu0.dtb.hits 21242668 # DTB hits +system.cpu0.dtb.misses 4971 # DTB misses +system.cpu0.dtb.accesses 21247639 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -469,639 +480,639 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2296 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2296 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2296 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2296 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2296 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 57378111376 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.254717 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -14615152624 -25.47% -25.47% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 71993264000 125.47% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 57378111376 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1260 74.03% 74.03% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 442 25.97% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1702 # Table walker page sizes translated +system.cpu0.itb.walker.walks 2431 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2431 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2431 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2431 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2431 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 56876140626 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.265790 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -15117125624 -26.58% -26.58% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 71993266250 126.58% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 56876140626 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1312 74.72% 74.72% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 444 25.28% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1756 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2296 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2296 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2431 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2431 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1702 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1702 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 3998 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 57357196 # ITB inst hits -system.cpu0.itb.inst_misses 2296 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1756 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1756 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4187 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56920666 # ITB inst hits +system.cpu0.itb.inst_misses 2431 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 170 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 344 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 171 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1708 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1759 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 57359492 # ITB inst accesses -system.cpu0.itb.hits 57357196 # DTB hits -system.cpu0.itb.misses 2296 # DTB misses -system.cpu0.itb.accesses 57359492 # DTB accesses -system.cpu0.numCycles 69413201 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 56923097 # ITB inst accesses +system.cpu0.itb.hits 56920666 # DTB hits +system.cpu0.itb.misses 2431 # DTB misses +system.cpu0.itb.accesses 56923097 # DTB accesses +system.cpu0.numCycles 68768248 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3088 # number of quiesce instructions executed -system.cpu0.committedInsts 55950800 # Number of instructions committed -system.cpu0.committedOps 67895777 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 59559088 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4429 # Number of float alu accesses -system.cpu0.num_func_calls 5748539 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7418498 # number of instructions that are conditional controls -system.cpu0.num_int_insts 59559088 # number of integer instructions -system.cpu0.num_fp_insts 4429 # number of float instructions -system.cpu0.num_int_register_reads 109971177 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41296104 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3323 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1108 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 206667117 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 25287808 # number of times the CC registers were written -system.cpu0.num_mem_refs 21990141 # number of memory refs -system.cpu0.num_load_insts 12179891 # Number of load instructions -system.cpu0.num_store_insts 9810250 # Number of store instructions -system.cpu0.num_idle_cycles 65532353.686303 # Number of idle cycles -system.cpu0.num_busy_cycles 3880847.313697 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055909 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944091 # Percentage of idle cycles -system.cpu0.Branches 13556608 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2177 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46939668 68.04% 68.05% # Class of executed instruction -system.cpu0.op_class::IntMult 49866 0.07% 68.12% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3817 0.01% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::MemRead 12179891 17.66% 85.78% # Class of executed instruction -system.cpu0.op_class::MemWrite 9810250 14.22% 100.00% # Class of executed instruction +system.cpu0.kern.inst.quiesce 3086 # number of quiesce instructions executed +system.cpu0.committedInsts 55456471 # Number of instructions committed +system.cpu0.committedOps 67221308 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 58995481 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4380 # Number of float alu accesses +system.cpu0.num_func_calls 5787158 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7357632 # number of instructions that are conditional controls +system.cpu0.num_int_insts 58995481 # number of integer instructions +system.cpu0.num_fp_insts 4380 # number of float instructions +system.cpu0.num_int_register_reads 108779991 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41129871 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3339 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1042 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 204568240 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 24713959 # number of times the CC registers were written +system.cpu0.num_mem_refs 21830038 # number of memory refs +system.cpu0.num_load_insts 12248052 # Number of load instructions +system.cpu0.num_store_insts 9581986 # Number of store instructions +system.cpu0.num_idle_cycles 64949431.464966 # Number of idle cycles +system.cpu0.num_busy_cycles 3818816.535034 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055532 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944468 # Percentage of idle cycles +system.cpu0.Branches 13461051 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2178 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 46425629 67.96% 67.96% # Class of executed instruction +system.cpu0.op_class::IntMult 50781 0.07% 68.04% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3880 0.01% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.04% # Class of executed instruction +system.cpu0.op_class::MemRead 12248052 17.93% 85.97% # Class of executed instruction +system.cpu0.op_class::MemWrite 9581986 14.03% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # 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Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.552141 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.736312 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 13.645453 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941529 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022563 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009251 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.026651 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 193158108 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 193158108 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11428921 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 3665380 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4294725 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 6439389 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25828415 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9038925 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 2620658 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3331215 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 3935728 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18926526 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 169435 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 54580 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 74986 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 86424 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 385425 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 210127 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 74901 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 77543 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 87725 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 450296 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 211418 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 76881 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 80173 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 91598 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460070 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20467846 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 6286038 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7625940 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 10375117 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 44754941 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20637281 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 6340618 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7700926 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 10461541 # number of overall hits -system.cpu0.dcache.overall_hits::total 45140366 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 163054 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 56550 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 94465 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 206057 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 520126 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 128070 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 30037 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 97212 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 1098174 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1353493 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 50296 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 17954 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 32256 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 38131 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 138637 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3902 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2617 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3585 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 7920 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18024 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 193086181 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 193086181 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11466813 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 3604015 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4048059 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 6693194 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25812081 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 8805126 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 2681872 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 3150720 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 4155645 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18793363 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178315 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 56771 # 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number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 83860 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu3.data 219596 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 526130 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 112315 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 34838 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 103940 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu3.data 1226727 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1477820 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 53930 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 19459 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 19330 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu3.data 42725 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 135444 # 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number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1873619 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 341420 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 104541 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 223933 # number of overall misses -system.cpu0.dcache.overall_misses::cpu3.data 1342362 # number of overall misses -system.cpu0.dcache.overall_misses::total 2012256 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 1025638000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1410367000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3709040500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6145045500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1809360000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 6517744997 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 77518 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 81128 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 95645 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 468320 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 211420 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 76881 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 80173 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 91623 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460097 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 20758970 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15556511938 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2981158500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 4997852500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 8612883938 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16591894938 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 629109500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1118645000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1808848000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3556602500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 629109500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1118645000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1808848000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3556602500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015174 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018086 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016790 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009391 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011332 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015450 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017506 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008438 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.243899 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.209461 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.225402 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.130193 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.013171 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.015432 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.025271 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010015 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000273 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000054 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013576 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.016930 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.017099 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.008977 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016168 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019535 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019297 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.010324 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17131.119965 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14546.692533 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15575.082678 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15600.312004 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59237.706828 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 66654.464791 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72470.580857 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68347.707840 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13247.159573 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13908.850109 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17403.134461 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15175.116153 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16223.800196 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 16790.734824 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16001.034340 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16260.341151 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 34320 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 34320 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 31750.543277 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35401.455221 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40682.070976 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37166.298993 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28609.142731 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32282.949216 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37812.790308 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34084.016931 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177764.764058 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 199615.453248 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215262.168273 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202701.612903 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 97946.364627 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 112426.633166 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 120317.147798 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 113242.350431 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 1977299 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.446081 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 94017501 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1977811 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 47.536140 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12783647500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 433.555541 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 10.959616 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 24.981248 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 41.949675 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.846788 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.021406 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.048791 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.081933 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998918 # Average percentage of cache occupancy +system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000291 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000063 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013772 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013610 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.025424 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu3.data 0.117634 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.042995 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.016213 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.016467 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.027716 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu3.data 0.119854 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.045390 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16108.218518 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14429.537324 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15254.658555 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10255.752381 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36542.984672 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48554.844102 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 49825.128421 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45635.940309 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12251.710864 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14540.784314 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13724.962816 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10877.831083 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 22777.777778 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21206.896552 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24316.240647 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 33316.568136 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44576.275363 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36346.996835 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19860.446173 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30207.364921 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43297.255906 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34045.886035 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 335985 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 31302 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 12606 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 672 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.652784 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 46.580357 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 692418 # number of writebacks +system.cpu0.dcache.writebacks::total 692418 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 104 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 8524 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 107233 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 115861 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 47971 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1130213 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1178184 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1643 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2350 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5425 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9418 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 104 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 56495 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu3.data 1237446 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1294045 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 104 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 56495 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu3.data 1237446 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1294045 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 51791 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 75336 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 112363 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 239490 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 34838 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 55969 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 96514 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 187321 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 19125 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 15868 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 29717 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 64710 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 695 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1475 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 2643 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4813 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 27 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 27 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 86629 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 131305 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu3.data 208877 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 426811 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 105754 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 147173 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu3.data 238594 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 491521 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 3424 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 7115 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 7790 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18329 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 2828 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5194 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6258 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14280 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 6252 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 12309 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 14048 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32609 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 782633000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1020579500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1612658500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3415871000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238246500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2646664500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 4858846947 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8743757947 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 247386000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 228071000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 457589000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 933046000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8958000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 27255500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 37981000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 74194500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 588000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 588000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2020879500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3667244000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 6471505447 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12159628947 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2268265500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3895315000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 6929094447 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13092674947 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 601507000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1484874500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1676185500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3762567000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 601507000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1484874500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1676185500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3762567000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014166 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018233 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016254 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009093 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012824 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017197 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017931 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009241 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.250885 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.182838 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.230869 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.123497 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.008985 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019791 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.027362 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010264 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000291 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000059 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013594 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017776 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016989 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.009157 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016399 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019693 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019204 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.010428 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15111.370701 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13547.035946 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14352.220037 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14263.104931 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35542.984672 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47288.043381 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50343.441853 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46677.937588 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12935.215686 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14373.014873 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15398.223239 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14418.884253 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12889.208633 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 18478.305085 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14370.412410 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15415.437357 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 21777.777778 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21777.777778 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23327.979083 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27929.203001 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 30982.374541 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28489.492883 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21448.507858 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26467.592561 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29041.360835 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26637.061177 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175673.773364 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 208696.345748 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215171.437741 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205279.447869 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 96210.332694 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 120633.235844 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 119318.443907 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115384.311080 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 1971000 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.470268 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 93100004 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1971512 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 47.222641 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 12494493500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 436.802699 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 12.961360 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 25.140810 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu3.inst 36.565400 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.853130 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.025315 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.049103 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu3.inst 0.071417 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998965 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 260 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 98016418 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 98016418 # 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miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14114.433055 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14205.313689 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 14431.238265 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9131.948664 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14114.433055 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14205.313689 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 14431.238265 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9131.948664 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14114.433055 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14205.313689 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 14431.238265 # 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average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12853.021015 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12688.700584 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12829.404359 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12937.655406 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12853.021015 # average overall mshr miss latency system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1131,55 +1142,61 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # 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Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11568.146418 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7309.305815 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 1216 75.67% 75.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 390 24.27% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1607 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 2016 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 2016 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 564 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1452 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 2016 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 2016 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 2016 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1645 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12118.844985 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10271.833283 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6851.972198 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.91% 0.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-6143 468 28.45% 29.36% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::6144-8191 121 7.36% 36.72% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::10240-12287 510 31.00% 67.72% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-14335 106 6.44% 74.16% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::14336-16383 70 4.26% 78.42% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-18431 12 0.73% 79.15% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::22528-24575 321 19.51% 98.66% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-26623 22 1.34% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1645 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1115 69.38% 69.38% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 492 30.62% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1607 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1898 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1089 66.20% 66.20% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 556 33.80% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1645 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2016 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1898 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1607 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2016 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1645 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1607 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3505 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1645 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3661 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3875521 # DTB read hits -system.cpu1.dtb.read_misses 1673 # DTB read misses -system.cpu1.dtb.write_hits 2730525 # DTB write hits -system.cpu1.dtb.write_misses 225 # DTB write misses -system.cpu1.dtb.flush_tlb 151 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 137 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 3812918 # DTB read hits +system.cpu1.dtb.read_misses 1745 # DTB read misses +system.cpu1.dtb.write_hits 2796286 # DTB write hits +system.cpu1.dtb.write_misses 271 # DTB write misses +system.cpu1.dtb.flush_tlb 154 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 179 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1104 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1302 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 243 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 65 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3877194 # DTB read accesses -system.cpu1.dtb.write_accesses 2730750 # DTB write accesses +system.cpu1.dtb.perms_faults 87 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3814663 # DTB read accesses +system.cpu1.dtb.write_accesses 2796557 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6606046 # DTB hits -system.cpu1.dtb.misses 1898 # DTB misses -system.cpu1.dtb.accesses 6607944 # DTB accesses +system.cpu1.dtb.hits 6609204 # DTB hits +system.cpu1.dtb.misses 2016 # DTB misses +system.cpu1.dtb.accesses 6611220 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1209,134 +1226,134 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 937 # Table walker walks requested -system.cpu1.itb.walker.walksShort 937 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 756 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 937 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 937 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 937 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 679 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12754.050074 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11061.595827 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6405.303661 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 193 28.42% 28.42% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::6144-8191 2 0.29% 28.72% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 178 26.22% 54.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 59 8.69% 63.62% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 121 17.82% 81.44% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 122 17.97% 99.41% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-26623 4 0.59% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 679 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 1033 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1033 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 205 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 828 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1033 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1033 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1033 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 765 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12816.993464 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10782.034364 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7152.863364 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 258 33.73% 33.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 199 26.01% 59.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 58 7.58% 67.32% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 58 7.58% 74.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-18431 1 0.13% 75.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 183 23.92% 98.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-26623 8 1.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 765 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 498 73.34% 73.34% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 181 26.66% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 679 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 560 73.20% 73.20% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 205 26.80% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 765 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 937 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 937 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1033 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1033 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 679 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 679 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1616 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 18092471 # ITB inst hits -system.cpu1.itb.inst_misses 937 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 765 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 765 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1798 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 17860427 # ITB inst hits +system.cpu1.itb.inst_misses 1033 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 151 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 137 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 154 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 179 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 710 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 792 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 18093408 # ITB inst accesses -system.cpu1.itb.hits 18092471 # DTB hits -system.cpu1.itb.misses 937 # DTB misses -system.cpu1.itb.accesses 18093408 # DTB accesses -system.cpu1.numCycles 144009903 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 17861460 # ITB inst accesses +system.cpu1.itb.hits 17860427 # DTB hits +system.cpu1.itb.misses 1033 # DTB misses +system.cpu1.itb.accesses 17861460 # DTB accesses +system.cpu1.numCycles 143797366 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 17421457 # Number of instructions committed -system.cpu1.committedOps 20899652 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 18577744 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1420 # Number of float alu accesses -system.cpu1.num_func_calls 1993615 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2230860 # number of instructions that are conditional controls -system.cpu1.num_int_insts 18577744 # number of integer instructions -system.cpu1.num_fp_insts 1420 # number of float instructions -system.cpu1.num_int_register_reads 34369524 # number of times the integer registers were read -system.cpu1.num_int_register_writes 13035923 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1160 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 260 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 76091406 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 7577340 # number of times the CC registers were written -system.cpu1.num_mem_refs 6800165 # number of memory refs -system.cpu1.num_load_insts 3918117 # Number of load instructions -system.cpu1.num_store_insts 2882048 # Number of store instructions -system.cpu1.num_idle_cycles 136636530.804008 # Number of idle cycles -system.cpu1.num_busy_cycles 7373372.195992 # Number of busy cycles -system.cpu1.not_idle_fraction 0.051200 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.948800 # Percentage of idle cycles -system.cpu1.Branches 4337141 # Number of branches fetched -system.cpu1.op_class::No_OpClass 23 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 14685999 68.30% 68.30% # Class of executed instruction -system.cpu1.op_class::IntMult 16352 0.08% 68.37% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 955 0.00% 68.38% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.38% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.38% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.38% # Class of executed instruction -system.cpu1.op_class::MemRead 3918117 18.22% 86.60% # Class of executed instruction -system.cpu1.op_class::MemWrite 2882048 13.40% 100.00% # Class of executed instruction +system.cpu1.committedInsts 17268414 # Number of instructions committed +system.cpu1.committedOps 20827213 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 18584422 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1582 # Number of float alu accesses +system.cpu1.num_func_calls 1992181 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2177842 # number of instructions that are conditional controls +system.cpu1.num_int_insts 18584422 # number of integer instructions +system.cpu1.num_fp_insts 1582 # number of float instructions +system.cpu1.num_int_register_reads 34435383 # number of times the integer registers were read +system.cpu1.num_int_register_writes 13029372 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1129 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 454 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 75826477 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 7417953 # number of times the CC registers were written +system.cpu1.num_mem_refs 6811480 # number of memory refs +system.cpu1.num_load_insts 3856412 # Number of load instructions +system.cpu1.num_store_insts 2955068 # Number of store instructions +system.cpu1.num_idle_cycles 136802879.005961 # Number of idle cycles +system.cpu1.num_busy_cycles 6994486.994039 # Number of busy cycles +system.cpu1.not_idle_fraction 0.048641 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.951359 # Percentage of idle cycles +system.cpu1.Branches 4283216 # Number of branches fetched +system.cpu1.op_class::No_OpClass 49 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 14611363 68.15% 68.15% # Class of executed instruction +system.cpu1.op_class::IntMult 16029 0.07% 68.23% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 979 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.23% # Class of executed instruction +system.cpu1.op_class::MemRead 3856412 17.99% 86.22% # Class of executed instruction +system.cpu1.op_class::MemWrite 2955068 13.78% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21503494 # Class of executed instruction -system.cpu2.branchPred.lookups 5770264 # Number of BP lookups -system.cpu2.branchPred.condPredicted 2970192 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 504477 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3340147 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 1745677 # Number of BTB hits +system.cpu1.op_class::total 21439900 # Class of executed instruction +system.cpu2.branchPred.lookups 5566129 # Number of BP lookups +system.cpu2.branchPred.condPredicted 2825980 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 493463 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3182486 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 1660276 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 52.263478 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1611184 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 331954 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 670735 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 637081 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 33654 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 21230 # Number of mispredicted indirect branches. +system.cpu2.branchPred.BTBHitPct 52.169153 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 1582499 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 327011 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 671898 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 638941 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 32957 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 21982 # Number of mispredicted indirect branches. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1366,60 +1383,57 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 12712 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 12712 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 8004 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4708 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 12712 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 12712 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 12712 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 2182 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 12059.578368 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 10400.362655 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 6359.555797 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::2048-4095 13 0.60% 0.60% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::4096-6143 665 30.48% 31.07% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::6144-8191 1 0.05% 31.12% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::10240-12287 773 35.43% 66.54% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::12288-14335 182 8.34% 74.89% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::14336-16383 171 7.84% 82.72% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::22528-24575 366 16.77% 99.50% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::24576-26623 11 0.50% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 2182 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 2000052000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0 2000052000 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 2000052000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 1365 62.56% 62.56% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 817 37.44% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 2182 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12712 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walks 11822 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 11822 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7337 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4485 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 11822 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 11822 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 11822 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 2048 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 12710.205078 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 10939.246339 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 6922.657260 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-8191 574 28.03% 28.03% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1046 51.07% 79.10% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::16384-24575 414 20.21% 99.32% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::24576-32767 12 0.59% 99.90% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::81920-90111 2 0.10% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 2048 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 2000043000 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0 2000043000 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 2000043000 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 1270 62.01% 62.01% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 778 37.99% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 2048 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 11822 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12712 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2182 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 11822 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2048 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2182 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 14894 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2048 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 13870 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 4621518 # DTB read hits -system.cpu2.dtb.read_misses 11435 # DTB read misses -system.cpu2.dtb.write_hits 3537262 # DTB write hits -system.cpu2.dtb.write_misses 1277 # DTB write misses -system.cpu2.dtb.flush_tlb 153 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 162 # Number of times TLB was flushed by MVA +system.cpu2.dtb.read_hits 4336552 # DTB read hits +system.cpu2.dtb.read_misses 10662 # DTB read misses +system.cpu2.dtb.write_hits 3355101 # DTB write hits +system.cpu2.dtb.write_misses 1160 # DTB write misses +system.cpu2.dtb.flush_tlb 152 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 1476 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 227 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 324 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 1478 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 270 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 121 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 4632953 # DTB read accesses -system.cpu2.dtb.write_accesses 3538539 # DTB write accesses +system.cpu2.dtb.perms_faults 127 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 4347214 # DTB read accesses +system.cpu2.dtb.write_accesses 3356261 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 8158780 # DTB hits -system.cpu2.dtb.misses 12712 # DTB misses -system.cpu2.dtb.accesses 8171492 # DTB accesses +system.cpu2.dtb.hits 7691653 # DTB hits +system.cpu2.dtb.misses 11822 # DTB misses +system.cpu2.dtb.accesses 7703475 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1449,122 +1463,120 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 1416 # Table walker walks requested -system.cpu2.itb.walker.walksShort 1416 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 256 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1160 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 1416 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 1416 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 1416 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 870 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 12294.252874 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 10677.468386 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 6303.110021 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::4096-6143 282 32.41% 32.41% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::6144-8191 1 0.11% 32.53% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::10240-12287 251 28.85% 61.38% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::12288-14335 36 4.14% 65.52% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::14336-16383 152 17.47% 82.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::16384-18431 1 0.11% 83.10% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::22528-24575 145 16.67% 99.77% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::24576-26623 2 0.23% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 870 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 2000037500 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 2000037500 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 2000037500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 614 70.57% 70.57% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 256 29.43% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 870 # Table walker page sizes translated +system.cpu2.itb.walker.walks 1331 # Table walker walks requested +system.cpu2.itb.walker.walksShort 1331 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 253 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1078 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 1331 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 1331 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 1331 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 850 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 12864.705882 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 11157.048638 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 6541.427390 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::4096-6143 256 30.12% 30.12% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::10240-12287 237 27.88% 58.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::12288-14335 63 7.41% 65.41% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::14336-16383 116 13.65% 79.06% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::22528-24575 176 20.71% 99.76% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::24576-26623 2 0.24% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 850 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 2000028500 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 2000028500 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 2000028500 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 607 71.41% 71.41% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 243 28.59% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 850 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1416 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1416 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1331 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1331 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 870 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 870 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 2286 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 10823576 # ITB inst hits -system.cpu2.itb.inst_misses 1416 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 850 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 850 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 2181 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 10452986 # ITB inst hits +system.cpu2.itb.inst_misses 1331 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 153 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 162 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb 152 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 879 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 885 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1762 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1709 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 10824992 # ITB inst accesses -system.cpu2.itb.hits 10823576 # DTB hits -system.cpu2.itb.misses 1416 # DTB misses -system.cpu2.itb.accesses 10824992 # DTB accesses -system.cpu2.numCycles 1395003781 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 10454317 # ITB inst accesses +system.cpu2.itb.hits 10452986 # DTB hits +system.cpu2.itb.misses 1331 # DTB misses +system.cpu2.itb.accesses 10454317 # DTB accesses +system.cpu2.numCycles 141973763 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 20361751 # Number of instructions committed -system.cpu2.committedOps 24653563 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 1458677 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 555 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 4254696736 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 68.510993 # CPI: cycles per instruction -system.cpu2.ipc 0.014596 # IPC: instructions per cycle -system.cpu2.op_class_0::No_OpClass 53 0.00% 0.00% # Class of committed instruction -system.cpu2.op_class_0::IntAlu 16404326 66.54% 66.54% # Class of committed instruction -system.cpu2.op_class_0::IntMult 20837 0.08% 66.62% # Class of committed instruction -system.cpu2.op_class_0::IntDiv 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::FloatAdd 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::FloatCmp 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::FloatCvt 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::FloatMult 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::FloatDiv 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::FloatSqrt 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdAdd 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdAddAcc 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdAlu 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdCmp 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdCvt 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdMisc 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdMult 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdMultAcc 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdShift 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdSqrt 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 66.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMisc 1376 0.01% 66.63% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMult 0 0.00% 66.63% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 66.63% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 66.63% # Class of committed instruction -system.cpu2.op_class_0::MemRead 4532751 18.39% 85.02% # Class of committed instruction -system.cpu2.op_class_0::MemWrite 3694220 14.98% 100.00% # Class of committed instruction +system.cpu2.committedInsts 19207375 # Number of instructions committed +system.cpu2.committedOps 23288496 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 1385563 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 546 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 36865 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 7.391628 # CPI: cycles per instruction +system.cpu2.ipc 0.135288 # IPC: instructions per cycle +system.cpu2.op_class_0::No_OpClass 48 0.00% 0.00% # Class of committed instruction +system.cpu2.op_class_0::IntAlu 15543125 66.74% 66.74% # Class of committed instruction +system.cpu2.op_class_0::IntMult 18693 0.08% 66.82% # Class of committed instruction +system.cpu2.op_class_0::IntDiv 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::FloatAdd 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::FloatCmp 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::FloatCvt 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::FloatMult 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::FloatDiv 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::FloatSqrt 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdAdd 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdAddAcc 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdAlu 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdCmp 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdCvt 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdMisc 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdMult 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdMultAcc 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdShift 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdSqrt 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 66.82% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMisc 1356 0.01% 66.83% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMult 0 0.00% 66.83% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 66.83% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 66.83% # Class of committed instruction +system.cpu2.op_class_0::MemRead 4252165 18.26% 85.09% # Class of committed instruction +system.cpu2.op_class_0::MemWrite 3473109 14.91% 100.00% # Class of committed instruction system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.op_class_0::total 24653563 # Class of committed instruction +system.cpu2.op_class_0::total 23288496 # Class of committed instruction system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 42378126 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 1352625655 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 13252062 # Number of BP lookups -system.cpu3.branchPred.condPredicted 7208218 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 300007 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 8273793 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 4241536 # Number of BTB hits +system.cpu2.tickCycles 41357618 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 100616145 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 13553669 # Number of BP lookups +system.cpu3.branchPred.condPredicted 7461566 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 296736 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 8400668 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 4438644 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 51.264710 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 3096631 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 16788 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 2038250 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 1978281 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 59969 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 18256 # Number of mispredicted indirect branches. +system.cpu3.branchPred.BTBHitPct 52.836798 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 3086842 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 16263 # Number of incorrect RAS predictions. +system.cpu3.branchPred.indirectLookups 2014355 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 1952666 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 61689 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 18072 # Number of mispredicted indirect branches. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1594,84 +1606,89 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 33989 # Table walker walks requested -system.cpu3.dtb.walker.walksShort 33989 # Table walker walks initiated with short descriptors -system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11190 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 8109 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 14690 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 19299 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 517.177056 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 3689.691447 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-16383 19111 99.03% 99.03% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::16384-32767 146 0.76% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-49151 30 0.16% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::49152-65535 4 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-81919 3 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::81920-98303 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::98304-114687 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::114688-131071 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::147456-163839 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 19299 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 6381 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 13105.939508 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 10791.784480 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 9136.863267 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-32767 6254 98.01% 98.01% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::32768-65535 124 1.94% 99.95% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-98303 1 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-163839 1 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::360448-393215 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 6381 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -8047359064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.134723 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-1 -8096058564 100.61% 100.61% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::2-3 33943000 -0.42% 100.18% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-5 7702500 -0.10% 100.09% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::6-7 2846000 -0.04% 100.05% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-9 1530000 -0.02% 100.03% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::10-11 743500 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-13 398000 -0.00% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::14-15 810000 -0.01% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-17 216000 -0.00% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::18-19 164500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-21 85000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::22-23 84500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-25 64500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::26-27 35000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-29 17500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::30-31 59500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -8047359064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 1874 70.21% 70.21% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::1M 795 29.79% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 2669 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 33989 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walks 34281 # Table walker walks requested +system.cpu3.dtb.walker.walksShort 34281 # Table walker walks initiated with short descriptors +system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 10962 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 8120 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 15199 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 19082 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 497.143905 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 3025.740716 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-8191 18625 97.61% 97.61% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::8192-16383 304 1.59% 99.20% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::16384-24575 96 0.50% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::24576-32767 29 0.15% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-40959 9 0.05% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::40960-49151 16 0.08% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::49152-57343 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 19082 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 6403 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 11721.380603 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 9562.982056 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 7657.065586 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-8191 2445 38.19% 38.19% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::8192-16383 2784 43.48% 81.66% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::16384-24575 982 15.34% 97.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::24576-32767 97 1.51% 98.52% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-40959 43 0.67% 99.19% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::40960-49151 36 0.56% 99.75% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::49152-57343 11 0.17% 99.92% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-73727 1 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 6403 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -8551346564 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.449587 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::stdev 0.363024 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-1 -8598250064 100.55% 100.55% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::2-3 33569000 -0.39% 100.16% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-5 6441000 -0.08% 100.08% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::6-7 2603000 -0.03% 100.05% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-9 1836000 -0.02% 100.03% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::10-11 609000 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-13 358000 -0.00% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::14-15 901500 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-17 248500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::18-19 75500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-21 42000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::22-23 21500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-25 24500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::26-27 20500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-29 9000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::30-31 144500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -8551346564 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 1841 71.89% 71.89% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::1M 720 28.11% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 2561 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 34281 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 33989 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2669 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 34281 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2561 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2669 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 36658 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2561 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 36842 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 7187448 # DTB read hits -system.cpu3.dtb.read_misses 29423 # DTB read misses -system.cpu3.dtb.write_hits 5346423 # DTB write hits -system.cpu3.dtb.write_misses 4566 # DTB write misses -system.cpu3.dtb.flush_tlb 162 # Number of times complete TLB was flushed -system.cpu3.dtb.flush_tlb_mva 274 # Number of times TLB was flushed by MVA +system.cpu3.dtb.read_hits 7461875 # DTB read hits +system.cpu3.dtb.read_misses 28710 # DTB read misses +system.cpu3.dtb.write_hits 5703324 # DTB write hits +system.cpu3.dtb.write_misses 5571 # DTB write misses +system.cpu3.dtb.flush_tlb 157 # Number of times complete TLB was flushed +system.cpu3.dtb.flush_tlb_mva 225 # Number of times TLB was flushed by MVA system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 1921 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 451 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 735 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_entries 1703 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 376 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 690 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 408 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 7216871 # DTB read accesses -system.cpu3.dtb.write_accesses 5350989 # DTB write accesses +system.cpu3.dtb.perms_faults 330 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 7490585 # DTB read accesses +system.cpu3.dtb.write_accesses 5708895 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 12533871 # DTB hits -system.cpu3.dtb.misses 33989 # DTB misses -system.cpu3.dtb.accesses 12567860 # DTB accesses +system.cpu3.dtb.hits 13165199 # DTB hits +system.cpu3.dtb.misses 34281 # DTB misses +system.cpu3.dtb.accesses 13199480 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1701,388 +1718,383 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 4586 # Table walker walks requested -system.cpu3.itb.walker.walksShort 4586 # Table walker walks initiated with short descriptors -system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1476 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2630 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 480 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 4106 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1386.751096 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 5919.935544 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-8191 3869 94.23% 94.23% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::8192-16383 140 3.41% 97.64% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::16384-24575 51 1.24% 98.88% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::24576-32767 18 0.44% 99.32% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-40959 9 0.22% 99.54% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::40960-49151 8 0.19% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::49152-57343 3 0.07% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::57344-65535 2 0.05% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-73727 1 0.02% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.02% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::81920-90111 2 0.05% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::90112-98303 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::106496-114687 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 4106 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 1793 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 12167.875070 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 9929.586957 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 7490.636626 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-4095 25 1.39% 1.39% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::4096-8191 685 38.20% 39.60% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::8192-12287 343 19.13% 58.73% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::12288-16383 337 18.80% 77.52% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::16384-20479 34 1.90% 79.42% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::20480-24575 327 18.24% 97.66% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::24576-28671 25 1.39% 99.05% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::28672-32767 2 0.11% 99.16% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-36863 8 0.45% 99.61% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::36864-40959 3 0.17% 99.78% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::40960-45055 1 0.06% 99.83% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::45056-49151 1 0.06% 99.89% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::49152-53247 2 0.11% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 1793 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -8048628564 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.273756 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.444979 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -5842963052 72.60% 72.60% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -2207299512 27.42% 100.02% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 1197000 -0.01% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 240000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 159500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 37500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -8048628564 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 959 73.04% 73.04% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::1M 354 26.96% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 1313 # Table walker page sizes translated +system.cpu3.itb.walker.walks 4255 # Table walker walks requested +system.cpu3.itb.walker.walksShort 4255 # Table walker walks initiated with short descriptors +system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1348 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2480 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 427 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 3828 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1433.646813 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 5723.775049 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-8191 3573 93.34% 93.34% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::8192-16383 172 4.49% 97.83% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::16384-24575 42 1.10% 98.93% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::24576-32767 19 0.50% 99.43% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-40959 8 0.21% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::40960-49151 2 0.05% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::49152-57343 3 0.08% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::57344-65535 3 0.08% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-73727 3 0.08% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::81920-90111 1 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::98304-106495 1 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 3828 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 1607 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 11553.827007 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 9422.694802 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 7714.919558 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-8191 693 43.12% 43.12% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::8192-16383 629 39.14% 82.27% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::16384-24575 247 15.37% 97.64% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::24576-32767 18 1.12% 98.76% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-40959 11 0.68% 99.44% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::40960-49151 4 0.25% 99.69% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::49152-57343 2 0.12% 99.81% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::57344-65535 2 0.12% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::81920-90111 1 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 1607 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -8760206064 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.998053 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.036484 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -15003296 0.17% 0.17% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -8746780268 99.85% 100.02% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 1238500 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 234500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 77000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 27500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -8760206064 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 845 71.61% 71.61% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::1M 335 28.39% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 1180 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4586 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4586 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4255 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4255 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1313 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1313 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 5899 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 9766986 # ITB inst hits -system.cpu3.itb.inst_misses 4586 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1180 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1180 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 5435 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 9881127 # ITB inst hits +system.cpu3.itb.inst_misses 4255 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.flush_tlb 162 # Number of times complete TLB was flushed -system.cpu3.itb.flush_tlb_mva 274 # Number of times TLB was flushed by MVA +system.cpu3.itb.flush_tlb 157 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb_mva 225 # Number of times TLB was flushed by MVA system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 1310 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_entries 1190 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 793 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 704 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 9771572 # ITB inst accesses -system.cpu3.itb.hits 9766986 # DTB hits -system.cpu3.itb.misses 4586 # DTB misses -system.cpu3.itb.accesses 9771572 # DTB accesses -system.cpu3.numCycles 57688006 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 9885382 # ITB inst accesses +system.cpu3.itb.hits 9881127 # DTB hits +system.cpu3.itb.misses 4255 # DTB misses +system.cpu3.itb.accesses 9885382 # DTB accesses +system.cpu3.numCycles 55785273 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 20811649 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 52033022 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 13252062 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 9316448 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 33930227 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1581201 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 68181 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 837 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 231 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 120341 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 80383 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 479 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 9765486 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 207700 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 2399 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 55802907 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.126480 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.271736 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 20908003 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 53885921 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 13553669 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 9478152 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 32386359 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 1568366 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 62721 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 789 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 205 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 111844 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 71140 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 397 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 9879794 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 204446 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 2262 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 54325621 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.196451 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.331638 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 41696580 74.72% 74.72% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 1836235 3.29% 78.01% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 1165184 2.09% 80.10% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3688211 6.61% 86.71% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 906128 1.62% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 549241 0.98% 89.32% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2914438 5.22% 94.54% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 602830 1.08% 95.62% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2444060 4.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 39861207 73.37% 73.37% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 1851185 3.41% 76.78% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 1193872 2.20% 78.98% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3684209 6.78% 85.76% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 942616 1.74% 87.50% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 608186 1.12% 88.62% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2968602 5.46% 94.08% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 642558 1.18% 95.26% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2573186 4.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 55802907 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.229720 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.901973 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 14568551 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 31866325 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 7772560 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 890718 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 704494 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 971899 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 87220 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 44590073 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 289455 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 704494 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 15048291 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 3770246 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 21829644 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 8174749 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 6275200 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 42740400 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 1148 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 970300 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 89126 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 4852570 # Number of times rename has blocked due to SQ full -system.cpu3.rename.RenamedOperands 44469975 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 196242063 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 47658053 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 4195 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 37088424 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 7381551 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 715073 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 665430 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 5054867 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 7671703 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 5900822 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 1096118 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 1546348 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 41143800 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 502182 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 39136171 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 53747 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 5932287 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 13678209 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 53132 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 55802907 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.701329 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.406589 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 54325621 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.242961 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.965952 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 14640830 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 30019697 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 7950688 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 1013386 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 700819 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 1055619 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 84442 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 46804919 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 276831 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 700819 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 15165685 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 3026849 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 21377967 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 8430789 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 5623288 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 44934032 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 688 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 1185922 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 108960 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 3941702 # Number of times rename has blocked due to SQ full +system.cpu3.rename.RenamedOperands 46859897 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 206328923 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 50493322 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 4028 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 39227152 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 7632745 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 719514 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 667644 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 5723010 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 7961886 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 6281204 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1151663 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1548732 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 43283754 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 518690 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 41211343 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 55539 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 6082671 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 14073441 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 54569 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 54325621 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.758599 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.457347 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 40242389 72.12% 72.12% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 5178782 9.28% 81.40% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 3976738 7.13% 88.52% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 3203416 5.74% 94.26% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 1255770 2.25% 96.51% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 764374 1.37% 97.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 832269 1.49% 99.37% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 238251 0.43% 99.80% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 110918 0.20% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 38109275 70.15% 70.15% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 5329887 9.81% 79.96% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 4096389 7.54% 87.50% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 3334773 6.14% 93.64% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 1373143 2.53% 96.17% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 820036 1.51% 97.68% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 873869 1.61% 99.29% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 257599 0.47% 99.76% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 130650 0.24% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 55802907 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 54325621 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 55578 9.37% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 279414 47.11% 56.48% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 258161 43.52% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 64574 10.28% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 290075 46.19% 56.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 273390 43.53% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 84 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 26095745 66.68% 66.68% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 29921 0.08% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 2385 0.01% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 7397516 18.90% 85.66% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 5610518 14.34% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 62 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 27512271 66.76% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 31067 0.08% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.83% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 2328 0.01% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 7676586 18.63% 85.47% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 5989019 14.53% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 39136171 # Type of FU issued -system.cpu3.iq.rate 0.678411 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 593153 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.015156 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 134713370 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 47601786 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 37987762 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 8779 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 5136 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 3873 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 39724534 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 4706 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 167566 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 41211343 # Type of FU issued +system.cpu3.iq.rate 0.738750 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 628039 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.015239 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 137423296 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 49907895 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 40057354 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 8589 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 4965 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 3611 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 41834646 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 4674 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 172531 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1160486 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 1105 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 29281 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 565962 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1192076 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 1205 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 28350 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 578137 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 108568 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 42515 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 104077 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 43928 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 704494 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 3163832 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 480485 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 41688387 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 67679 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 7671703 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 5900822 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 259528 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 22774 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 451647 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 29281 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 127480 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 130164 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 257644 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 38819012 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 7269209 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 283254 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 700819 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 2631103 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 281724 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 43863625 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 65733 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 7961886 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 6281204 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 267636 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 25569 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 250025 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 28350 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 127807 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 129932 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 257739 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 40889959 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 7546719 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 287191 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 42405 # number of nop insts executed -system.cpu3.iew.exec_refs 12824644 # number of memory reference insts executed -system.cpu3.iew.exec_branches 7229166 # Number of branches executed -system.cpu3.iew.exec_stores 5555435 # Number of stores executed -system.cpu3.iew.exec_rate 0.672913 # Inst execution rate -system.cpu3.iew.wb_sent 38534594 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 37991635 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 19895864 # num instructions producing a value -system.cpu3.iew.wb_consumers 34654258 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.658571 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.574125 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 5941608 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 449050 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 213879 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 54520380 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.655522 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.547792 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 61181 # number of nop insts executed +system.cpu3.iew.exec_refs 13479054 # number of memory reference insts executed +system.cpu3.iew.exec_branches 7536416 # Number of branches executed +system.cpu3.iew.exec_stores 5932335 # Number of stores executed +system.cpu3.iew.exec_rate 0.732988 # Inst execution rate +system.cpu3.iew.wb_sent 40598245 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 40060965 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 21086862 # num instructions producing a value +system.cpu3.iew.wb_consumers 37255215 # num instructions consuming a value +system.cpu3.iew.wb_rate 0.718128 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.566011 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 6097187 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 464121 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 213352 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 53027988 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.712050 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.609623 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 40723432 74.69% 74.69% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 6130706 11.24% 85.94% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 3105147 5.70% 91.63% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 1318175 2.42% 94.05% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 725189 1.33% 95.38% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 499185 0.92% 96.30% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 937323 1.72% 98.02% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 226618 0.42% 98.43% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 854605 1.57% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 38640336 72.87% 72.87% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 6301176 11.88% 84.75% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 3204029 6.04% 90.79% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 1405492 2.65% 93.44% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 791559 1.49% 94.94% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 551412 1.04% 95.98% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 959183 1.81% 97.78% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 243958 0.46% 98.24% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 930843 1.76% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 54520380 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 29254285 # Number of instructions committed -system.cpu3.commit.committedOps 35739310 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 53027988 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 30988188 # Number of instructions committed +system.cpu3.commit.committedOps 37758554 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 11846077 # Number of memory references committed -system.cpu3.commit.loads 6511217 # Number of loads committed -system.cpu3.commit.membars 174051 # Number of memory barriers committed -system.cpu3.commit.branches 6823843 # Number of branches committed -system.cpu3.commit.fp_insts 3728 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 31222167 # Number of committed integer instructions. -system.cpu3.commit.function_calls 1239499 # Number of function calls committed. +system.cpu3.commit.refs 12472877 # Number of memory references committed +system.cpu3.commit.loads 6769810 # Number of loads committed +system.cpu3.commit.membars 181184 # Number of memory barriers committed +system.cpu3.commit.branches 7122308 # Number of branches committed +system.cpu3.commit.fp_insts 3347 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 32924881 # Number of committed integer instructions. +system.cpu3.commit.function_calls 1244375 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 23861884 66.77% 66.77% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 28964 0.08% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 2385 0.01% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 6511217 18.22% 85.07% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 5334860 14.93% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 25253254 66.88% 66.88% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 30097 0.08% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.96% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 2326 0.01% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 6769810 17.93% 84.90% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 5703067 15.10% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 35739310 # Class of committed instruction -system.cpu3.commit.bw_lim_events 854605 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 89694977 # The number of ROB reads -system.cpu3.rob.rob_writes 84644260 # The number of ROB writes -system.cpu3.timesIdled 227108 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1885099 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 5160958859 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 29228670 # Number of Instructions Simulated -system.cpu3.committedOps 35713695 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.973679 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.973679 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.506668 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.506668 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 42269766 # number of integer regfile reads -system.cpu3.int_regfile_writes 24060528 # number of integer regfile writes -system.cpu3.fp_regfile_reads 14520 # number of floating regfile reads -system.cpu3.fp_regfile_writes 12259 # number of floating regfile writes -system.cpu3.cc_regfile_reads 137213612 # number of cc regfile reads -system.cpu3.cc_regfile_writes 14769581 # number of cc regfile writes -system.cpu3.misc_regfile_reads 75722157 # number of misc regfile reads -system.cpu3.misc_regfile_writes 336126 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 30181 # Transaction distribution -system.iobus.trans_dist::ReadResp 30181 # Transaction distribution +system.cpu3.commit.op_class_0::total 37758554 # Class of committed instruction +system.cpu3.commit.bw_lim_events 930843 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 90355965 # The number of ROB reads +system.cpu3.rob.rob_writes 89008997 # The number of ROB writes +system.cpu3.timesIdled 227180 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1459652 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 5161855344 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 30949407 # Number of Instructions Simulated +system.cpu3.committedOps 37719773 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.802467 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.802467 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.554795 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.554795 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 44810806 # number of integer regfile reads +system.cpu3.int_regfile_writes 25112765 # number of integer regfile writes +system.cpu3.fp_regfile_reads 14550 # number of floating regfile reads +system.cpu3.fp_regfile_writes 12084 # number of floating regfile writes +system.cpu3.cc_regfile_reads 144202792 # number of cc regfile reads +system.cpu3.cc_regfile_writes 15932581 # number of cc regfile writes +system.cpu3.misc_regfile_reads 74870960 # number of misc regfile reads +system.cpu3.misc_regfile_writes 343753 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30152 # Transaction distribution +system.iobus.trans_dist::ReadResp 30152 # Transaction distribution system.iobus.trans_dist::WriteReq 59010 # Transaction distribution system.iobus.trans_dist::WriteResp 59010 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54148 # Packet count per connected master and slave (bytes) @@ -2105,9 +2117,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105436 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178324 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67865 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -2128,791 +2140,845 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159093 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480317 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 27737500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480085 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 30018500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 101500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 203000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 228500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 19500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 13000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 1500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 40500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 3864000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 3980500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 22351500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 22050500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 78673017 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 72564537 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 48334000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 50308000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 15512000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 14254000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36409 # number of replacements -system.iocache.tags.tagsinuse 1.005569 # Cycle average of tags in use -system.iocache.tags.total_refs 30 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 249219554509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.005569 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062848 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062848 # Average percentage of cache occupancy +system.iocache.tags.replacements 36410 # number of replacements +system.iocache.tags.tagsinuse 1.002475 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 248713478009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.002475 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062655 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062655 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328227 # Number of tag accesses -system.iocache.tags.data_accesses 328227 # Number of data accesses -system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits -system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits -system.iocache.demand_hits::realview.ide 29 # number of demand (read+write) hits -system.iocache.demand_hits::total 29 # number of demand (read+write) hits -system.iocache.overall_hits::realview.ide 29 # number of overall hits -system.iocache.overall_hits::total 29 # number of overall hits -system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses -system.iocache.ReadReq_misses::total 249 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses +system.iocache.tags.tag_accesses 327996 # Number of tag accesses +system.iocache.tags.data_accesses 327996 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses +system.iocache.ReadReq_misses::total 220 # number of ReadReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 36444 # number of demand (read+write) misses system.iocache.demand_misses::total 36444 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36444 # number of overall misses system.iocache.overall_misses::total 36444 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 17512919 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 17512919 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 1907451098 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 1907451098 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 1924964017 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1924964017 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 1924964017 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1924964017 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_latency::realview.ide 16064414 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 16064414 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 1679848123 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 1679848123 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 1695912537 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1695912537 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 1695912537 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1695912537 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36473 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36473 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36473 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36473 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36444 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36444 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36444 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36444 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::realview.ide 0.999205 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 0.999205 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ide 0.999205 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 0.999205 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 70333.008032 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 70333.008032 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 52699.298190 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 52699.298190 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 52819.778756 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 52819.778756 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 52819.778756 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 52819.778756 # average overall miss latency +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ide 73020.063636 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 73020.063636 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 46373.899155 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 46373.899155 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 46534.752963 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 46534.752963 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 46534.752963 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 46534.752963 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 36160 # number of writebacks -system.iocache.writebacks::total 36160 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 148 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 148 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 15187 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 15187 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 15335 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 15335 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 15335 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 15335 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 10112919 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 10112919 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 1147424968 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1147424968 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1157537887 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1157537887 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1157537887 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1157537887 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.594378 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.419252 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.419252 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.420448 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.420448 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.420448 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.420448 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68330.533784 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68330.533784 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75553.102522 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75553.102522 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75483.396609 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75483.396609 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75483.396609 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75483.396609 # average overall mshr miss latency -system.l2c.tags.replacements 103654 # number of replacements -system.l2c.tags.tagsinuse 65094.562604 # Cycle average of tags in use -system.l2c.tags.total_refs 5149240 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168905 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 30.486013 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 80133862000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49018.245060 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.971846 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4276.002230 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2253.870491 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.966972 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 903.622290 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 882.214681 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 22.046662 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1923.753709 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 720.306234 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 49.949258 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 3365.651463 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 1676.961612 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.747959 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 135 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 135 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 13984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 13984 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 14119 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 14119 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 14119 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 14119 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 9314414 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 9314414 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 979789535 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 979789535 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 989103949 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 989103949 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 989103949 # 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Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 79348480000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 49045.638268 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.902700 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.002962 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4655.400387 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1832.462463 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000002 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 777.111964 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 859.577397 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 20.871513 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.006796 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2228.936773 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 823.872322 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 51.838280 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.itb.walker 0.001832 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2977.448230 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 1828.803519 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.748377 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.065247 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.034391 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.013788 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013462 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000336 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.029354 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.010991 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000762 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.051356 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.025588 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993264 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 64 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65187 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 64 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2167 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7607 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55305 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994675 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45502395 # Number of tag accesses -system.l2c.tags.data_accesses 45502395 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4144 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2033 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1722 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 868 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 13393 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 1189 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 21091 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 4127 # number of ReadReq hits -system.l2c.ReadReq_hits::total 48567 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 692123 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 692123 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1939703 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1939703 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 11 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 42 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 67 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu3.data 17 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 19 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 66572 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 17866 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 28004 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3.data 44210 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 156652 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 721971 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 204101 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 492422 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 538161 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1956655 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 211223 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 72596 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 101112 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 137861 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 522792 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4144 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2033 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 721971 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 277795 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 1722 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 868 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 204101 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 90462 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 13393 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 1189 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 492422 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 129116 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.dtb.walker 21091 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.itb.walker 4127 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 538161 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 182071 # number of demand (read+write) hits -system.l2c.demand_hits::total 2684666 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4144 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2033 # number of overall hits -system.l2c.overall_hits::cpu0.inst 721971 # number of overall hits -system.l2c.overall_hits::cpu0.data 277795 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 1722 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 868 # number of overall hits -system.l2c.overall_hits::cpu1.inst 204101 # number of overall hits -system.l2c.overall_hits::cpu1.data 90462 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 13393 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 1189 # number of overall hits -system.l2c.overall_hits::cpu2.inst 492422 # number of overall hits -system.l2c.overall_hits::cpu2.data 129116 # number of overall hits -system.l2c.overall_hits::cpu3.dtb.walker 21091 # number of overall hits -system.l2c.overall_hits::cpu3.itb.walker 4127 # number of overall hits -system.l2c.overall_hits::cpu3.inst 538161 # number of overall hits -system.l2c.overall_hits::cpu3.data 182071 # number of overall hits -system.l2c.overall_hits::total 2684666 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # 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Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.027905 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993422 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65111 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 59 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2175 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8177 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54718 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000900 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.993515 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 45392022 # Number of tag accesses +system.l2c.tags.data_accesses 45392022 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4238 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2128 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 1538 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 869 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 12508 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 1155 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.dtb.walker 20749 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.itb.walker 3757 # number of ReadReq hits +system.l2c.ReadReq_hits::total 46942 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 692418 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 692418 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1933833 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1933833 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 8 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3.data 33 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 59 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu3.data 19 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 20 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 66454 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 22443 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 25986 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3.data 44665 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 159548 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 735257 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 209850 # 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number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 558688000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1395919500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1578780500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3533388000 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 558688000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 1395919500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3.data 1578780500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3533388000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000650 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002234 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000865 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003362 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.002147 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989605 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.981900 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.957143 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.585704 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.296296 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.275862 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.346771 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.532020 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.533515 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.311759 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.009062 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.011223 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.011128 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006734 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.033696 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.023037 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.030342 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.016633 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000650 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009062 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.135201 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002234 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000865 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011223 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.213736 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003362 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.011128 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.230693 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.040262 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000650 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009062 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.135201 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002234 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000865 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011223 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.213736 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003362 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.011128 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.230693 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.040262 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74732.142857 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 76307.142857 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 75930.693069 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18974.789916 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 18981.566820 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 19021.709634 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18997.571342 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 32062.500000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 32062.500000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68568.532819 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67019.125313 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 72527.572774 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70259.355515 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72691.245440 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72362.412949 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73311.548643 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72842.045797 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74047.865727 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72685.714286 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 78755.978137 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76035.238841 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72691.245440 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69491.379912 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74732.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72362.412949 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67401.048079 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 76307.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73311.548643 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 73020.577207 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 71012.402595 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72691.245440 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69491.379912 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74732.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72362.412949 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67401.048079 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 76307.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73311.548643 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 73020.577207 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 71012.402595 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163168.224299 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196193.886156 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202667.586650 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 192775.819739 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 89361.484325 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 113406.409944 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 112384.716686 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 108356.220675 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 348991 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 146410 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.trans_dist::ReadReq 40114 # Transaction distribution -system.membus.trans_dist::ReadResp 76256 # Transaction distribution +system.membus.trans_dist::ReadResp 75609 # Transaction distribution system.membus.trans_dist::WriteReq 27565 # Transaction distribution system.membus.trans_dist::WriteResp 27565 # Transaction distribution -system.membus.trans_dist::WritebackDirty 131145 # Transaction distribution -system.membus.trans_dist::CleanEvict 8918 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4561 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1773 # Transaction distribution -system.membus.trans_dist::ReadExReq 137930 # Transaction distribution -system.membus.trans_dist::ReadExResp 137930 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 36142 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution -system.membus.trans_dist::InvalidateResp 21008 # Transaction distribution +system.membus.trans_dist::WritebackDirty 128684 # Transaction distribution +system.membus.trans_dist::CleanEvict 8545 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4547 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1834 # Transaction distribution +system.membus.trans_dist::ReadExReq 135487 # Transaction distribution +system.membus.trans_dist::ReadExResp 135487 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 35495 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 22240 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 485390 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 592842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 93962 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 93962 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 686804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 476439 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 583891 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 95179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679070 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17249660 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17412785 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2320704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2320704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19733489 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 305 # Total snoops (count) -system.membus.snoop_fanout::samples 422579 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16891580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17054705 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2321600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19376305 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 335 # Total snoops (count) +system.membus.snoop_fanout::samples 342553 # Request fanout histogram +system.membus.snoop_fanout::mean 0.015446 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.123318 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 422579 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 337262 98.46% 98.46% # Request fanout histogram +system.membus.snoop_fanout::1 5291 1.54% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 422579 # Request fanout histogram -system.membus.reqLayer0.occupancy 54358000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 342553 # Request fanout histogram +system.membus.reqLayer0.occupancy 56458000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 678498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 682999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 480577516 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 493971550 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 576478500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 649041000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 796581 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 721087 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2955,60 +3021,60 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5652843 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2841066 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 44935 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 620 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 620 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5640723 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2834949 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 44718 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 306 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 306 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 111947 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2627538 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 110707 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2619793 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 760857 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1977299 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 146342 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2855 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2881 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296355 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296355 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1977848 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 537745 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 15186 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5950911 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2624542 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 25489 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 101525 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8702467 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 253157304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97861113 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41336 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 179388 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 351239141 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 193521 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4203916 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021594 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.145353 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 747367 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1971000 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 146335 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2812 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2841 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296829 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296829 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1971549 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 537547 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4488 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5931996 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2625304 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 25197 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 99111 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8681608 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 252349880 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97897081 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 40804 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 174056 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 350461821 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 123025 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4134634 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021870 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.146260 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4113137 97.84% 97.84% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 90779 2.16% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4044208 97.81% 97.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 90426 2.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4203916 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3441095952 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4134634 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3415021456 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 260919 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 230913 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1872616750 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1843284752 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 760133706 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 768458163 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11021467 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10591473 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 48273206 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 47113721 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index c3b5f0f58..a8fee84d0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.817566 # Number of seconds simulated -sim_ticks 2817566302500 # Number of ticks simulated -final_tick 2817566302500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.804583 # Number of seconds simulated +sim_ticks 2804582834000 # Number of ticks simulated +final_tick 2804582834000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130714 # Simulator instruction rate (inst/s) -host_op_rate 158652 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3149885183 # Simulator tick rate (ticks/s) -host_mem_usage 588664 # Number of bytes of host memory used -host_seconds 894.50 # Real time elapsed on the host -sim_insts 116922977 # Number of instructions simulated -sim_ops 141913965 # Number of ops (including micro ops) simulated +host_inst_rate 128680 # Simulator instruction rate (inst/s) +host_op_rate 156182 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3087037891 # Simulator tick rate (ticks/s) +host_mem_usage 586780 # Number of bytes of host memory used +host_seconds 908.50 # Real time elapsed on the host +sim_insts 116905819 # Number of instructions simulated +sim_ops 141891765 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 3776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 3968 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 681792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5202336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 4864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 690880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4586120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 685504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5035168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 4288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 692224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4774856 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11170792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 681792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 690880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1372672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8446592 # Number of bytes written to this memory +system.physmem.bytes_read::total 11197032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 685504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 692224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1377728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8413760 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8464116 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 59 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8431284 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 62 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10653 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 81805 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 76 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10795 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 71660 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10711 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 79193 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 67 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74609 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175064 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131978 # Number of write requests responded to by this memory +system.physmem.num_reads::total 175474 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131465 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136359 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1340 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 135846 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1415 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 241979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1846393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 245205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1627688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3964695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 241979 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 245205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 487184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2997833 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6217 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 244423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1795336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 246819 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1702519 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3992406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 244423 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 246819 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 491242 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3000004 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6245 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3004052 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2997833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3006252 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3000004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1415 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 241979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1852610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1726 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 245205 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1627691 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6968747 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175065 # Number of read requests accepted -system.physmem.writeReqs 136359 # Number of write requests accepted -system.physmem.readBursts 175065 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 136359 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11195328 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8832 # Total number of bytes read from write queue -system.physmem.bytesWritten 8476864 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11170856 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8464116 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 138 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 244423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1801581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 246819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1702522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6998658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175475 # Number of read requests accepted +system.physmem.writeReqs 135846 # Number of write requests accepted +system.physmem.readBursts 175475 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 135846 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11220480 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9920 # Total number of bytes read from write queue +system.physmem.bytesWritten 8444352 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11197096 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8431284 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 155 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12026 # Per bank write bursts -system.physmem.perBankRdBursts::1 11043 # Per bank write bursts -system.physmem.perBankRdBursts::2 11014 # Per bank write bursts -system.physmem.perBankRdBursts::3 11213 # Per bank write bursts -system.physmem.perBankRdBursts::4 11525 # Per bank write bursts -system.physmem.perBankRdBursts::5 11226 # Per bank write bursts -system.physmem.perBankRdBursts::6 11723 # Per bank write bursts -system.physmem.perBankRdBursts::7 11697 # Per bank write bursts -system.physmem.perBankRdBursts::8 10818 # Per bank write bursts -system.physmem.perBankRdBursts::9 11281 # Per bank write bursts -system.physmem.perBankRdBursts::10 10383 # Per bank write bursts -system.physmem.perBankRdBursts::11 9838 # Per bank write bursts -system.physmem.perBankRdBursts::12 10204 # Per bank write bursts -system.physmem.perBankRdBursts::13 10800 # Per bank write bursts -system.physmem.perBankRdBursts::14 10202 # Per bank write bursts -system.physmem.perBankRdBursts::15 9934 # Per bank write bursts -system.physmem.perBankWrBursts::0 8926 # Per bank write bursts -system.physmem.perBankWrBursts::1 8447 # Per bank write bursts -system.physmem.perBankWrBursts::2 8579 # Per bank write bursts -system.physmem.perBankWrBursts::3 8754 # Per bank write bursts -system.physmem.perBankWrBursts::4 8390 # Per bank write bursts -system.physmem.perBankWrBursts::5 8423 # Per bank write bursts -system.physmem.perBankWrBursts::6 8479 # Per bank write bursts -system.physmem.perBankWrBursts::7 8702 # Per bank write bursts -system.physmem.perBankWrBursts::8 8251 # Per bank write bursts -system.physmem.perBankWrBursts::9 8712 # Per bank write bursts -system.physmem.perBankWrBursts::10 8030 # Per bank write bursts -system.physmem.perBankWrBursts::11 7698 # Per bank write bursts -system.physmem.perBankWrBursts::12 7882 # Per bank write bursts -system.physmem.perBankWrBursts::13 8282 # Per bank write bursts -system.physmem.perBankWrBursts::14 7677 # Per bank write bursts -system.physmem.perBankWrBursts::15 7219 # Per bank write bursts +system.physmem.perBankRdBursts::0 11302 # Per bank write bursts +system.physmem.perBankRdBursts::1 11252 # Per bank write bursts +system.physmem.perBankRdBursts::2 11256 # Per bank write bursts +system.physmem.perBankRdBursts::3 10710 # Per bank write bursts +system.physmem.perBankRdBursts::4 11532 # Per bank write bursts +system.physmem.perBankRdBursts::5 11381 # Per bank write bursts +system.physmem.perBankRdBursts::6 12180 # Per bank write bursts +system.physmem.perBankRdBursts::7 12061 # Per bank write bursts +system.physmem.perBankRdBursts::8 10232 # Per bank write bursts +system.physmem.perBankRdBursts::9 10264 # Per bank write bursts +system.physmem.perBankRdBursts::10 10575 # Per bank write bursts +system.physmem.perBankRdBursts::11 9266 # Per bank write bursts +system.physmem.perBankRdBursts::12 10585 # Per bank write bursts +system.physmem.perBankRdBursts::13 11349 # Per bank write bursts +system.physmem.perBankRdBursts::14 10873 # Per bank write bursts +system.physmem.perBankRdBursts::15 10502 # Per bank write bursts +system.physmem.perBankWrBursts::0 8422 # Per bank write bursts +system.physmem.perBankWrBursts::1 8567 # Per bank write bursts +system.physmem.perBankWrBursts::2 8697 # Per bank write bursts +system.physmem.perBankWrBursts::3 8116 # Per bank write bursts +system.physmem.perBankWrBursts::4 8443 # Per bank write bursts +system.physmem.perBankWrBursts::5 8487 # Per bank write bursts +system.physmem.perBankWrBursts::6 9141 # Per bank write bursts +system.physmem.perBankWrBursts::7 9034 # Per bank write bursts +system.physmem.perBankWrBursts::8 7740 # Per bank write bursts +system.physmem.perBankWrBursts::9 7663 # Per bank write bursts +system.physmem.perBankWrBursts::10 7868 # Per bank write bursts +system.physmem.perBankWrBursts::11 6935 # Per bank write bursts +system.physmem.perBankWrBursts::12 8081 # Per bank write bursts +system.physmem.perBankWrBursts::13 8671 # Per bank write bursts +system.physmem.perBankWrBursts::14 8304 # Per bank write bursts +system.physmem.perBankWrBursts::15 7774 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 24 # Number of times write queue was full causing retry -system.physmem.totGap 2817566126000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 2804582655500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 174509 # Read request sizes (log2) +system.physmem.readPktSize::6 174919 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131978 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 104121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1707 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131465 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 103782 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -161,179 +161,179 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 104 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 100 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65817 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.891289 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.511638 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.918519 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24962 37.93% 37.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16108 24.47% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6699 10.18% 72.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3770 5.73% 78.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2952 4.49% 82.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1615 2.45% 85.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1043 1.58% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1102 1.67% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7566 11.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65817 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6524 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.807940 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 488.205097 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6522 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 36 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64935 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.837730 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.379870 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.140175 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24467 37.68% 37.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15703 24.18% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6760 10.41% 72.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3722 5.73% 78.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2848 4.39% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1541 2.37% 84.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1091 1.68% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1047 1.61% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7756 11.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64935 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6659 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.328127 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 478.808129 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6657 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6524 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6524 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.302115 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.296217 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.183093 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 18 0.28% 0.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 6 0.09% 0.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 6 0.09% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 9 0.14% 0.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5697 87.32% 87.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 177 2.71% 90.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 43 0.66% 91.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 57 0.87% 92.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 27 0.41% 92.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 20 0.31% 92.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 60 0.92% 93.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.15% 93.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 144 2.21% 96.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 12 0.18% 96.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.08% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 10 0.15% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 63 0.97% 97.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 9 0.14% 97.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.03% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 26 0.40% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 90 1.38% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.05% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 5 0.08% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.14% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6659 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6659 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.814236 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.240992 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.368669 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 11 0.17% 0.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 8 0.12% 0.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 5 0.08% 0.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 7 0.11% 0.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5729 86.03% 86.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 143 2.15% 88.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 83 1.25% 89.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 58 0.87% 90.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 282 4.23% 95.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 54 0.81% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 22 0.33% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.15% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.20% 96.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 9 0.14% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.12% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.08% 96.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 158 2.37% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.03% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 9 0.14% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.05% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 6 0.09% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.20% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6524 # Writes before turning the bus around for reads -system.physmem.totQLat 2763863500 # Total ticks spent queuing -system.physmem.totMemAccLat 6043744750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 874635000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15800.10 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6659 # Writes before turning the bus around for reads +system.physmem.totQLat 2658321750 # Total ticks spent queuing +system.physmem.totMemAccLat 5945571750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 876600000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15162.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34550.10 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.97 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 33912.68 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.00 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.01 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.96 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.00 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.99 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.81 # Average write queue length when enqueuing -system.physmem.readRowHits 143943 # Number of row buffer hits during reads -system.physmem.writeRowHits 97617 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.69 # Row buffer hit rate for writes -system.physmem.avgGap 9047363.49 # Average gap between requests -system.physmem.pageHitRate 78.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 262097640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 143009625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 713442600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 445176000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184029555840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 80250373530 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1620143225250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1885986880485 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.367938 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2695137554500 # Time in different power states -system.physmem_0.memoryStateTime::REF 94084640000 # Time in different power states +system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.41 # Average write queue length when enqueuing +system.physmem.readRowHits 144869 # Number of row buffer hits during reads +system.physmem.writeRowHits 97458 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.86 # Row buffer hit rate for writes +system.physmem.avgGap 9008652.34 # Average gap between requests +system.physmem.pageHitRate 78.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 258385680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 140984250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 715049400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 446517360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 183181277760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 78012609390 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1614313697250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1877068521090 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.287723 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2685462700000 # Time in different power states +system.physmem_0.memoryStateTime::REF 93650960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28341635500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 25469163500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 235478880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 128485500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 650980200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 413106480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184029555840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79085591640 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1621164963750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1885708162290 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.269016 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2696848801250 # Time in different power states -system.physmem_1.memoryStateTime::REF 94084640000 # Time in different power states +system.physmem_1.actEnergy 232522920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 126872625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 652438800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 408473280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 183181277760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 77055662610 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1615153124250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1876810372245 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.195678 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2686857596250 # Time in different power states +system.physmem_1.memoryStateTime::REF 93650960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 26632850750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 24067808750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 768 # Number of bytes read from this memory @@ -341,31 +341,31 @@ system.realview.nvmem.bytes_inst_read::cpu0.inst 768 system.realview.nvmem.bytes_inst_read::total 768 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 12 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 273 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 273 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 273 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 273 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 273 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 273 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 274 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 274 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 274 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 274 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 274 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 274 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 26582301 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13715885 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 494954 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 15490869 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8022372 # Number of BTB hits +system.cpu0.branchPred.lookups 26563319 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13759388 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 495774 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 16214186 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8026564 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 51.787747 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6629975 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28839 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4497397 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 4389117 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 108280 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 31787 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 49.503342 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6609603 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28316 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4513473 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 4401835 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 111638 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 31883 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -396,88 +396,88 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 58814 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 58814 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17346 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14926 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 26542 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 32272 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 726.791026 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 4755.027696 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-16383 31886 98.80% 98.80% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-32767 277 0.86% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-49151 61 0.19% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-65535 23 0.07% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-81919 11 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::81920-98303 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-114687 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::114688-131071 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::147456-163839 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::163840-180223 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::180224-196607 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 32272 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 12665 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 13014.923016 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 10587.989224 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 9127.008729 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 12438 98.21% 98.21% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 206 1.63% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 5 0.04% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 9 0.07% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 6 0.05% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 12665 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 90261197040 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.667138 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.493122 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 90178529040 99.91% 99.91% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 56487500 0.06% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 11942500 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 4980500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 3127500 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1706500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 1155500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 2289000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 484000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 141500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-21 89500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::22-23 39000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-25 163500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::26-27 25500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-29 11500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::30-31 24500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 90261197040 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3551 69.31% 69.31% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1572 30.69% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5123 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 58814 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 59132 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 59132 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17796 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14691 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 26645 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 32487 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 741.511989 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 4828.940187 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-16383 32073 98.73% 98.73% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-32767 302 0.93% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-49151 58 0.18% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-65535 24 0.07% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-81919 12 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::81920-98303 5 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-114687 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::114688-131071 5 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::147456-163839 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 32487 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 12954 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 13356.453605 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11053.395474 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 8313.507092 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 9693 74.83% 74.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 2999 23.15% 97.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 232 1.79% 99.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 12 0.09% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-81919 3 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 11 0.08% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 12954 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 80893447336 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.689246 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.490660 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 80809388336 99.90% 99.90% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 57018000 0.07% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 12830500 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 5059000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 2818000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 1843000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 1116000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 1980000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 463500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 218500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-21 179500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::22-23 36500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-25 167500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::26-27 41000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-29 27000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::30-31 261000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 80893447336 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3543 69.38% 69.38% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1564 30.62% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5107 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 59132 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 58814 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5123 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 59132 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5107 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5123 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 63937 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5107 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 64239 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 13996599 # DTB read hits -system.cpu0.dtb.read_misses 49814 # DTB read misses -system.cpu0.dtb.write_hits 10431599 # DTB write hits -system.cpu0.dtb.write_misses 9000 # DTB write misses -system.cpu0.dtb.flush_tlb 179 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 456 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 13759363 # DTB read hits +system.cpu0.dtb.read_misses 49716 # DTB read misses +system.cpu0.dtb.write_hits 10256386 # DTB write hits +system.cpu0.dtb.write_misses 9416 # DTB write misses +system.cpu0.dtb.flush_tlb 182 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3299 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 781 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1241 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3461 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 822 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1317 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 730 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14046413 # DTB read accesses -system.cpu0.dtb.write_accesses 10440599 # DTB write accesses +system.cpu0.dtb.perms_faults 673 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 13809079 # DTB read accesses +system.cpu0.dtb.write_accesses 10265802 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24428198 # DTB hits -system.cpu0.dtb.misses 58814 # DTB misses -system.cpu0.dtb.accesses 24487012 # DTB accesses +system.cpu0.dtb.hits 24015749 # DTB hits +system.cpu0.dtb.misses 59132 # DTB misses +system.cpu0.dtb.accesses 24074881 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,798 +507,796 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 7918 # Table walker walks requested -system.cpu0.itb.walker.walksShort 7918 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2364 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 4650 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 904 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 7014 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1709.295694 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 7049.166862 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-8191 6549 93.37% 93.37% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-16383 244 3.48% 96.85% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-24575 111 1.58% 98.43% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-32767 40 0.57% 99.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-40959 16 0.23% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-49151 20 0.29% 99.52% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::49152-57343 6 0.09% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::57344-65535 11 0.16% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-73727 6 0.09% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::73728-81919 2 0.03% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::81920-90111 4 0.06% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::90112-98303 1 0.01% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-106495 3 0.04% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::114688-122879 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 7014 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3153 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12090.865842 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9887.284211 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7911.936320 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2500 79.29% 79.29% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 629 19.95% 99.24% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 19 0.60% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-65535 3 0.10% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::114688-131071 1 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3153 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 43016532284 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.690427 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.462733 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 13322631928 30.97% 30.97% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 29689752356 69.02% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 2941500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 833500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 255500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 93500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 24000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 43016532284 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1677 74.57% 74.57% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 572 25.43% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2249 # Table walker page sizes translated +system.cpu0.itb.walker.walks 7852 # Table walker walks requested +system.cpu0.itb.walker.walksShort 7852 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2338 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 4601 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 913 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 6939 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1482.922611 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 5881.501681 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-8191 6495 93.60% 93.60% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-16383 232 3.34% 96.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-24575 124 1.79% 98.73% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-32767 39 0.56% 99.29% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-40959 13 0.19% 99.48% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-49151 15 0.22% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::49152-57343 10 0.14% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::57344-65535 3 0.04% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-73727 4 0.06% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::73728-81919 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::81920-90111 2 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 6939 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3247 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12392.208192 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 10258.914411 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7404.792558 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 1195 36.80% 36.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1373 42.29% 79.09% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 618 19.03% 98.12% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 36 1.11% 99.23% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 12 0.37% 99.60% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 8 0.25% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.09% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 3247 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 29354741784 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.621127 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.485486 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 11126118428 37.90% 37.90% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 18225065856 62.09% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 2842500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 576000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 139000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 29354741784 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1743 74.68% 74.68% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 591 25.32% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2334 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7918 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7918 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7852 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7852 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2249 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2249 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 10167 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 20135553 # ITB inst hits -system.cpu0.itb.inst_misses 7918 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2334 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2334 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 10186 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 19905461 # ITB inst hits +system.cpu0.itb.inst_misses 7852 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 179 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 456 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 182 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2166 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2294 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1314 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1258 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 20143471 # ITB inst accesses -system.cpu0.itb.hits 20135553 # DTB hits -system.cpu0.itb.misses 7918 # DTB misses -system.cpu0.itb.accesses 20143471 # DTB accesses -system.cpu0.numCycles 111793147 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 19913313 # ITB inst accesses +system.cpu0.itb.hits 19905461 # DTB hits +system.cpu0.itb.misses 7852 # DTB misses +system.cpu0.itb.accesses 19913313 # DTB accesses +system.cpu0.numCycles 106457732 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 39618267 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 104005693 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 26582301 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19041464 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 66973533 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3106371 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 109142 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 4323 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 492 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 147946 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 134023 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 629 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 20133698 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 348335 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 4138 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 108541503 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.150586 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.270795 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 39778101 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 102329331 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 26563319 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19038002 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 62116027 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3105600 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 111146 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 3723 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 374 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 142117 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 123224 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 483 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 19903626 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 349456 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 4039 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 103827958 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.185750 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.289369 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 79990694 73.70% 73.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3816909 3.52% 77.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2386840 2.20% 79.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 8006128 7.38% 86.79% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1535692 1.41% 88.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 1070295 0.99% 89.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6024989 5.55% 94.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1046446 0.96% 95.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4663510 4.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 75543670 72.76% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3812816 3.67% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2351525 2.26% 78.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 7978907 7.68% 86.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1585659 1.53% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 993143 0.96% 88.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6063618 5.84% 94.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1017561 0.98% 95.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4481059 4.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 108541503 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.237781 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.930341 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 27078357 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 63118683 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15442618 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1487824 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1413697 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1876108 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 141386 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 86216951 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 468944 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1413697 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27917312 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6737317 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 45777609 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 16085983 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 10609270 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 82519213 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1975 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1079762 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 279653 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 8498365 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 84889546 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 380829987 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 92265906 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 6437 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 72096231 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12793299 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1560839 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1462535 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8709532 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 14755108 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11569793 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 2006584 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2797109 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 79506629 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1117012 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 76470203 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 91035 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10513087 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 23255127 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 107098 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 108541503 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.704525 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.408140 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 103827958 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.249520 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.961220 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 27448347 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58255743 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15281337 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1431455 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1410775 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1819074 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 143809 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 84464795 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 475260 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1410775 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 28253862 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6710507 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 43964237 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 15899574 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7588686 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 80835076 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 4210 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1036846 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 275223 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 5569610 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 83235701 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 372792978 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 90140763 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 7010 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 70379825 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12855876 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1526723 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1432794 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8313035 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 14557991 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11307773 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1955979 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2652434 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 77887971 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1057787 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 74749052 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 90659 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10605329 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 23154537 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 112514 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 103827958 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.719932 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.414021 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 78039194 71.90% 71.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10217369 9.41% 81.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7697876 7.09% 88.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6506516 5.99% 94.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2324489 2.14% 96.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1523922 1.40% 97.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1470166 1.35% 99.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 496796 0.46% 99.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 265175 0.24% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 73906108 71.18% 71.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10009384 9.64% 80.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7640879 7.36% 88.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6355260 6.12% 94.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2281294 2.20% 96.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1454406 1.40% 97.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1486828 1.43% 99.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 476436 0.46% 99.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 217363 0.21% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 108541503 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 103827958 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 114394 10.01% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 533468 46.67% 56.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 495163 43.32% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 96059 8.82% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 522555 47.96% 56.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 470896 43.22% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 1057 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 50961896 66.64% 66.64% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57056 0.07% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4042 0.01% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14381965 18.81% 85.53% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 11064184 14.47% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2193 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 49733964 66.53% 66.54% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57150 0.08% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4360 0.01% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14140204 18.92% 85.54% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 10811178 14.46% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 76470203 # Type of FU issued -system.cpu0.iq.rate 0.684033 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1143026 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014947 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 262701898 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 91181243 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 74205181 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 14072 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 8084 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 6077 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 77604626 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 7546 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 356476 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 74749052 # Type of FU issued +system.cpu0.iq.rate 0.702148 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1089511 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.014576 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 254491356 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 89595521 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 72529451 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 14876 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 8869 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 6537 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 75828364 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 8006 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 352891 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2025396 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2046 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 53693 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1019422 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2046517 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2081 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 54500 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1025754 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 206190 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 120975 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 203183 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 83677 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1413697 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5422271 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1092121 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 80743722 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 103923 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 14755108 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11569793 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 575298 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 45368 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1034932 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 53693 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 203963 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 218205 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 422168 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 75920997 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 14162652 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 490566 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1410775 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5864401 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 637976 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 79069756 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 107726 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 14557991 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11307773 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 551458 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 44492 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 582169 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 54500 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 204607 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 218688 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 423295 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 74201167 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 13921134 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 488864 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 120081 # number of nop insts executed -system.cpu0.iew.exec_refs 25131819 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14053120 # Number of branches executed -system.cpu0.iew.exec_stores 10969167 # Number of stores executed -system.cpu0.iew.exec_rate 0.679120 # Inst execution rate -system.cpu0.iew.wb_sent 75353130 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 74211258 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 38909862 # num instructions producing a value -system.cpu0.iew.wb_consumers 67987561 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.663827 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.572309 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 10505736 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1009914 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 355428 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 106122323 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.661384 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.563144 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 123998 # number of nop insts executed +system.cpu0.iew.exec_refs 24636404 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14031471 # Number of branches executed +system.cpu0.iew.exec_stores 10715270 # Number of stores executed +system.cpu0.iew.exec_rate 0.697001 # Inst execution rate +system.cpu0.iew.wb_sent 73687563 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 72535988 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 37714943 # num instructions producing a value +system.cpu0.iew.wb_consumers 65670191 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.681360 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.574308 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 10562082 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 945273 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 353712 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 101401285 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.674752 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.564672 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 78982453 74.43% 74.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12211696 11.51% 85.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6095376 5.74% 91.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2654698 2.50% 94.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1273985 1.20% 95.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 842007 0.79% 96.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1777365 1.67% 97.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 427049 0.40% 98.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1857694 1.75% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 74703088 73.67% 73.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12065534 11.90% 85.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6043146 5.96% 91.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2565114 2.53% 94.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1263406 1.25% 95.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 840623 0.83% 96.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1825870 1.80% 97.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 394429 0.39% 98.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1700075 1.68% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 106122323 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 57860770 # Number of instructions committed -system.cpu0.commit.committedOps 70187602 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 101401285 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 56174796 # Number of instructions committed +system.cpu0.commit.committedOps 68420730 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 23280083 # Number of memory references committed -system.cpu0.commit.loads 12729712 # Number of loads committed -system.cpu0.commit.membars 412824 # Number of memory barriers committed -system.cpu0.commit.branches 13343572 # Number of branches committed -system.cpu0.commit.fp_insts 5690 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 61639242 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2627168 # Number of function calls committed. +system.cpu0.commit.refs 22793493 # Number of memory references committed +system.cpu0.commit.loads 12511474 # Number of loads committed +system.cpu0.commit.membars 380410 # Number of memory barriers committed +system.cpu0.commit.branches 13308961 # Number of branches committed +system.cpu0.commit.fp_insts 6093 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 59905864 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2612225 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 46847826 66.75% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55651 0.08% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4042 0.01% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12729712 18.14% 84.97% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10550371 15.03% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 45567261 66.60% 66.60% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55619 0.08% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4357 0.01% 66.69% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.69% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.69% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.69% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12511474 18.29% 84.97% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10282019 15.03% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 70187602 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1857694 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 172582589 # The number of ROB reads -system.cpu0.rob.rob_writes 163805074 # The number of ROB writes -system.cpu0.timesIdled 387475 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3251644 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2095657765 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 57783718 # Number of Instructions Simulated -system.cpu0.committedOps 70110550 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.934682 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.934682 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.516881 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.516881 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 82769836 # number of integer regfile reads -system.cpu0.int_regfile_writes 47340037 # number of integer regfile writes -system.cpu0.fp_regfile_reads 16967 # number of floating regfile reads -system.cpu0.fp_regfile_writes 13430 # number of floating regfile writes -system.cpu0.cc_regfile_reads 268235222 # number of cc regfile reads -system.cpu0.cc_regfile_writes 27675650 # number of cc regfile writes -system.cpu0.misc_regfile_reads 149360983 # number of misc regfile reads -system.cpu0.misc_regfile_writes 774294 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 854223 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.975115 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42339802 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 854735 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.535589 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 151893500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 245.630516 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 266.344600 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.479747 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.520204 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999951 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 68420730 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1700075 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 166296825 # The number of ROB reads +system.cpu0.rob.rob_writes 160391499 # The number of ROB writes +system.cpu0.timesIdled 400345 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 2629774 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2956130676 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 56094495 # Number of Instructions Simulated +system.cpu0.committedOps 68340429 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.897829 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.897829 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.526918 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.526918 # 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Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.071418 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.913027 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.359514 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.640455 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189188933 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189188933 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 12328240 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 12835653 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25163893 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 7920383 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 7983564 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15903947 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 182811 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 180265 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 363076 # 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number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 125538249761 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 267118259846 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 12771140 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 13233311 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26004451 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9779670 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9819445 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19599115 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 299797 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 246750 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 546547 # 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number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 178403907084 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 93671976214 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 84731930870 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 178403907084 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 12632956 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 13368330 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 26001286 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9606512 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9991986 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19598498 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 257155 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 289787 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 546942 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 223711 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 250514 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 474225 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216369 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 243063 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 459432 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 22239468 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 23360316 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 45599784 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 22496623 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 23650103 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 46146726 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031611 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032402 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.032017 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.203375 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.174774 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.188793 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.308989 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.360589 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.336328 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061369 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056009 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058538 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000231 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000177 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000202 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.105806 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.093299 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.099398 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108128 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.096574 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.102207 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15007.860568 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15243.336119 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15130.381590 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44877.788374 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44738.946634 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44812.258557 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13092.614174 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14790.143254 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13950.612392 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20580 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 18337.209302 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 19543.010753 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39808.596475 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 38876.935427 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39360.604314 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 38508.251418 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37098.286928 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 37825.470462 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1131320 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 188861 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 53104 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 2863 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.303857 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 65.966119 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 702476 # number of writebacks +system.cpu0.dcache.writebacks::total 702476 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 189142 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 219525 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 408667 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1797272 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1603201 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 3400473 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9446 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 9040 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18486 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1986414 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1822726 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3809140 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1986414 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1822726 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3809140 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 210193 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 213631 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 423824 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 156452 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 143134 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 299586 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 55184 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 67813 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 122997 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4283 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4991 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9274 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 50 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 43 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 75 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 360471 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 365482 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 725953 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 434709 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 414147 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 848856 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14976 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16153 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15353 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 12235 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27588 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 30329 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 28388 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58717 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3376686000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 3344381500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6721067500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10980513336 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 10043251436 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 21023764772 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1117542000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 750771500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1868313500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 92062500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58470500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 150533000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 878500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 1831000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2709500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14357199336 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 13387632936 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 27744832272 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15474741336 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 14138404436 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 29613145772 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3016953500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3284093000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6301046500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3016953500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3284093000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6301046500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016480 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016324 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016401 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015338 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015221 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015279 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.247628 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.197224 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224872 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018887 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.018623 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018758 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000136 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000191 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000163 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015985 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015854 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015919 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019024 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017775 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018393 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16043.550150 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15481.814184 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15759.027175 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 73202.934220 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 67196.019296 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70204.882647 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15053.503597 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15427.339977 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15201.528848 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 20162.614980 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13516.065650 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16929.037337 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27453.125000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 42581.395349 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 36126.666667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 39828.999659 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36630.074630 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38218.496613 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35597.931803 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34138.613671 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34885.947407 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201452.557425 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203311.644896 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202417.247583 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 99474.216097 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 115685.958856 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107312.132772 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 1940234 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.477808 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 38724516 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1940746 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 19.953418 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 11116168500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 198.827128 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 312.650680 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.388334 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.610646 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998980 # Average percentage of cache occupancy +system.cpu0.dcache.StoreCondReq_mshr_misses::total 93 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 366645 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 356765 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 723410 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 421829 # 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number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10737930430 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 21813821802 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3308436000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2995791000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6304227000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3308436000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2995791000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6304227000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016638 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015980 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016300 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016286 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014325 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015286 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.214594 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.234010 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224881 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.019145 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019923 # 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average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16798.537367 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15028.682338 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19580 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 17337.209302 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18543.010753 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28093.476993 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27388.715065 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27745.908685 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26256.827700 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25290.830966 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25772.260629 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202177.707162 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202925.624873 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202532.431651 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 102368.142579 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 113511.329191 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107377.271721 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 1934770 # 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Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 42755477 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 42755477 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 19119275 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 19605241 # 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number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 19902954 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 20886296 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 40789250 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 19902954 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 20886296 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 40789250 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 19902954 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 20886296 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 40789250 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051919 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050259 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.051069 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051919 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050259 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.051069 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051919 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050259 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.051069 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13559.104271 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13595.692011 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13577.542028 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13559.104271 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13595.692011 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13577.542028 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13559.104271 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13595.692011 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13577.542028 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 12666 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 839 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 637 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.159714 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.883830 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1940234 # number of writebacks -system.cpu0.icache.writebacks::total 1940234 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 72829 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 76365 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 149194 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 72829 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 76365 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 149194 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 72829 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 76365 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 149194 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 940922 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 999962 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1940884 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 940922 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 999962 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1940884 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 940922 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 999962 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1940884 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1934770 # number of writebacks +system.cpu0.icache.writebacks::total 1934770 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 71468 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 76180 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 147648 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 71468 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 76180 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 147648 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 71468 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 76180 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 147648 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 961875 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 973547 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1935422 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 961875 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 973547 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1935422 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 961875 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 973547 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1935422 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 667 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 667 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 667 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 667 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12649517983 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 13451239983 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 26100757966 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12649517983 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 13451239983 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 26100757966 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12649517983 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 13451239983 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 26100757966 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 85612500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 85612500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 85612500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 85612500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.046735 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.048350 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047554 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.046735 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.048350 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.047554 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.046735 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.048350 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.047554 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13443.747710 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13451.751150 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13447.871159 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13443.747710 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13451.751150 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13447.871159 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13443.747710 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13451.751150 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13447.871159 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 128354.572714 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 128354.572714 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 128354.572714 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 128354.572714 # average overall mshr uncacheable latency -system.cpu1.branchPred.lookups 27807268 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14522614 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 521884 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 17250489 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 8558251 # Number of BTB hits +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12392823488 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12603228992 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 24996052480 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12392823488 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12603228992 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 24996052480 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12392823488 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12603228992 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 24996052480 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 53482500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 53482500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 53482500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 53482500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.048328 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046612 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047449 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.048328 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046612 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047449 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.048328 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046612 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047449 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12884.027018 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12945.681094 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12915.039965 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12884.027018 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12945.681094 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12915.039965 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12884.027018 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12945.681094 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12915.039965 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 80183.658171 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 80183.658171 # average overall mshr uncacheable latency +system.cpu1.branchPred.lookups 27800734 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14468017 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 520264 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17357855 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 8537221 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 49.611643 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6837595 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 30253 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 4638011 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 4524834 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 113177 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 32246 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 49.183617 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6851276 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 30109 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 4615749 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 4505317 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 110432 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 32773 # Number of mispredicted indirect branches. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1328,88 +1326,91 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 59403 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 59403 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19503 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 14179 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 25721 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 33682 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 625.541832 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 4121.027251 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-16383 33293 98.85% 98.85% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-32767 302 0.90% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-49151 51 0.15% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-65535 17 0.05% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-81919 10 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::81920-98303 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-114687 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::114688-131071 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::147456-163839 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 33682 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 13282 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 14572.202981 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 12211.597102 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 8282.780589 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 9027 67.96% 67.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 3941 29.67% 97.64% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 289 2.18% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 20 0.15% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-98303 1 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-114687 2 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 13282 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 93940791836 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.786357 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.432735 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 93856164336 99.91% 99.91% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 59118500 0.06% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 13540500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 4598500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 2377500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 1150500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 641500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 2158000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 464500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 154000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-21 113500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::22-23 32000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-25 104000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::26-27 24000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-29 20500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::30-31 130000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 93940791836 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3783 68.79% 68.79% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1716 31.21% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5499 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 59403 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 58704 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 58704 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18787 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 14342 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 25575 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 33129 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 607.488907 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3928.944060 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-16383 32763 98.90% 98.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-32767 284 0.86% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-49151 53 0.16% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-65535 14 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-81919 9 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::81920-98303 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-114687 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::114688-131071 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::147456-163839 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 33129 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 12929 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 13107.123521 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10856.290186 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7818.028410 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 3814 29.50% 29.50% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 6003 46.43% 75.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 2605 20.15% 96.08% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 277 2.14% 98.22% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 121 0.94% 99.16% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 97 0.75% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 6 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-73727 2 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 2 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 12929 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 90162765428 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.682767 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.486580 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 90084509428 99.91% 99.91% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 54607500 0.06% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 11537000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 4308000 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 2626500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 1272000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 860000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 1827500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 362000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 169500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-21 127500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::22-23 189000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-25 278500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::26-27 31000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-29 4000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::30-31 56000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 90162765428 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3736 69.71% 69.71% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1623 30.29% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5359 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58704 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 59403 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5499 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58704 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5359 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5499 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 64902 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5359 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 64063 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14363291 # DTB read hits -system.cpu1.dtb.read_misses 51304 # DTB read misses -system.cpu1.dtb.write_hits 10466548 # DTB write hits -system.cpu1.dtb.write_misses 8099 # DTB write misses -system.cpu1.dtb.flush_tlb 185 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 461 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 14569453 # DTB read hits +system.cpu1.dtb.read_misses 50573 # DTB read misses +system.cpu1.dtb.write_hits 10639861 # DTB write hits +system.cpu1.dtb.write_misses 8131 # DTB write misses +system.cpu1.dtb.flush_tlb 176 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 472 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3703 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 789 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1302 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 3396 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 805 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1145 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 692 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14414595 # DTB read accesses -system.cpu1.dtb.write_accesses 10474647 # DTB write accesses +system.cpu1.dtb.perms_faults 620 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14620026 # DTB read accesses +system.cpu1.dtb.write_accesses 10647992 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 24829839 # DTB hits -system.cpu1.dtb.misses 59403 # DTB misses -system.cpu1.dtb.accesses 24889242 # DTB accesses +system.cpu1.dtb.hits 25209314 # DTB hits +system.cpu1.dtb.misses 58704 # DTB misses +system.cpu1.dtb.accesses 25268018 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1439,387 +1440,380 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 8176 # Table walker walks requested -system.cpu1.itb.walker.walksShort 8176 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2725 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4550 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 901 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 7275 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1291.065292 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 5441.618044 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-8191 6876 94.52% 94.52% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-16383 235 3.23% 97.75% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-24575 98 1.35% 99.09% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-32767 22 0.30% 99.40% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-40959 16 0.22% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::40960-49151 13 0.18% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::49152-57343 4 0.05% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-73727 4 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::73728-81919 3 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::81920-90111 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::90112-98303 2 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 7275 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 3329 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 13317.062181 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11226.218881 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7219.287794 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 33 0.99% 0.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 951 28.57% 29.56% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 591 17.75% 47.31% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 974 29.26% 76.57% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 56 1.68% 78.25% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 639 19.19% 97.45% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 50 1.50% 98.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.21% 99.16% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 8 0.24% 99.40% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 9 0.27% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 7 0.21% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 3329 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 16626242508 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.560807 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.496851 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 7305801500 43.94% 43.94% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 9317469508 56.04% 99.98% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 2523000 0.02% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 191000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 257500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 16626242508 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1825 75.16% 75.16% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 603 24.84% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2428 # Table walker page sizes translated +system.cpu1.itb.walker.walks 7547 # Table walker walks requested +system.cpu1.itb.walker.walksShort 7547 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2262 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4445 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 840 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 6707 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1590.577009 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 7723.778790 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-16383 6530 97.36% 97.36% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-32767 110 1.64% 99.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-49151 34 0.51% 99.51% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::49152-65535 14 0.21% 99.72% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-81919 4 0.06% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::81920-98303 4 0.06% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-114687 4 0.06% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::114688-131071 3 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-147455 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::147456-163839 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-180223 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 6707 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 3150 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12187.460317 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9947.804489 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 8166.759001 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-16383 2468 78.35% 78.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-32767 654 20.76% 99.11% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-49151 23 0.73% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-65535 4 0.13% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::180224-196607 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 3150 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 25738120488 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.844814 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.363091 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 3999711376 15.54% 15.54% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 21735062612 84.45% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 2190000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 624000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 246500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 151000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::6 78500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::7 56500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 25738120488 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1735 75.11% 75.11% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 575 24.89% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2310 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 8176 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 8176 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7547 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7547 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2428 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2428 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 10604 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 20684254 # ITB inst hits -system.cpu1.itb.inst_misses 8176 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2310 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2310 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 9857 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 20888873 # ITB inst hits +system.cpu1.itb.inst_misses 7547 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 185 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 461 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 176 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 472 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2403 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2235 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1403 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1381 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20692430 # ITB inst accesses -system.cpu1.itb.hits 20684254 # DTB hits -system.cpu1.itb.misses 8176 # DTB misses -system.cpu1.itb.accesses 20692430 # DTB accesses -system.cpu1.numCycles 114171883 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 20896420 # ITB inst accesses +system.cpu1.itb.hits 20888873 # DTB hits +system.cpu1.itb.misses 7547 # DTB misses +system.cpu1.itb.accesses 20896420 # DTB accesses +system.cpu1.numCycles 109807766 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 41307055 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 106903297 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27807268 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19920680 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 67458241 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3216021 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 121509 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 7142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 400 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 160606 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 131997 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 578 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20681575 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 364929 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 4168 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 110795501 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.160287 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.270583 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 40946708 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 108526504 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27800734 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19893814 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 64236038 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3213549 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 105759 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 7245 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 373 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 135453 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 122613 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 242 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20886297 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 363278 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3848 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 107161169 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.215637 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.316725 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 81287702 73.37% 73.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3968445 3.58% 76.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2465737 2.23% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8227247 7.43% 86.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1665467 1.50% 88.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1110283 1.00% 89.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6325144 5.71% 94.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1155008 1.04% 95.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4590468 4.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 77416464 72.24% 72.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3965095 3.70% 75.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2490829 2.32% 78.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8243361 7.69% 85.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1613956 1.51% 87.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1187147 1.11% 88.57% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6283757 5.86% 94.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1186298 1.11% 95.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4774262 4.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 110795501 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.243556 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.936336 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 28346426 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 63534954 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15742282 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1712283 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1459261 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1949115 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 150539 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 88605226 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 497888 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1459261 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 29272328 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 6824679 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 46697941 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16517482 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 10023500 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 84831585 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 5826 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1700956 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 268416 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 7295598 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 88095005 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 390290446 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 94261831 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6556 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 74597964 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13497041 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1571787 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1475121 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 9868182 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15213702 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11513965 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2143340 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2824110 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 81772790 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1092881 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 78357937 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 92895 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 11062256 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24614502 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 108703 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 110795501 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.707230 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.397571 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 107161169 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.253176 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.988332 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27964353 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 60068615 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15897753 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1769475 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1460665 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 2003148 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 148026 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 90335872 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 490325 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1460665 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28918939 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 5241732 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 47181148 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16705614 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 7652719 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 86492691 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2006 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1748729 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 211009 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 4894541 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 89713841 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 398200824 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 96380963 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6166 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 76287775 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13426050 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1604503 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1503333 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 10223805 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15401006 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11773081 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2213053 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2955194 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 83360447 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1152123 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 80030097 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 91651 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10961230 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 24701225 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 103564 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 107161169 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.746820 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.429737 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 79253115 71.53% 71.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10577284 9.55% 81.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8128095 7.34% 88.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6656902 6.01% 94.42% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2466913 2.23% 96.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1485866 1.34% 97.99% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1541530 1.39% 99.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 478773 0.43% 99.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 207023 0.19% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 74988145 69.98% 69.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10859318 10.13% 80.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8183119 7.64% 87.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6800302 6.35% 94.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2507101 2.34% 96.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1554442 1.45% 97.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1528270 1.43% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 490375 0.46% 99.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 250097 0.23% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 110795501 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 107161169 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 96333 8.58% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 5 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 530832 47.29% 55.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 495255 44.12% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 115126 9.98% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 7 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 527227 45.72% 55.70% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 510910 44.30% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 1280 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 52536411 67.05% 67.05% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59049 0.08% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4537 0.01% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14749265 18.82% 85.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11007390 14.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 144 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 53746905 67.16% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59075 0.07% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 3 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 3 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4215 0.01% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14959094 18.69% 85.93% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11260652 14.07% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 78357937 # Type of FU issued -system.cpu1.iq.rate 0.686316 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1122425 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014324 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 268712676 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 93970035 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 76074139 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14019 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8104 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6058 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 79471535 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7547 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 353893 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 80030097 # Type of FU issued +system.cpu1.iq.rate 0.728820 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1153270 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014410 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 268452912 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 95516318 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 77725340 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 13372 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7575 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5790 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 81175982 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7241 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 353102 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2138712 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2178 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 51387 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1026051 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2112683 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1972 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 51148 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1017197 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 208095 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 80598 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 193348 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 111717 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1459261 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 5474450 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1047007 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 82982431 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 112348 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15213702 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11513965 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 559325 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 44311 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 989592 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 51387 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 224281 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 227429 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 451710 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 77795994 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14521150 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 502664 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1460665 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4238159 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 750598 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 84630100 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 109084 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15401006 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11773081 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 582386 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 44757 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 693078 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 51148 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 222492 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 227539 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 450031 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 79465930 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14732483 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 505630 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 116760 # number of nop insts executed -system.cpu1.iew.exec_refs 25431924 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14791580 # Number of branches executed -system.cpu1.iew.exec_stores 10910774 # Number of stores executed -system.cpu1.iew.exec_rate 0.681394 # Inst execution rate -system.cpu1.iew.wb_sent 77262283 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 76080197 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 39863669 # num instructions producing a value -system.cpu1.iew.wb_consumers 69476168 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.666365 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.573775 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 11052926 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 984178 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 373097 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 108271763 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.663897 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.547392 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 117530 # number of nop insts executed +system.cpu1.iew.exec_refs 25895547 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14804111 # Number of branches executed +system.cpu1.iew.exec_stores 11163064 # Number of stores executed +system.cpu1.iew.exec_rate 0.723682 # Inst execution rate +system.cpu1.iew.wb_sent 78901102 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 77731130 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 41032213 # num instructions producing a value +system.cpu1.iew.wb_consumers 71725825 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.707884 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.572070 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 10989958 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1048559 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 374118 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 104645735 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.703573 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.592319 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 80200179 74.07% 74.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12516978 11.56% 85.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6520368 6.02% 91.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2652401 2.45% 94.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1417496 1.31% 95.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 923552 0.85% 96.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1918077 1.77% 98.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 411551 0.38% 98.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1711161 1.58% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 76040779 72.66% 72.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12759216 12.19% 84.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6569138 6.28% 91.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2748147 2.63% 93.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1448865 1.38% 95.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 932135 0.89% 96.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1856823 1.77% 97.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 438122 0.42% 98.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1852510 1.77% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 108271763 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 59217112 # Number of instructions committed -system.cpu1.commit.committedOps 71881268 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 104645735 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 60885928 # Number of instructions committed +system.cpu1.commit.committedOps 73625940 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 23562904 # Number of memory references committed -system.cpu1.commit.loads 13074990 # Number of loads committed -system.cpu1.commit.membars 401228 # Number of memory barriers committed -system.cpu1.commit.branches 14038691 # Number of branches committed -system.cpu1.commit.fp_insts 5738 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 62807538 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2710976 # Number of function calls committed. +system.cpu1.commit.refs 24044207 # Number of memory references committed +system.cpu1.commit.loads 13288323 # Number of loads committed +system.cpu1.commit.membars 433821 # Number of memory barriers committed +system.cpu1.commit.branches 14065730 # Number of branches committed +system.cpu1.commit.fp_insts 5335 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 64521424 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2723504 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 48256450 67.13% 67.13% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 57377 0.08% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4537 0.01% 67.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.22% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 13074990 18.19% 85.41% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10487914 14.59% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 49520111 67.26% 67.26% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 57410 0.08% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4212 0.01% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 13288323 18.05% 85.39% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10755884 14.61% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 71881268 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1711161 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 176735150 # The number of ROB reads -system.cpu1.rob.rob_writes 168391360 # The number of ROB writes -system.cpu1.timesIdled 416029 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 3376382 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3313480178 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 59139259 # Number of Instructions Simulated -system.cpu1.committedOps 71803415 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.930560 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.930560 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.517984 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.517984 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 84439414 # number of integer regfile reads -system.cpu1.int_regfile_writes 48406893 # number of integer regfile writes -system.cpu1.fp_regfile_reads 17104 # number of floating regfile reads -system.cpu1.fp_regfile_writes 13298 # number of floating regfile writes -system.cpu1.cc_regfile_reads 275043982 # number of cc regfile reads -system.cpu1.cc_regfile_writes 29275058 # number of cc regfile writes -system.cpu1.misc_regfile_reads 152546731 # number of misc regfile reads -system.cpu1.misc_regfile_writes 745677 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 30182 # Transaction distribution -system.iobus.trans_dist::ReadResp 30182 # Transaction distribution +system.cpu1.commit.op_class_0::total 73625940 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1852510 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 174677688 # The number of ROB reads +system.cpu1.rob.rob_writes 171746746 # The number of ROB writes +system.cpu1.timesIdled 397244 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2646597 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2436737930 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 60811324 # Number of Instructions Simulated +system.cpu1.committedOps 73551336 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.805712 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.805712 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.553798 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.553798 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 86399425 # number of integer regfile reads +system.cpu1.int_regfile_writes 49556939 # number of integer regfile writes +system.cpu1.fp_regfile_reads 16634 # number of floating regfile reads +system.cpu1.fp_regfile_writes 13036 # number of floating regfile writes +system.cpu1.cc_regfile_reads 280643076 # number of cc regfile reads +system.cpu1.cc_regfile_writes 29716175 # number of cc regfile writes +system.cpu1.misc_regfile_reads 149728966 # number of misc regfile reads +system.cpu1.misc_regfile_writes 794523 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30198 # Transaction distribution +system.iobus.trans_dist::ReadResp 30198 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1842,9 +1836,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -1865,36 +1859,36 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 49489000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 49488500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 335500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 336500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 88500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 612500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 631000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 49000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) @@ -1902,612 +1896,624 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6433500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6430000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38433500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38405500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187130237 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187814627 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36423 # number of replacements -system.iocache.tags.tagsinuse 1.038891 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 236424190000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.038891 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064931 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064931 # Average percentage of cache occupancy +system.iocache.tags.replacements 36409 # number of replacements +system.iocache.tags.tagsinuse 0.981814 # Cycle average of tags in use +system.iocache.tags.total_refs 30 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 234298498000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.981814 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.061363 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.061363 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328113 # Number of tag accesses -system.iocache.tags.data_accesses 328113 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses -system.iocache.ReadReq_misses::total 233 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36457 # number of demand (read+write) misses -system.iocache.demand_misses::total 36457 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36457 # number of overall misses -system.iocache.overall_misses::total 36457 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 30201377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 30201377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4553154860 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4553154860 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4583356237 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4583356237 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4583356237 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4583356237 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) +system.iocache.tags.tag_accesses 328227 # Number of tag accesses +system.iocache.tags.data_accesses 328227 # Number of data accesses +system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits +system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits +system.iocache.demand_hits::realview.ide 29 # number of demand (read+write) hits +system.iocache.demand_hits::total 29 # number of demand (read+write) hits +system.iocache.overall_hits::realview.ide 29 # number of overall hits +system.iocache.overall_hits::total 29 # number of overall hits +system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses +system.iocache.ReadReq_misses::total 249 # number of ReadReq misses +system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses +system.iocache.demand_misses::realview.ide 36444 # number of demand (read+write) misses +system.iocache.demand_misses::total 36444 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36444 # number of overall misses +system.iocache.overall_misses::total 36444 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31228377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31228377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4281194250 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4281194250 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4312422627 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4312422627 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4312422627 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4312422627 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36457 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36457 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36457 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36457 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36473 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36473 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36473 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36473 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129619.643777 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129619.643777 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125694.425243 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125694.425243 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125719.511671 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125719.511671 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125719.511671 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125719.511671 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses +system.iocache.demand_miss_rate::realview.ide 0.999205 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 0.999205 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 0.999205 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 0.999205 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ide 125415.168675 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125415.168675 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118281.371736 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118281.371736 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118330.112693 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118330.112693 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118330.112693 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118330.112693 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 93 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 93 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # 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Sample count of references to valid blocks. -system.l2c.tags.avg_refs 30.384251 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 74565493500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48889.400560 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 39.621431 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000315 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5209.577965 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3051.295581 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 57.223536 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5380.787536 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2475.798353 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.745993 # 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Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046559 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000873 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.082104 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.037778 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993404 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 95 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65103 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 95 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3204 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8943 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52585 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.001450 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.993393 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45530803 # Number of tag accesses -system.l2c.tags.data_accesses 45530803 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 34635 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6743 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 37358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7553 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86289 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 704221 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 704221 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1901578 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1901578 # 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Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65177 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 78 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3224 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8984 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52582 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.001190 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994522 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 45398834 # Number of tag accesses +system.l2c.tags.data_accesses 45398834 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 35730 # 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number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 82259 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 74230 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 156489 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 951585 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 962532 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1914117 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 262545 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 278213 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 540758 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 35730 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 6852 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 951585 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 344804 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 36375 # 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mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.959410 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.953594 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.320000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.186047 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.258065 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.469139 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.476498 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.472655 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.010459 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011113 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010788 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.026064 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.028420 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.027277 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001732 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000146 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010459 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.187760 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001839 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011113 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.176792 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.061402 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001732 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000146 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010459 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.187760 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001839 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011113 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.176792 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.061402 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 82887.096774 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75507.462687 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 79011.538462 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19040.474529 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19030 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19035.492133 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 22500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 26062.500000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23687.500000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74604.787124 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73399.763191 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 74024.311992 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72750.248360 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 74031.663215 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73414.251449 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77325.128201 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80252.764128 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78896.261933 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82887.096774 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72750.248360 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74844.599438 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75507.462687 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74031.663215 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74136.615811 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 74374.649300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82887.096774 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72750.248360 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74844.599438 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75507.462687 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74031.663215 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74136.615811 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 74374.649300 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189674.040577 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190422.034817 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 187397.936655 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96037.191745 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 106517.145347 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 100342.382667 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 356405 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 150205 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 31794 # Transaction distribution +system.membus.trans_dist::ReadResp 68215 # Transaction distribution +system.membus.trans_dist::WriteReq 27584 # Transaction distribution +system.membus.trans_dist::WriteResp 27584 # Transaction distribution +system.membus.trans_dist::WritebackDirty 131465 # Transaction distribution +system.membus.trans_dist::CleanEvict 9298 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4631 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 24 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 137965 # Transaction distribution -system.membus.trans_dist::ReadExResp 137965 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 36388 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::ReadExReq 138363 # Transaction distribution +system.membus.trans_dist::ReadExResp 138363 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 36422 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 24 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2082 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 468158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 575742 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72895 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72895 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 648637 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 468976 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 576548 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649416 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4164 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17317788 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17481845 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19798965 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 501 # Total snoops (count) -system.membus.snoop_fanout::samples 415426 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17313116 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17477149 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19792349 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 523 # Total snoops (count) +system.membus.snoop_fanout::samples 275014 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019224 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.137313 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 415426 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 269727 98.08% 98.08% # Request fanout histogram +system.membus.snoop_fanout::1 5287 1.92% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 415426 # Request fanout histogram -system.membus.reqLayer0.occupancy 95665000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 275014 # Request fanout histogram +system.membus.reqLayer0.occupancy 95656500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1698498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1704498 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 923038607 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 922039711 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1006596250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1008874750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1263123 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1321623 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2550,63 +2556,63 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5631885 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2836272 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 46849 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 558 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 558 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5615551 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2827345 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 47668 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 189 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 150344 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2649691 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27588 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27588 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 836223 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1940234 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 158771 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2995 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 75 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 3070 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296500 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296500 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1940884 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 558486 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5822943 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2687514 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37786 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 167187 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8715430 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 248409088 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99970933 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 57188 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 288512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 348725721 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 209954 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3153965 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.027355 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.163116 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 149135 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2640787 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 797781 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1934770 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 158854 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2867 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 93 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2959 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296749 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296749 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1935422 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 556302 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4761 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5806529 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2681416 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 36041 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 166883 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8690869 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 247708160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99732253 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 53396 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 288936 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 347782745 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 141693 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3081386 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.027688 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.164077 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 3067688 97.26% 97.26% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 86277 2.74% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2996069 97.23% 97.23% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 85317 2.77% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3153965 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5543895402 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3081386 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5532635383 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 377377 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 308377 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2914118404 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2905951347 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1329027112 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1326155926 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23521931 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 22725930 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 95501099 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 95104578 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3037 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 3038 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 7463dd4c7..3e87001d4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.535940 # Number of seconds simulated -sim_ticks 47535940136000 # Number of ticks simulated -final_tick 47535940136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.355903 # Number of seconds simulated +sim_ticks 47355903328000 # Number of ticks simulated +final_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 200561 # Simulator instruction rate (inst/s) -host_op_rate 235891 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10615931561 # Simulator tick rate (ticks/s) -host_mem_usage 769436 # Number of bytes of host memory used -host_seconds 4477.79 # Real time elapsed on the host -sim_insts 898069628 # Number of instructions simulated -sim_ops 1056270581 # Number of ops (including micro ops) simulated +host_inst_rate 234942 # Simulator instruction rate (inst/s) +host_op_rate 276333 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12593783431 # Simulator tick rate (ticks/s) +host_mem_usage 765460 # Number of bytes of host memory used +host_seconds 3760.26 # Real time elapsed on the host +sim_insts 883443630 # Number of instructions simulated +sim_ops 1039082168 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 89728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 8161024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 14243656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 14782784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 150400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 127744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3048640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9523856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 12507584 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 413056 # Number of bytes read from this memory -system.physmem.bytes_read::total 63147416 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 8161024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3048640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11209664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75703424 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 131584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 123776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7567040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 14160840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 16409728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 122112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 100992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3330560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9705936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 10452736 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 444224 # Number of bytes read from this memory +system.physmem.bytes_read::total 62549528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7567040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3330560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10897600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75633728 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 75724008 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1546 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1402 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 127516 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 222570 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 230981 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2350 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1996 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 47635 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 148823 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 195431 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6454 # Number of read requests responded to by this memory -system.physmem.num_reads::total 986704 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1182866 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 75654312 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2056 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1934 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 118235 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 221276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 256402 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1908 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1578 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 52040 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 151668 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 163324 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6941 # Number of read requests responded to by this memory +system.physmem.num_reads::total 977362 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1181777 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1185440 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1888 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 171681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 299640 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 310981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 64133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 200351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 263118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8689 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1328414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 171681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 64133 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 235815 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1592551 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1184351 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 159791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 299030 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 346519 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2579 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 70330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 204957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 220727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1320839 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 159791 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 70330 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 230121 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1597134 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1592984 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1592551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2081 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 171681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 300073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 310981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 64133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 200351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 263118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8689 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2921398 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 986704 # Number of read requests accepted -system.physmem.writeReqs 1185440 # Number of write requests accepted -system.physmem.readBursts 986704 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1185440 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 63115328 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 33728 # Total number of bytes read from write queue -system.physmem.bytesWritten 75722560 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 63147416 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 75724008 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 527 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2258 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1597569 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1597134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 159791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 299465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 346519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 70330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 204957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 220727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2918408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 977362 # Number of read requests accepted +system.physmem.writeReqs 1184351 # Number of write requests accepted +system.physmem.readBursts 977362 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1184351 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 62527296 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 23872 # Total number of bytes read from write queue +system.physmem.bytesWritten 75653504 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62549528 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 75654312 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 373 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 63842 # Per bank write bursts -system.physmem.perBankRdBursts::1 66317 # Per bank write bursts -system.physmem.perBankRdBursts::2 58522 # Per bank write bursts -system.physmem.perBankRdBursts::3 64863 # Per bank write bursts -system.physmem.perBankRdBursts::4 59095 # Per bank write bursts -system.physmem.perBankRdBursts::5 67998 # Per bank write bursts -system.physmem.perBankRdBursts::6 58322 # Per bank write bursts -system.physmem.perBankRdBursts::7 56006 # Per bank write bursts -system.physmem.perBankRdBursts::8 52486 # Per bank write bursts -system.physmem.perBankRdBursts::9 111449 # Per bank write bursts -system.physmem.perBankRdBursts::10 50777 # Per bank write bursts -system.physmem.perBankRdBursts::11 58061 # Per bank write bursts -system.physmem.perBankRdBursts::12 51458 # Per bank write bursts -system.physmem.perBankRdBursts::13 52890 # Per bank write bursts -system.physmem.perBankRdBursts::14 54883 # Per bank write bursts -system.physmem.perBankRdBursts::15 59208 # Per bank write bursts -system.physmem.perBankWrBursts::0 77123 # Per bank write bursts -system.physmem.perBankWrBursts::1 81948 # Per bank write bursts -system.physmem.perBankWrBursts::2 74623 # Per bank write bursts -system.physmem.perBankWrBursts::3 80009 # Per bank write bursts -system.physmem.perBankWrBursts::4 75007 # Per bank write bursts -system.physmem.perBankWrBursts::5 80611 # Per bank write bursts -system.physmem.perBankWrBursts::6 72005 # Per bank write bursts -system.physmem.perBankWrBursts::7 72012 # Per bank write bursts -system.physmem.perBankWrBursts::8 68266 # Per bank write bursts -system.physmem.perBankWrBursts::9 73887 # Per bank write bursts -system.physmem.perBankWrBursts::10 67546 # Per bank write bursts -system.physmem.perBankWrBursts::11 72517 # Per bank write bursts -system.physmem.perBankWrBursts::12 68786 # Per bank write bursts -system.physmem.perBankWrBursts::13 69993 # Per bank write bursts -system.physmem.perBankWrBursts::14 72865 # Per bank write bursts -system.physmem.perBankWrBursts::15 75967 # Per bank write bursts +system.physmem.perBankRdBursts::0 54912 # Per bank write bursts +system.physmem.perBankRdBursts::1 56908 # Per bank write bursts +system.physmem.perBankRdBursts::2 51582 # Per bank write bursts +system.physmem.perBankRdBursts::3 63469 # Per bank write bursts +system.physmem.perBankRdBursts::4 61411 # Per bank write bursts +system.physmem.perBankRdBursts::5 61841 # Per bank write bursts +system.physmem.perBankRdBursts::6 57272 # Per bank write bursts +system.physmem.perBankRdBursts::7 62841 # Per bank write bursts +system.physmem.perBankRdBursts::8 51834 # Per bank write bursts +system.physmem.perBankRdBursts::9 112088 # Per bank write bursts +system.physmem.perBankRdBursts::10 55237 # Per bank write bursts +system.physmem.perBankRdBursts::11 58857 # Per bank write bursts +system.physmem.perBankRdBursts::12 56745 # Per bank write bursts +system.physmem.perBankRdBursts::13 58205 # Per bank write bursts +system.physmem.perBankRdBursts::14 53859 # Per bank write bursts +system.physmem.perBankRdBursts::15 59928 # Per bank write bursts +system.physmem.perBankWrBursts::0 69820 # Per bank write bursts +system.physmem.perBankWrBursts::1 73385 # Per bank write bursts +system.physmem.perBankWrBursts::2 70846 # Per bank write bursts +system.physmem.perBankWrBursts::3 76844 # Per bank write bursts +system.physmem.perBankWrBursts::4 76655 # Per bank write bursts +system.physmem.perBankWrBursts::5 78828 # Per bank write bursts +system.physmem.perBankWrBursts::6 72793 # Per bank write bursts +system.physmem.perBankWrBursts::7 76848 # Per bank write bursts +system.physmem.perBankWrBursts::8 69899 # Per bank write bursts +system.physmem.perBankWrBursts::9 74878 # Per bank write bursts +system.physmem.perBankWrBursts::10 69893 # Per bank write bursts +system.physmem.perBankWrBursts::11 73658 # Per bank write bursts +system.physmem.perBankWrBursts::12 73258 # Per bank write bursts +system.physmem.perBankWrBursts::13 76164 # Per bank write bursts +system.physmem.perBankWrBursts::14 72361 # Per bank write bursts +system.physmem.perBankWrBursts::15 75956 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 44 # Number of times write queue was full causing retry -system.physmem.totGap 47535938023500 # Total gap between requests +system.physmem.numWrRetry 28 # Number of times write queue was full causing retry +system.physmem.totGap 47355901307500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 986674 # Read request sizes (log2) +system.physmem.readPktSize::6 977332 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1182866 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 668450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 115815 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 26396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 23877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 21311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1181777 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 653624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 118392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33441 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 28719 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 26608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 24389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 21172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 19081 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 791 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 539 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,166 +188,174 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 37996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 51637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 64761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 68893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 71932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 72504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 73761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 76926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 74288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 75236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 82718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 73770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 68266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 65794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 26534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 34947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 50320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 57992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 63163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 65860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 68534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 70437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 72935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 73131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 75636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 78760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 75174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 74381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 78953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 69890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 64098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 147 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 135 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 984595 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 141.009629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 96.339121 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 189.114371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 670707 68.12% 68.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 190612 19.36% 87.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44448 4.51% 91.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20648 2.10% 94.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14900 1.51% 95.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9763 0.99% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5507 0.56% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4424 0.45% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23586 2.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 984595 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61315 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.083617 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 159.391032 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61313 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 102 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 973522 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 141.938602 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 96.538228 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 191.263762 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 662821 68.08% 68.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 188353 19.35% 87.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 43865 4.51% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 19742 2.03% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14303 1.47% 95.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9443 0.97% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6391 0.66% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5216 0.54% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23388 2.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 973522 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 57494 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.992747 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 164.605284 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 57491 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61315 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61315 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.296502 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.510563 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.190386 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 48917 79.78% 79.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 5503 8.97% 88.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 3053 4.98% 93.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1653 2.70% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 478 0.78% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 276 0.45% 97.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 266 0.43% 98.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 90 0.15% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 261 0.43% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 71 0.12% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 38 0.06% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 55 0.09% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 246 0.40% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 32 0.05% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 47 0.08% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 108 0.18% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 156 0.25% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 24 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 11 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 57494 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 57494 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.560163 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.793170 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.728131 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 49230 85.63% 85.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2347 4.08% 89.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 805 1.40% 91.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 601 1.05% 92.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 998 1.74% 93.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 486 0.85% 94.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 329 0.57% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 263 0.46% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 216 0.38% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 180 0.31% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 129 0.22% 96.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 154 0.27% 96.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 478 0.83% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 131 0.23% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 143 0.25% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 111 0.19% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 107 0.19% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 71 0.12% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 85 0.15% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 71 0.12% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 101 0.18% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 73 0.13% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 62 0.11% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 52 0.09% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 38 0.07% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 47 0.08% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 26 0.05% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 37 0.06% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 49 0.09% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 22 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 8 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 12 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 6 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 8 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61315 # Writes before turning the bus around for reads -system.physmem.totQLat 31916274746 # Total ticks spent queuing -system.physmem.totMemAccLat 50407093496 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4930885000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32363.64 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 3 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::236-239 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 57494 # Writes before turning the bus around for reads +system.physmem.totQLat 32578317305 # Total ticks spent queuing +system.physmem.totMemAccLat 50896861055 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4884945000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33345.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51113.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.33 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.33 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52095.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.32 # Average write queue length when enqueuing -system.physmem.readRowHits 734466 # Number of row buffer hits during reads -system.physmem.writeRowHits 450279 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.06 # Row buffer hit rate for writes -system.physmem.avgGap 21884340.09 # Average gap between requests -system.physmem.pageHitRate 54.61 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3920933520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2139398250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3860672400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3974430240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3104816267280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1203845511330 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27465556979250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31788114192270 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.717535 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45690953287273 # Time in different power states -system.physmem_0.memoryStateTime::REF 1587329380000 # Time in different power states +system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing +system.physmem.readRowHits 734277 # Number of row buffer hits during reads +system.physmem.writeRowHits 451275 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.18 # Row buffer hit rate for writes +system.physmem.avgGap 21906655.19 # Average gap between requests +system.physmem.pageHitRate 54.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3752269920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2047369500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3667786200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3862203120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1180767055500 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27377781027000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31664935054200 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.658673 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45545161867023 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581317660000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 257656491727 # Time in different power states +system.physmem_0.memoryStateTime::ACT 229423166977 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3522604680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1922056125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3831445800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3692478960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3104816267280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1196085851100 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27472363698750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31786234402695 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.677991 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45702273449121 # Time in different power states -system.physmem_1.memoryStateTime::REF 1587329380000 # Time in different power states +system.physmem_1.actEnergy 3607556400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1968408750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3952673400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3797714160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1177905490200 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27380291180250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31664580366120 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.651183 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45549316476567 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581317660000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 246336261879 # Time in different power states +system.physmem_1.memoryStateTime::ACT 225268560933 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -378,22 +386,22 @@ system.realview.nvmem.bw_total::total 28 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1674 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 146462396 # Number of BP lookups -system.cpu0.branchPred.condPredicted 102364881 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6839955 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 108739004 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75372629 # Number of BTB hits +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. +system.cpu0.branchPred.lookups 145452632 # Number of BP lookups +system.cpu0.branchPred.condPredicted 102233764 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6537956 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 107843095 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 75495824 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 69.315173 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17612403 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1195732 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 3915449 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2665463 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1249986 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 447212 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 70.005246 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17327542 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1162135 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 3835403 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2658726 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1176677 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 420775 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -424,62 +432,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 302048 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 302048 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10564 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84260 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 302048 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 302048 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 302048 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 94824 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22896.634818 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21259.302446 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 17613.215135 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 93928 99.06% 99.06% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 167 0.18% 99.23% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 600 0.63% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 30 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 32 0.03% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 34 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 94824 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 84260 88.86% 88.86% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10564 11.14% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 94824 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302048 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 298304 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 298304 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10716 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85635 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 298304 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 298304 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 298304 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 96351 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22754.257870 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21300.315388 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14215.969550 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 95122 98.72% 98.72% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1073 1.11% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 26 0.03% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 56 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 56 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 96351 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 734209704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 734209704 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 734209704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 85635 88.88% 88.88% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10716 11.12% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 96351 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 298304 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302048 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94824 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 298304 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96351 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94824 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 396872 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96351 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 394655 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 94909868 # DTB read hits -system.cpu0.dtb.read_misses 253021 # DTB read misses -system.cpu0.dtb.write_hits 83284387 # DTB write hits -system.cpu0.dtb.write_misses 49027 # DTB write misses +system.cpu0.dtb.read_hits 93899745 # DTB read hits +system.cpu0.dtb.read_misses 250404 # DTB read misses +system.cpu0.dtb.write_hits 82108561 # DTB write hits +system.cpu0.dtb.write_misses 47900 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 38313 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2113 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 10577 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 39156 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2185 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 10307 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10792 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 95162889 # DTB read accesses -system.cpu0.dtb.write_accesses 83333414 # DTB write accesses +system.cpu0.dtb.perms_faults 10956 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 94150149 # DTB read accesses +system.cpu0.dtb.write_accesses 82156461 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 178194255 # DTB hits -system.cpu0.dtb.misses 302048 # DTB misses -system.cpu0.dtb.accesses 178496303 # DTB accesses +system.cpu0.dtb.hits 176008306 # DTB hits +system.cpu0.dtb.misses 298304 # DTB misses +system.cpu0.dtb.accesses 176306610 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -509,885 +516,876 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 66529 # Table walker walks requested -system.cpu0.itb.walker.walksLong 66529 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 603 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 54822 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 66529 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 66529 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 66529 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 55425 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25786.567433 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23469.117152 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 20785.804114 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 51379 92.70% 92.70% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 3140 5.67% 98.37% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 12 0.02% 98.39% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.39% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 536 0.97% 99.36% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 270 0.49% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 8 0.01% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 15 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 29 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 55425 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54822 98.91% 98.91% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 603 1.09% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 55425 # Table walker page sizes translated +system.cpu0.itb.walker.walks 65048 # Table walker walks requested +system.cpu0.itb.walker.walksLong 65048 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 515 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52970 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 65048 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 65048 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 65048 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 53485 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25497.494625 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23453.450778 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 17328.133028 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 49469 92.49% 92.49% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 2789 5.21% 97.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 9 0.02% 97.72% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 1088 2.03% 99.76% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.04% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 47 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 18 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 53485 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 733487204 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 733487204 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 733487204 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 52970 99.04% 99.04% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 515 0.96% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 53485 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66529 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66529 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65048 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 65048 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55425 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55425 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 121954 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 260612167 # ITB inst hits -system.cpu0.itb.inst_misses 66529 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53485 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53485 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 118533 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 259203584 # ITB inst hits +system.cpu0.itb.inst_misses 65048 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 27578 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 28333 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 178681 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 171713 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 260678696 # ITB inst accesses -system.cpu0.itb.hits 260612167 # DTB hits -system.cpu0.itb.misses 66529 # DTB misses -system.cpu0.itb.accesses 260678696 # DTB accesses -system.cpu0.numCycles 1099930824 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 259268632 # ITB inst accesses +system.cpu0.itb.hits 259203584 # DTB hits +system.cpu0.itb.misses 65048 # DTB misses +system.cpu0.itb.accesses 259268632 # DTB accesses +system.cpu0.numCycles 1023758481 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 487305462 # Number of instructions committed -system.cpu0.committedOps 572197777 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 47186623 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4440 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93972724601 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.257169 # CPI: cycles per instruction -system.cpu0.ipc 0.443033 # IPC: instructions per cycle +system.cpu0.committedInsts 483101155 # Number of instructions committed +system.cpu0.committedOps 567019823 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 47457065 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4178 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93688785177 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.119139 # CPI: cycles per instruction +system.cpu0.ipc 0.471890 # IPC: instructions per cycle system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 396450876 69.29% 69.29% # Class of committed instruction -system.cpu0.op_class_0::IntMult 1302433 0.23% 69.51% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 64217 0.01% 69.52% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 76920 0.01% 69.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.op_class_0::MemRead 91382938 15.97% 85.51% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 82920392 14.49% 100.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 393333975 69.37% 69.37% # Class of committed instruction +system.cpu0.op_class_0::IntMult 1298911 0.23% 69.60% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 62117 0.01% 69.61% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 39633 0.01% 69.62% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction +system.cpu0.op_class_0::MemRead 90520623 15.96% 85.58% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 81764563 14.42% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 572197777 # Class of committed instruction +system.cpu0.op_class_0::total 567019823 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13277 # number of quiesce instructions executed -system.cpu0.tickCycles 780613530 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 319317294 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5972011 # number of replacements -system.cpu0.dcache.tags.tagsinuse 508.033077 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 169168179 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5972523 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.324408 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.033077 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992252 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.992252 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 13020 # number of quiesce instructions executed +system.cpu0.tickCycles 768761843 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 254996638 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 6026209 # number of replacements +system.cpu0.dcache.tags.tagsinuse 478.505782 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 166971566 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6026721 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.705209 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 5039130000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.505782 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934582 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.934582 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 388 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 359361260 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 359361260 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 87043361 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 87043361 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 77242749 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 77242749 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 305030 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 305030 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 287060 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 287060 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1877481 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1877481 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1849167 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1849167 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 164573170 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 164573170 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 164878200 # number of overall hits -system.cpu0.dcache.overall_hits::total 164878200 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3693348 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3693348 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2460225 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2460225 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 661742 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 661742 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 847892 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 847892 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173543 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 173543 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200600 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 200600 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 7001465 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 7001465 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 7663207 # number of overall misses -system.cpu0.dcache.overall_misses::total 7663207 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 64125292500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 64125292500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62047058000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 62047058000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 51167444000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 51167444000 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2860725000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2860725000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5699610500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5699610500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5746000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5746000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 177339794500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 177339794500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 177339794500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 177339794500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 90736709 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 90736709 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 79702974 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 79702974 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 966772 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 966772 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1134952 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1134952 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2051024 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2051024 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2049767 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2049767 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 171574635 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 171574635 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 172541407 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 172541407 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040704 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.040704 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030867 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.030867 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.684486 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.684486 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.747073 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.747073 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084613 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084613 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097865 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097865 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.040807 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.040807 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.044414 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.044414 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17362.374870 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17362.374870 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25220.074587 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25220.074587 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 60346.652640 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 60346.652640 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16484.243098 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16484.243098 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28412.814058 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28412.814058 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 355154483 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 355154483 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 85976696 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 85976696 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 76051356 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 76051356 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300861 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 300861 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 281214 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 281214 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1915398 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1915398 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1894723 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1894723 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 162309266 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 162309266 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 162610127 # number of overall hits +system.cpu0.dcache.overall_hits::total 162610127 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3729679 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3729679 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2481919 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2481919 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 681303 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 681303 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 827220 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 827220 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 176003 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 176003 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195484 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 195484 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 7038818 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 7038818 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 7720121 # number of overall misses +system.cpu0.dcache.overall_misses::total 7720121 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57503024000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 57503024000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 50806938500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 50806938500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 27591387500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 27591387500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2577956500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2577956500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4885048500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4885048500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3405000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3405000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 135901350000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 135901350000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 135901350000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 135901350000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 89706375 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 89706375 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 78533275 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 78533275 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 982164 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 982164 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1108434 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1108434 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2091401 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2091401 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2090207 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2090207 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 169348084 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 169348084 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 170330248 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 170330248 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041577 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.041577 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031603 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.031603 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.693675 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.693675 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.746296 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.746296 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084156 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084156 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.093524 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.093524 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041564 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.041564 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045324 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.045324 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15417.687152 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15417.687152 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20470.828621 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20470.828621 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33354.352530 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33354.352530 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.230445 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.230445 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24989.505535 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24989.505535 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25328.955369 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25328.955369 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23141.720496 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 23141.720496 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19307.410704 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19307.410704 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17603.525903 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17603.525903 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5972043 # number of writebacks -system.cpu0.dcache.writebacks::total 5972043 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 444932 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 444932 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1012331 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1012331 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 90 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 90 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46565 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46565 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 65 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 65 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1457353 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1457353 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1457353 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1457353 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3248416 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3248416 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1447894 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1447894 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 660170 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 660170 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 847802 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 847802 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 126978 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 126978 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200535 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 200535 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5544112 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5544112 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 6204282 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 6204282 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31552 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31552 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31148 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31148 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62700 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62700 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50756784000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50756784000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36350818500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36350818500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16579433500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16579433500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 50311370000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 50311370000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1783759500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1783759500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5494928000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5494928000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5416500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5416500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 137418972500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 137418972500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 153998406000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 153998406000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6041391000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6041391000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6041391000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6041391000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035800 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035800 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018166 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018166 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.682860 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.682860 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746994 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746994 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061910 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061910 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097833 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097833 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032313 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032313 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035958 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.035958 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15625.087427 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15625.087427 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25105.994292 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25105.994292 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25113.885060 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25113.885060 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 59343.301856 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 59343.301856 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14047.783868 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14047.783868 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27401.341412 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27401.341412 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 6026220 # number of writebacks +system.cpu0.dcache.writebacks::total 6026220 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 447326 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 447326 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1020420 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1020420 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 73 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 73 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44988 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44988 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 67 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1467819 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1467819 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1467819 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1467819 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3282353 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3282353 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1461499 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1461499 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 679841 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 679841 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 827147 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 827147 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 131015 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 131015 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195417 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 195417 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5570999 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5570999 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6250840 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6250840 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31702 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31225 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62927 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45702695000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45702695000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29281044500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29281044500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14665959000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14665959000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 26759895500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26759895500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1703041500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1703041500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4687173500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4687173500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3267500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3267500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 101743635000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 101743635000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 116409594000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 116409594000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6136923000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6136923000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6136923000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6136923000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036590 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036590 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018610 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018610 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.692187 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.692187 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746230 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746230 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062645 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062645 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.093492 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.093492 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032897 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032897 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036698 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.036698 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13923.759876 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13923.759876 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20034.939812 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20034.939812 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21572.630953 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21572.630953 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32352.043228 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32352.043228 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12998.828378 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12998.828378 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23985.495121 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23985.495121 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24786.471215 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24786.471215 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24821.309863 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24821.309863 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191474.106237 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191474.106237 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96353.923445 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96353.923445 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 10516028 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.897153 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 249911266 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 10516540 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 23.763640 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 33054279000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897153 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999799 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999799 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18263.086208 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18263.086208 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18623.032104 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18623.032104 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193581.572141 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193581.572141 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97524.480748 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97524.480748 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 9817579 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.932451 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 249208397 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9818091 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 25.382572 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 22021065000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932451 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 531372181 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 531372181 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 249911266 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 249911266 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 249911266 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 249911266 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 249911266 # number of overall hits -system.cpu0.icache.overall_hits::total 249911266 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 10516550 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 10516550 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 10516550 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 10516550 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 10516550 # number of overall misses -system.cpu0.icache.overall_misses::total 10516550 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 109481334000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 109481334000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 109481334000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 109481334000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 109481334000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 109481334000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 260427816 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 260427816 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 260427816 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 260427816 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 260427816 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 260427816 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040382 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.040382 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040382 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.040382 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040382 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.040382 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10410.384965 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10410.384965 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10410.384965 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10410.384965 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10410.384965 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10410.384965 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 527871096 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 527871096 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 249208397 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 249208397 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 249208397 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 249208397 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 249208397 # number of overall hits +system.cpu0.icache.overall_hits::total 249208397 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9818101 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9818101 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9818101 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9818101 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9818101 # number of overall misses +system.cpu0.icache.overall_misses::total 9818101 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 99002118000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 99002118000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 99002118000 # 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average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92491.166179 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8242304 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8243665 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 1198 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1038823 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2850300 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16126.746563 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 26039957 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2866458 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 9.084367 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 8707838500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15278.163009 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 75.302883 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 76.950246 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 696.330425 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.932505 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004596 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004697 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.042501 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984298 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1240 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14860 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 23 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 522 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 622 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 73 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 43 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1092 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5314 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7823 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 536 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.075684 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.906982 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 554897291 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 554897291 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 569819 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 172472 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 742291 # 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number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 898 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 898 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 10706 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 10718 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 9 # 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number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 84001 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31225 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52299 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 115226 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 290829500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 661622000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38426708957 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38426708957 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5314605493 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5314605493 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3216326998 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3216326998 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2770000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2770000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11196985497 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11196985497 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 20080949000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 20080949000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 29451947493 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 29451947493 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 20309675000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 20309675000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 290829500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20080949000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 40648932990 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 61391503990 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 290829500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20080949000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 40648932990 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38426708957 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 99818212947 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4418803500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5883144500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10301948000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4418803500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5883144500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10301948000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027711 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998585 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998585 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997627 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997627 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.224517 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.224517 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.071267 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254730 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254730 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.728290 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.728290 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.247822 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.125137 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.247822 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.222469 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.222469 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073759 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.248813 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248813 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.737239 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.737239 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242791 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128085 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242791 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.174585 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35899.796364 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56710.263890 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29958.038116 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29958.038116 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19875.340328 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19875.340328 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 994400 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 994400 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 58388.867967 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 58388.867967 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33267.758218 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35913.269977 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35913.269977 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70950.838813 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70950.838813 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40568.708271 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37874.691491 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40568.708271 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43209.493938 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183468.464757 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152454.084735 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92325.311005 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111164.795799 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 33857668 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 17264460 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3128 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 2263959 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2263472 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 487 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 924227 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 15578589 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31149 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31148 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5528357 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 12594701 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 3060195 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1058289 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 483217 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361321 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 533499 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1230571 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1205955 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 10516550 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5115631 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 898497 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 845557 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 31653744 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19358528 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 379556 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1223236 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 52615064 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1349432640 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 724409976 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1445984 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4653440 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 2079942040 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 7567377 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 25314697 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.102016 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.302732 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.180273 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 31863.899056 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46387.947706 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20687.367869 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20687.367869 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16459.293479 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16459.293479 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 461666.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 461666.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41499.673832 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41499.673832 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27729.414851 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28921.697098 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28921.697098 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33385.840298 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33385.840298 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30196.275404 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34883.677504 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185576.446281 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122640.778086 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93491.577542 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89406.453405 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 32574371 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16625689 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 2229520 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2229086 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 913111 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14927613 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31225 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31225 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5591471 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 11901739 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2979875 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1058098 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 473129 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352230 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 525861 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1247048 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1223348 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9818101 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5127973 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 875849 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 825149 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29558377 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19506589 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370132 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1208276 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 50643374 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1260030528 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 732739948 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1405536 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4588864 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1998764876 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 7447074 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 24526103 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.104449 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.305900 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 22732690 89.80% 89.80% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2581520 10.20% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 487 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 21964812 89.56% 89.56% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2560857 10.44% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 434 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 25314697 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 33752723480 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 24526103 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 32454354981 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 205163062 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 208052919 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 15856801952 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14809077024 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8551593856 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8648892723 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 198848419 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 194486906 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 641675758 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 634782270 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 127453033 # Number of BP lookups -system.cpu1.branchPred.condPredicted 91217282 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5663830 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 96224557 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 67852361 # Number of BTB hits +system.cpu1.branchPred.lookups 123875539 # Number of BP lookups +system.cpu1.branchPred.condPredicted 88073767 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5721607 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 93465185 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 65276742 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 70.514600 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 14431851 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 916644 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3338859 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2197659 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1141200 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 412569 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 69.840703 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 14217829 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 926540 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3290763 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2135700 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1155063 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 419705 # Number of mispredicted indirect branches. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1417,64 +1415,61 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 261031 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 261031 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9619 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80662 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 261031 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 261031 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 261031 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 90281 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23808.564371 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21471.713865 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 22312.583155 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 88920 98.49% 98.49% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 187 0.21% 98.70% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 992 1.10% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 43 0.05% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 45 0.05% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 26 0.03% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 33 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 21 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 90281 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1786242352 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1786242352 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1786242352 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 80662 89.35% 89.35% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 9619 10.65% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 90281 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261031 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 255224 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 255224 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8861 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76574 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 255224 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 255224 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 255224 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 85435 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22815.538128 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21300.261475 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14551.493747 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 84387 98.77% 98.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 897 1.05% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 42 0.05% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 51 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 31 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 13 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 85435 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -788977056 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -788977056 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -788977056 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 76574 89.63% 89.63% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8861 10.37% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 85435 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 255224 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261031 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90281 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 255224 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 85435 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90281 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 351312 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 85435 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 340659 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 80497438 # DTB read hits -system.cpu1.dtb.read_misses 213464 # DTB read misses -system.cpu1.dtb.write_hits 70911031 # DTB write hits -system.cpu1.dtb.write_misses 47567 # DTB write misses +system.cpu1.dtb.read_hits 78594683 # DTB read hits +system.cpu1.dtb.read_misses 208094 # DTB read misses +system.cpu1.dtb.write_hits 69544419 # DTB write hits +system.cpu1.dtb.write_misses 47130 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37751 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1110 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 7072 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 35846 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 839 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11967 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 80710902 # DTB read accesses -system.cpu1.dtb.write_accesses 70958598 # DTB write accesses +system.cpu1.dtb.perms_faults 11450 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 78802777 # DTB read accesses +system.cpu1.dtb.write_accesses 69591549 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 151408469 # DTB hits -system.cpu1.dtb.misses 261031 # DTB misses -system.cpu1.dtb.accesses 151669500 # DTB accesses +system.cpu1.dtb.hits 148139102 # DTB hits +system.cpu1.dtb.misses 255224 # DTB misses +system.cpu1.dtb.accesses 148394326 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1504,864 +1499,883 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 64962 # Table walker walks requested -system.cpu1.itb.walker.walksLong 64962 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 549 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55482 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 64962 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 64962 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 64962 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 56031 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 27185.022577 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24059.100661 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 24848.225124 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 54737 97.69% 97.69% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 10 0.02% 97.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1140 2.03% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 44 0.08% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 63 0.11% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 23 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 11 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 56031 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1785244852 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1785244852 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1785244852 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 55482 99.02% 99.02% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 549 0.98% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 56031 # Table walker page sizes translated +system.cpu1.itb.walker.walks 62177 # Table walker walks requested +system.cpu1.itb.walker.walksLong 62177 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54596 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 62177 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 62177 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 62177 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 55226 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25650.988665 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23787.605646 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 16059.408850 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 49961 90.47% 90.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 4236 7.67% 98.14% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 9 0.02% 98.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 906 1.64% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 28 0.05% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 21 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 55226 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -789630556 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -789630556 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -789630556 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54596 98.86% 98.86% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 630 1.14% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55226 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64962 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64962 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62177 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 62177 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56031 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56031 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 120993 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 225980528 # ITB inst hits -system.cpu1.itb.inst_misses 64962 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55226 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55226 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 117403 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 219337574 # ITB inst hits +system.cpu1.itb.inst_misses 62177 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26783 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25383 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 166792 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 167002 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 226045490 # ITB inst accesses -system.cpu1.itb.hits 225980528 # DTB hits -system.cpu1.itb.misses 64962 # DTB misses -system.cpu1.itb.accesses 226045490 # DTB accesses -system.cpu1.numCycles 884296043 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 219399751 # ITB inst accesses +system.cpu1.itb.hits 219337574 # DTB hits +system.cpu1.itb.misses 62177 # DTB misses +system.cpu1.itb.accesses 219399751 # DTB accesses +system.cpu1.numCycles 838096745 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 410764166 # Number of instructions committed -system.cpu1.committedOps 484072804 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 46607969 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5245 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 94188329171 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.152807 # CPI: cycles per instruction -system.cpu1.ipc 0.464510 # IPC: instructions per cycle +system.cpu1.committedInsts 400342475 # Number of instructions committed +system.cpu1.committedOps 472062345 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 44700411 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5381 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93874475142 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.093449 # CPI: cycles per instruction +system.cpu1.ipc 0.477681 # IPC: instructions per cycle system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 334821764 69.17% 69.17% # Class of committed instruction -system.cpu1.op_class_0::IntMult 956339 0.20% 69.37% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 55233 0.01% 69.38% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 37353 0.01% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.op_class_0::MemRead 77588616 16.03% 85.41% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 70613457 14.59% 100.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 326101667 69.08% 69.08% # Class of committed instruction +system.cpu1.op_class_0::IntMult 925373 0.20% 69.28% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 54057 0.01% 69.29% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.29% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 72329 0.02% 69.30% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction +system.cpu1.op_class_0::MemRead 75664367 16.03% 85.33% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 69244510 14.67% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 484072804 # Class of committed instruction +system.cpu1.op_class_0::total 472062345 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5362 # number of quiesce instructions executed -system.cpu1.tickCycles 676945147 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 207350896 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5011869 # number of replacements -system.cpu1.dcache.tags.tagsinuse 436.764256 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 143763031 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5012381 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.681585 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8498279834500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 436.764256 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.853055 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.853055 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 376 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 305397096 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 305397096 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 73662807 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 73662807 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 66040616 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 66040616 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 200864 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 200864 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 33950 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 33950 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1678906 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1678906 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1638259 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1638259 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 139737373 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 139737373 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 139938237 # number of overall hits -system.cpu1.dcache.overall_hits::total 139938237 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3193197 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3193197 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2277873 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2277873 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 648992 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 648992 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 409957 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 409957 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159945 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 159945 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199493 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 199493 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5881027 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5881027 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6530019 # number of overall misses -system.cpu1.dcache.overall_misses::total 6530019 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52208022500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 52208022500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 51224639500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 51224639500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 14899741000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 14899741000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2555092000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2555092000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5532212500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5532212500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5344000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5344000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 118332403000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 118332403000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 118332403000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 118332403000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 76856004 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 76856004 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 68318489 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 68318489 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 849856 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 849856 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 443907 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 443907 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1838851 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1838851 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1837752 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1837752 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 145618400 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 145618400 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 146468256 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 146468256 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041548 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.041548 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033342 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.033342 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.763649 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.763649 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.923520 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.923520 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086981 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086981 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108553 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108553 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040387 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.040387 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044583 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044583 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16349.765611 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16349.765611 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22487.926017 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22487.926017 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 36344.643463 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 36344.643463 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15974.816343 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15974.816343 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27731.361501 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27731.361501 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 5498 # number of quiesce instructions executed +system.cpu1.tickCycles 657140254 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 180956491 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 4810857 # number of replacements +system.cpu1.dcache.tags.tagsinuse 458.623346 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 140763490 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4811366 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.256450 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8377530544000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.623346 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.895749 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.895749 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 298669128 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 298669128 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 72030058 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 72030058 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 64877267 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 64877267 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 197389 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 197389 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 40268 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 40268 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1587155 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1587155 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1543611 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1543611 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 136947593 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 136947593 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 137144982 # number of overall hits +system.cpu1.dcache.overall_hits::total 137144982 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3077185 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3077185 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2162319 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2162319 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 609138 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 609138 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 415243 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 415243 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150447 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 150447 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 192941 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 192941 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5654747 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5654747 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6263885 # number of overall misses +system.cpu1.dcache.overall_misses::total 6263885 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46366444000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 46366444000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40662976500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 40662976500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10070349000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10070349000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2311960000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2311960000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4775235000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4775235000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2623000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2623000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 97099769500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 97099769500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 97099769500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 97099769500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 75107243 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 75107243 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 67039586 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 67039586 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 806527 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 806527 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 455511 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 455511 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1737602 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1737602 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1736552 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1736552 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 142602340 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 142602340 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 143408867 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 143408867 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040971 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.040971 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032254 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.032254 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.755261 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.755261 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.911598 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.911598 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086583 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086583 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.111106 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.111106 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039654 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.039654 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043679 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043679 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15067.811653 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15067.811653 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18805.262545 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18805.262545 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24251.700811 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24251.700811 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15367.272196 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15367.272196 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24749.716234 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24749.716234 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20121.043995 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20121.043995 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18121.295359 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18121.295359 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17171.372919 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17171.372919 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15501.524932 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15501.524932 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5011891 # number of writebacks -system.cpu1.dcache.writebacks::total 5011891 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 367321 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 367321 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 943211 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 943211 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40165 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40165 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 85 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 85 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1310590 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1310590 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1310590 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1310590 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2825876 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2825876 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1334662 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1334662 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 648629 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 648629 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 409899 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 409899 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 119780 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 119780 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199408 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 199408 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4570437 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4570437 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5219066 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5219066 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7337 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7337 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7641 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7641 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14978 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14978 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41329046000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41329046000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30034339000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30034339000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15914789000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15914789000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14484285500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14484285500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1714801500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1714801500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5327664500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5327664500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4914500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4914500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 85847670500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 85847670500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101762459500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 101762459500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 919733500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 919733500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 919733500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 919733500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036768 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036768 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019536 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019536 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.763222 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.763222 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.923389 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.923389 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065139 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065139 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108506 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108506 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031386 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031386 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035633 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035633 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14625.215685 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14625.215685 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22503.329682 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22503.329682 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24536.042946 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24536.042946 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 35336.230388 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 35336.230388 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14316.258975 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14316.258975 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26717.406022 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26717.406022 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 4810864 # number of writebacks +system.cpu1.dcache.writebacks::total 4810864 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 357052 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 357052 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 892415 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 892415 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 74 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 74 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40665 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40665 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 58 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1249541 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1249541 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1249541 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1249541 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2720133 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2720133 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1269904 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1269904 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 608760 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 608760 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 415169 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 415169 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 109782 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 109782 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 192883 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 192883 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4405206 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4405206 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5013966 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5013966 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6941 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6941 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7280 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14221 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14221 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36972803500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36972803500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23335803000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23335803000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13834846000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13834846000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9650155000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9650155000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1512082000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1512082000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4580259000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4580259000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2341500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2341500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69958761500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 69958761500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83793607500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 83793607500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 837242500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 837242500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 837242500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 837242500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036217 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036217 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018943 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018943 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.754792 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.754792 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.911436 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.911436 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063180 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063180 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.111072 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.111072 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030892 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030892 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034963 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034963 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13592.277841 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13592.277841 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18376.037086 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18376.037086 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22726.273080 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22726.273080 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23243.919946 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23243.919946 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13773.496566 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13773.496566 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23746.307347 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23746.307347 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18783.252127 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18783.252127 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19498.212803 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19498.212803 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125355.526782 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125355.526782 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 61405.628255 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 61405.628255 # average overall mshr uncacheable latency -system.cpu1.icache.tags.replacements 8449872 # number of replacements -system.cpu1.icache.tags.tagsinuse 506.781387 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 217357255 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 8450384 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 25.721583 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8379180185000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.781387 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989807 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.989807 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15880.928497 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15880.928497 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16712.041426 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16712.041426 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120622.748883 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120622.748883 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 58873.672738 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 58873.672738 # average overall mshr uncacheable latency +system.cpu1.icache.tags.replacements 8744967 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.224680 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 210419103 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8745479 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 24.060329 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8367967785000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.224680 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990673 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990673 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 365 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 460065662 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 460065662 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 217357255 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 217357255 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 217357255 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 217357255 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 217357255 # number of overall hits -system.cpu1.icache.overall_hits::total 217357255 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 8450384 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 8450384 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 8450384 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 8450384 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 8450384 # number of overall misses -system.cpu1.icache.overall_misses::total 8450384 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 88216596500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 88216596500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 88216596500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 88216596500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 88216596500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 88216596500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 225807639 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 225807639 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 225807639 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 225807639 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 225807639 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 225807639 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037423 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.037423 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037423 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.037423 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037423 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.037423 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10439.359501 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10439.359501 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10439.359501 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10439.359501 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10439.359501 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10439.359501 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 447074643 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 447074643 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 210419103 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 210419103 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 210419103 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 210419103 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 210419103 # number of overall hits +system.cpu1.icache.overall_hits::total 210419103 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 8745479 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 8745479 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 8745479 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 8745479 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 8745479 # 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number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 219164582 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 219164582 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039904 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.039904 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.039904 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.039904 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.039904 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.039904 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10093.006284 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10093.006284 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10093.006284 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10093.006284 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10093.006284 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10093.006284 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 8449872 # number of writebacks -system.cpu1.icache.writebacks::total 8449872 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8450384 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 8450384 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 8450384 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 8450384 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 8450384 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 8450384 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 8744967 # number of writebacks +system.cpu1.icache.writebacks::total 8744967 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8745479 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 8745479 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 8745479 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 8745479 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 8745479 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 8745479 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 83991404500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 83991404500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 83991404500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 83991404500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 83991404500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 83991404500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13018000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13018000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13018000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 13018000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037423 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037423 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037423 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.037423 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037423 # 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average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 139978.494624 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7137751 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7137894 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 127 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 83895435000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 83895435000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 83895435000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 83895435000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 83895435000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 83895435000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8450000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8450000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8450000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8450000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039904 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.039904 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.039904 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9593.006284 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90860.215054 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90860.215054 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6641051 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6641093 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 36 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 851890 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2314380 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13359.571881 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 21237271 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2330274 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 9.113637 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10056444277000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12441.859609 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 52.856295 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 59.323629 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 805.532348 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.759391 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003226 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003621 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.049166 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.815404 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1023 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14801 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 326 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 596 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 82 # Occupied blocks per task id +system.cpu1.l2cache.prefetcher.pfSpanPage 796339 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2218428 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13419.558556 # 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mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.264644 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135232 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.264644 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.194834 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42980.473047 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50482.920781 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30794.884700 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30794.884700 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19197.135951 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19197.135951 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 897199.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 897199.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44069.998428 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44069.998428 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29828.373467 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31486.407700 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31486.407700 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45586.717224 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45586.717224 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34176.305402 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32740.287687 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34176.305402 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37793.329747 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117341.079460 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117524.293405 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 57479.736948 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57939.453255 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 27757324 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14199775 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1809 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 2096264 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2095922 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 342 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 778911 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 12918528 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 7641 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 7641 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4342023 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 10300458 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2852323 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 992320 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 439929 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 359269 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 498097 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1135001 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1111432 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8450384 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4652967 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 462443 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 408042 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25350826 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16287327 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370687 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1094902 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 43103742 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1081622336 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 628052039 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1412064 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4140800 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1715227239 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6782222 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 21311973 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.112849 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.316459 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186208 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 31037.609644 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35918.637723 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20808.816504 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20808.816504 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16224.436051 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16224.436051 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 500874.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 500874.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32120.644676 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32120.644676 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26735.574243 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26815.018004 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26815.018004 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26186.131086 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26186.131086 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27558.035864 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29846.821834 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112606.396773 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112213.107762 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 54961.043527 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 55142.308230 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 27911552 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14263179 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 2035614 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2035313 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 755700 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13030335 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 7280 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 7280 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4134671 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 10529340 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2783515 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 903944 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 426493 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 348519 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 477830 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1080105 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1057121 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8745479 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4495606 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 466229 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 413447 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26236111 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15633953 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 355051 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1069038 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 43294153 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1119394496 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 601463021 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1354416 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4048968 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1726260901 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6529606 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 21121122 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.110367 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.313393 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 18907277 88.72% 88.72% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2404354 11.28% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 342 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 18790338 88.96% 88.96% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2330483 11.03% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 301 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 21311973 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 27584218481 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 21121122 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 27750114484 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 185839513 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 177306545 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 12678955503 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 13121677843 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7484332893 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7163335235 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 194250357 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 185802393 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 577391819 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 563017795 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40390 # Transaction distribution -system.iobus.trans_dist::ReadResp 40390 # Transaction distribution -system.iobus.trans_dist::WriteReq 136973 # Transaction distribution -system.iobus.trans_dist::WriteResp 136973 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40337 # Transaction distribution +system.iobus.trans_dist::ReadResp 40337 # Transaction distribution +system.iobus.trans_dist::WriteReq 136616 # Transaction distribution +system.iobus.trans_dist::WriteResp 136616 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47664 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2372,15 +2386,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122924 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231722 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231722 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122598 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231228 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231228 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354726 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353906 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47684 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2391,103 +2405,103 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155939 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355240 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155705 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338928 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338928 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42523001 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496719 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 43180502 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25802501 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25595502 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36398001 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36402501 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568577386 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569469754 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92938000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92713000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148162000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147924000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115843 # number of replacements -system.iocache.tags.tagsinuse 11.310828 # Cycle average of tags in use +system.iocache.tags.replacements 115611 # number of replacements +system.iocache.tags.tagsinuse 11.284790 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115859 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115627 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9138959017000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.826637 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.484190 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239165 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.467762 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706927 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9167417766000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.418888 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.865902 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463681 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.241619 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705299 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1043106 # Number of tag accesses -system.iocache.tags.data_accesses 1043106 # Number of data accesses +system.iocache.tags.tag_accesses 1040883 # Number of tag accesses +system.iocache.tags.data_accesses 1040883 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115861 # number of demand (read+write) misses -system.iocache.demand_misses::total 115901 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115614 # number of demand (read+write) misses +system.iocache.demand_misses::total 115654 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115861 # number of overall misses -system.iocache.overall_misses::total 115901 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1651659585 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1656859085 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115614 # number of overall misses +system.iocache.overall_misses::total 115654 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1668794518 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1673992518 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13563940301 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13563940301 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15215599886 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15221168386 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15215599886 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15221168386 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12857701236 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12857701236 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14526495754 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14532062754 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14526495754 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14532062754 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115861 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115901 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115614 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115654 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115861 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115901 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115614 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115654 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2501,53 +2515,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 186060.559311 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 185871.559906 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 187800.418411 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 187604.227054 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126784.755674 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126784.755674 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 131329.051397 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 131329.051397 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32764 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120471.677873 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120471.677873 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125651.190223 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125651.190223 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33480 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3385 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3531 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.679173 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.481733 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106951 # number of writebacks -system.iocache.writebacks::total 106951 # number of writebacks +system.iocache.writebacks::writebacks 106695 # number of writebacks +system.iocache.writebacks::total 106695 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8877 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8886 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8923 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115861 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115901 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115614 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115654 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115861 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115901 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1207809585 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1211159085 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115614 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115654 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1224494518 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1227842518 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8208491858 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8208491858 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9416301443 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9419869943 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9416301443 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9419869943 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7512769435 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7512769435 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8737263953 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8740830953 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8737263953 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8740830953 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2561,637 +2575,644 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136060.559311 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 135871.559906 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137800.418411 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 137604.227054 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76726.350277 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76726.350277 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 81272.399194 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 81275.139498 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 81272.399194 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 81275.139498 # average overall mshr miss latency -system.l2c.tags.replacements 1387428 # number of replacements -system.l2c.tags.tagsinuse 63551.257518 # Cycle average of tags in use -system.l2c.tags.total_refs 6641936 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1448331 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.585924 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 13283135500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 22018.288167 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 94.707462 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 112.653017 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5422.209579 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6394.892392 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5645.972820 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 238.578829 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 322.014833 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3724.645789 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6574.117531 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13003.177099 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.335972 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001445 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001719 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.082736 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.097578 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.086151 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003640 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004914 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056834 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.100313 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.198413 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.969715 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10329 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 221 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50353 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 518 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 2097 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 7705 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 212 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2461 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13754 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 33762 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.157608 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003372 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.768326 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 81054625 # Number of tag accesses -system.l2c.tags.data_accesses 81054625 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 2804232 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2804232 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 166858 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 141079 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 307937 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 43211 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 40746 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 83957 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 52655 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 61293 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113948 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6392 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4086 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 674086 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 617640 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 331682 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 7229 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5312 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 633543 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 593468 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 330392 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 3203830 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 133432 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 138176 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 271608 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6392 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4086 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 674086 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 670295 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 331682 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 7229 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5312 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 633543 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 654761 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 330392 # number of demand (read+write) hits -system.l2c.demand_hits::total 3317778 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6392 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4086 # number of overall hits -system.l2c.overall_hits::cpu0.inst 674086 # number of overall hits -system.l2c.overall_hits::cpu0.data 670295 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 331682 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 7229 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5312 # number of overall hits -system.l2c.overall_hits::cpu1.inst 633543 # number of overall hits -system.l2c.overall_hits::cpu1.data 654761 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 330392 # number of overall hits -system.l2c.overall_hits::total 3317778 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 63565 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 62220 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 125785 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 13487 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 11849 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 25336 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 80559 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 50978 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 131537 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1402 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 75397 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 144871 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 231057 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2351 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1996 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 47759 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 100866 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 195589 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 802834 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 470568 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 95260 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 565828 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1546 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1402 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 75397 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 225430 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 231057 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2351 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1996 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 47759 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 151844 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 195589 # number of demand (read+write) misses -system.l2c.demand_misses::total 934371 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1546 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1402 # number of overall misses -system.l2c.overall_misses::cpu0.inst 75397 # number of overall misses -system.l2c.overall_misses::cpu0.data 225430 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 231057 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2351 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1996 # number of overall misses -system.l2c.overall_misses::cpu1.inst 47759 # number of overall misses -system.l2c.overall_misses::cpu1.data 151844 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 195589 # number of overall misses -system.l2c.overall_misses::total 934371 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 1159828500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1086354500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 2246183000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 232119500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 209371000 # 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number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6431697000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 14230471500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 32826320681 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 125256809936 # number of ReadSharedReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu0.data 174062000 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu1.data 150333500 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::total 324395500 # number of InvalidateReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 218104500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 197814500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 10138484000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 31372323000 # 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number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 203299 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 433722 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 56698 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 52595 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 109293 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 133214 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 112271 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 245485 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7938 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5488 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 749483 # 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number of demand (read+write) accesses -system.l2c.demand_accesses::total 4252149 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 7938 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 5488 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 749483 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 895725 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 562739 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9580 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7308 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 681302 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 806605 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 525981 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4252149 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.275862 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.306052 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.290013 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.237874 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.225288 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.231817 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.604734 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.454062 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.535825 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.194759 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.255466 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.100599 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.189992 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.410594 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.245407 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.273125 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.070100 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.145270 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.371856 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.200375 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.779086 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.408078 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.675667 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.194759 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.255466 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.100599 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.251673 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.410594 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.245407 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.273125 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.070100 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.188251 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.371856 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.219741 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.194759 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.255466 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.100599 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.251673 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.410594 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.245407 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.273125 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.070100 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.188251 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.371856 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.219741 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 18246.338394 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17459.892318 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 17857.320030 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17210.610217 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17669.929952 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 17425.422324 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138407.477749 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133341.617953 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 136444.171602 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 141076.649418 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141094.507846 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134468.002706 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139588.703053 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 174771.951315 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139710.974054 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140691.132265 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134669.842333 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141082.936768 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 156018.317530 # average ReadSharedReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 369.897656 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 1578.138778 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::total 573.311148 # average InvalidateReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141076.649418 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141094.507846 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 134468.002706 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 139166.583862 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 174771.951315 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139710.974054 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140691.132265 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 134669.842333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 138483.973684 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 153262.747812 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141076.649418 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141094.507846 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 134468.002706 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 139166.583862 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 174771.951315 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139710.974054 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140691.132265 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 134669.842333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 138483.973684 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 153262.747812 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 971 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.738204 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.738204 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency +system.l2c.tags.replacements 1371243 # number of replacements +system.l2c.tags.tagsinuse 63411.869664 # Cycle average of tags in use +system.l2c.tags.total_refs 6460055 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1430877 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.514752 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7876910500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 21329.379338 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 243.549056 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 346.213430 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5332.164924 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9972.711960 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14780.287325 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 85.709675 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 92.474711 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3611.694384 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3808.494767 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3809.190093 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.325461 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003716 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.005283 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.081362 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.152172 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.225529 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001308 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001411 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.055110 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.058113 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058124 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.967588 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 9222 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 255 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 50157 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 98 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 408 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 8708 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1961 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5894 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 42105 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.140717 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.765335 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 79235647 # Number of tag accesses +system.l2c.tags.data_accesses 79235647 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 2747527 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2747527 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 170119 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 132427 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 302546 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 41747 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 38038 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 79785 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 52086 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 59057 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 111143 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6348 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3788 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 658119 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 620329 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 316694 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6918 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5196 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 620556 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 563518 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 312616 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 3114082 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 130339 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 134354 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 264693 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6348 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3788 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 658119 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 672415 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 316694 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6918 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5196 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 620556 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 622575 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 312616 # number of demand (read+write) hits +system.l2c.demand_hits::total 3225225 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6348 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3788 # number of overall hits +system.l2c.overall_hits::cpu0.inst 658119 # number of overall hits +system.l2c.overall_hits::cpu0.data 672415 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 316694 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6918 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5196 # number of overall hits +system.l2c.overall_hits::cpu1.inst 620556 # number of overall hits +system.l2c.overall_hits::cpu1.data 622575 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 312616 # number of overall hits +system.l2c.overall_hits::total 3225225 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 63896 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 60301 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 124197 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 12467 # 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average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83264.562249 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48660.123998 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 91156.141469 # average overall mshr uncacheable latency -system.membus.trans_dist::ReadReq 91289 # Transaction distribution -system.membus.trans_dist::ReadResp 902614 # Transaction distribution -system.membus.trans_dist::WriteReq 38789 # Transaction distribution -system.membus.trans_dist::WriteResp 38789 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1182866 # Transaction distribution -system.membus.trans_dist::CleanEvict 259673 # Transaction distribution -system.membus.trans_dist::UpgradeReq 445486 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 315870 # Transaction distribution +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.273042 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.312881 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.291035 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.229959 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.227623 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.608025 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.463927 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.542710 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.187612 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.155621 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.202847 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.781222 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.415262 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.679365 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.249927 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.199302 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.222752 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.249927 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.199302 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.222752 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21610.225883 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21647.742077 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21628.441009 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24617.068902 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24607.448617 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24612.514128 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79236.339662 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72651.227338 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 76684.798346 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79699.783619 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81643.583511 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 98118.647459 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20918.654291 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20760.842224 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20891.805966 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79532.664887 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78677.910596 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 95060.153730 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79532.664887 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78677.910596 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 95060.153730 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167570.579301 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 94623.649229 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102107.944449 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84420.399908 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46177.192630 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 71756.492357 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3789204 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2296931 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 91033 # Transaction distribution +system.membus.trans_dist::ReadResp 892432 # Transaction distribution +system.membus.trans_dist::WriteReq 38505 # Transaction distribution +system.membus.trans_dist::WriteResp 38505 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1181777 # Transaction distribution +system.membus.trans_dist::CleanEvict 252869 # Transaction distribution +system.membus.trans_dist::UpgradeReq 437143 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 308404 # Transaction distribution system.membus.trans_dist::UpgradeResp 22 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 143483 # Transaction distribution -system.membus.trans_dist::ReadExResp 126149 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 811325 # Transaction distribution -system.membus.trans_dist::InvalidateReq 668729 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122924 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 143945 # Transaction distribution +system.membus.trans_dist::ReadExResp 126263 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 801399 # Transaction distribution +system.membus.trans_dist::InvalidateReq 663637 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122598 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27208 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4633500 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4783684 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5021882 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155939 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26474 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4585882 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4735006 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4973212 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155705 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 131613504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 131825183 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7257920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 139083103 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 621301 # Total snoops (count) -system.membus.snoop_fanout::samples 3957559 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52948 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 130931136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 131141113 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7272704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7272704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 138413817 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 608511 # Total snoops (count) +system.membus.snoop_fanout::samples 2484071 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012278 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.110125 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3957559 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2453571 98.77% 98.77% # Request fanout histogram +system.membus.snoop_fanout::1 30500 1.23% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3957559 # Request fanout histogram -system.membus.reqLayer0.occupancy 105148497 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2484071 # Request fanout histogram +system.membus.reqLayer0.occupancy 105594995 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22946496 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22316500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8356686345 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8304045809 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5285705581 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5231778477 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45456154 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45499333 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3245,53 +3266,54 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 12610950 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6824430 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2134576 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 142334 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 128133 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 14201 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 91291 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4901304 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38789 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38789 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3987141 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 3034318 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 743952 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 399827 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1143779 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302895 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302895 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4817262 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 944420 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 837436 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10209362 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8295779 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 18505141 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 250153960 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 205145975 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 455299935 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3080857 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8841930 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.362342 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.484007 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 12326432 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6670511 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2086069 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 130580 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 118652 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 11928 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 91035 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4782322 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38505 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38505 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3822609 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2941580 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 730122 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 388189 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1118311 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 299700 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 299700 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4691812 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 853093 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 825528 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10130133 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7962376 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18092509 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 250257116 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194861853 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 445118969 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2830390 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8463866 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.368667 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.485356 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5652330 63.93% 63.93% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3175399 35.91% 99.84% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 14201 0.16% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5355444 63.27% 63.27% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3096494 36.58% 99.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 11928 0.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8841930 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9598709952 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8463866 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9400124055 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2569910 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2566916 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4696248682 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4651836575 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4118726891 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3960751843 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 0e56e5404..9c49f3e4a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.660653 # Nu sim_ticks 51660652947000 # Number of ticks simulated final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 286668 # Simulator instruction rate (inst/s) -host_op_rate 336848 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15934426663 # Simulator tick rate (ticks/s) -host_mem_usage 682904 # Number of bytes of host memory used -host_seconds 3242.08 # Real time elapsed on the host +host_inst_rate 260799 # Simulator instruction rate (inst/s) +host_op_rate 306450 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14496494193 # Simulator tick rate (ticks/s) +host_mem_usage 677256 # Number of bytes of host memory used +host_seconds 3563.67 # Real time elapsed on the host sim_insts 929398934 # Number of instructions simulated sim_ops 1092086880 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index 005b587a4..5d9de1414 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.327140 # Nu sim_ticks 51327139864000 # Number of ticks simulated final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109720 # Simulator instruction rate (inst/s) -host_op_rate 128923 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6639754669 # Simulator tick rate (ticks/s) -host_mem_usage 687008 # Number of bytes of host memory used -host_seconds 7730.28 # Real time elapsed on the host +host_inst_rate 134762 # Simulator instruction rate (inst/s) +host_op_rate 158348 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8155197699 # Simulator tick rate (ticks/s) +host_mem_usage 681612 # Number of bytes of host memory used +host_seconds 6293.79 # Real time elapsed on the host sim_insts 848164321 # Number of instructions simulated sim_ops 996610207 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 7762e55fa..c46aa316c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,167 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.468752 # Number of seconds simulated -sim_ticks 47468751978000 # Number of ticks simulated -final_tick 47468751978000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.384315 # Number of seconds simulated +sim_ticks 47384315163000 # Number of ticks simulated +final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133266 # Simulator instruction rate (inst/s) -host_op_rate 156717 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6699893970 # Simulator tick rate (ticks/s) -host_mem_usage 769956 # Number of bytes of host memory used -host_seconds 7085.00 # Real time elapsed on the host -sim_insts 944191442 # Number of instructions simulated -sim_ops 1110340105 # Number of ops (including micro ops) simulated +host_inst_rate 172390 # Simulator instruction rate (inst/s) +host_op_rate 202727 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9043218476 # Simulator tick rate (ticks/s) +host_mem_usage 765852 # Number of bytes of host memory used +host_seconds 5239.76 # Real time elapsed on the host +sim_insts 903281747 # Number of instructions simulated +sim_ops 1062243320 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 171136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 120960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3861216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 14070216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 17654336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 218240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 209216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3621984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 13693456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 20748864 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 405504 # Number of bytes read from this memory -system.physmem.bytes_read::total 74775128 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3861216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3621984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7483200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 90808384 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 88320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 58304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4233376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 12825352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 13896960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 201536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 189312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2647264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 11439440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 16431296 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 444928 # Number of bytes read from this memory +system.physmem.bytes_read::total 62456088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4233376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2647264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6880640 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 79489088 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 90828968 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2674 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1890 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 76284 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 219860 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 275849 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3269 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56637 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 213973 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 324201 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6336 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1184383 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1418881 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 79509672 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1380 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 911 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 82099 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 200409 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 217140 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3149 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2958 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 41407 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 178754 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 256739 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6952 # Number of read requests responded to by this memory +system.physmem.num_reads::total 991898 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1242017 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1421455 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 81342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 296410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 371915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 76302 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 288473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 437106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1575250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 81342 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 76302 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 157645 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1913014 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1244591 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 89341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 270667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 293282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 55868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 241418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 346767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1318075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 89341 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 55868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 145209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1677540 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1913448 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1913014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 81342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 296844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 371915 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 76302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 288473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 437106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3488697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1184383 # Number of read requests accepted -system.physmem.writeReqs 1421455 # Number of write requests accepted -system.physmem.readBursts 1184383 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1421455 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 75776512 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 24000 # Total number of bytes read from write queue -system.physmem.bytesWritten 90827456 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 74775128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 90828968 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 375 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1677974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1677540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 89341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 271101 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 293282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 55868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 241418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 346767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2996050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 991898 # Number of read requests accepted +system.physmem.writeReqs 1244591 # Number of write requests accepted +system.physmem.readBursts 991898 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1244591 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 63457600 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 23872 # Total number of bytes read from write queue +system.physmem.bytesWritten 79508544 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62456088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 79509672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 373 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 72103 # Per bank write bursts -system.physmem.perBankRdBursts::1 78803 # Per bank write bursts -system.physmem.perBankRdBursts::2 72464 # Per bank write bursts -system.physmem.perBankRdBursts::3 70552 # Per bank write bursts -system.physmem.perBankRdBursts::4 69846 # Per bank write bursts -system.physmem.perBankRdBursts::5 79143 # Per bank write bursts -system.physmem.perBankRdBursts::6 69266 # Per bank write bursts -system.physmem.perBankRdBursts::7 70722 # Per bank write bursts -system.physmem.perBankRdBursts::8 68903 # Per bank write bursts -system.physmem.perBankRdBursts::9 99020 # Per bank write bursts -system.physmem.perBankRdBursts::10 71711 # Per bank write bursts -system.physmem.perBankRdBursts::11 73604 # Per bank write bursts -system.physmem.perBankRdBursts::12 71852 # Per bank write bursts -system.physmem.perBankRdBursts::13 74765 # Per bank write bursts -system.physmem.perBankRdBursts::14 70123 # Per bank write bursts -system.physmem.perBankRdBursts::15 71131 # Per bank write bursts -system.physmem.perBankWrBursts::0 89065 # Per bank write bursts -system.physmem.perBankWrBursts::1 93300 # Per bank write bursts -system.physmem.perBankWrBursts::2 85781 # Per bank write bursts -system.physmem.perBankWrBursts::3 86502 # Per bank write bursts -system.physmem.perBankWrBursts::4 86907 # Per bank write bursts -system.physmem.perBankWrBursts::5 92159 # Per bank write bursts -system.physmem.perBankWrBursts::6 86239 # Per bank write bursts -system.physmem.perBankWrBursts::7 88123 # Per bank write bursts -system.physmem.perBankWrBursts::8 85047 # Per bank write bursts -system.physmem.perBankWrBursts::9 93098 # Per bank write bursts -system.physmem.perBankWrBursts::10 87729 # Per bank write bursts -system.physmem.perBankWrBursts::11 90867 # Per bank write bursts -system.physmem.perBankWrBursts::12 86341 # Per bank write bursts -system.physmem.perBankWrBursts::13 90891 # Per bank write bursts -system.physmem.perBankWrBursts::14 88902 # Per bank write bursts -system.physmem.perBankWrBursts::15 88228 # Per bank write bursts +system.physmem.perBankRdBursts::0 57534 # Per bank write bursts +system.physmem.perBankRdBursts::1 67322 # Per bank write bursts +system.physmem.perBankRdBursts::2 57239 # Per bank write bursts +system.physmem.perBankRdBursts::3 59640 # Per bank write bursts +system.physmem.perBankRdBursts::4 58543 # Per bank write bursts +system.physmem.perBankRdBursts::5 68655 # Per bank write bursts +system.physmem.perBankRdBursts::6 57471 # Per bank write bursts +system.physmem.perBankRdBursts::7 60839 # Per bank write bursts +system.physmem.perBankRdBursts::8 60208 # Per bank write bursts +system.physmem.perBankRdBursts::9 81942 # Per bank write bursts +system.physmem.perBankRdBursts::10 59318 # Per bank write bursts +system.physmem.perBankRdBursts::11 61436 # Per bank write bursts +system.physmem.perBankRdBursts::12 60309 # Per bank write bursts +system.physmem.perBankRdBursts::13 62906 # Per bank write bursts +system.physmem.perBankRdBursts::14 58748 # Per bank write bursts +system.physmem.perBankRdBursts::15 59415 # Per bank write bursts +system.physmem.perBankWrBursts::0 74024 # Per bank write bursts +system.physmem.perBankWrBursts::1 81724 # Per bank write bursts +system.physmem.perBankWrBursts::2 74878 # Per bank write bursts +system.physmem.perBankWrBursts::3 76858 # Per bank write bursts +system.physmem.perBankWrBursts::4 76593 # Per bank write bursts +system.physmem.perBankWrBursts::5 82864 # Per bank write bursts +system.physmem.perBankWrBursts::6 74278 # Per bank write bursts +system.physmem.perBankWrBursts::7 78173 # Per bank write bursts +system.physmem.perBankWrBursts::8 76626 # Per bank write bursts +system.physmem.perBankWrBursts::9 80136 # Per bank write bursts +system.physmem.perBankWrBursts::10 77163 # Per bank write bursts +system.physmem.perBankWrBursts::11 80655 # Per bank write bursts +system.physmem.perBankWrBursts::12 76245 # Per bank write bursts +system.physmem.perBankWrBursts::13 79687 # Per bank write bursts +system.physmem.perBankWrBursts::14 75064 # Per bank write bursts +system.physmem.perBankWrBursts::15 77353 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 43 # Number of times write queue was full causing retry -system.physmem.totGap 47468750370500 # Total gap between requests +system.physmem.numWrRetry 51477 # Number of times write queue was full causing retry +system.physmem.totGap 47384313590500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1163025 # Read request sizes (log2) +system.physmem.readPktSize::6 970540 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1418881 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 512770 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 308725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 87137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 63943 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 45149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 40149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 37001 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 34987 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 30693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 8585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4718 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1609 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1005 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 765 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1242017 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 445378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 243433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 76996 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 56880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 37150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 31949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 29173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 27068 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 25124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 6848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3836 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 708 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -188,162 +188,135 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 49676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 56919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 67754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 74407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 81101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 85167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 89920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 95633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 94983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 99480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 111361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 98562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 89368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 83432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 13050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 9803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 105 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1159540 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 143.680535 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 97.586865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 190.741453 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 783407 67.56% 67.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 222260 19.17% 86.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 55727 4.81% 91.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 24890 2.15% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 21192 1.83% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11987 1.03% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8178 0.71% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4967 0.43% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 26932 2.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1159540 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 67946 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.425117 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 68.584486 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 67943 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 23188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 36083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 41131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 48159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 53054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 57269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 63720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 68707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 72599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 69938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 72538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 82492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 73770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 67397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 63055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 6136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 24445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 120872 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 982131 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 145.566960 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.657532 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 193.069606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 654413 66.63% 66.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 194527 19.81% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 50477 5.14% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21176 2.16% 93.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 16419 1.67% 95.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9395 0.96% 96.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6596 0.67% 97.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5289 0.54% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23839 2.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 982131 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 56922 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.418608 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 74.895923 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 56917 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 67946 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 67946 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.886866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.982744 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 74.693624 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-127 67692 99.63% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-255 167 0.25% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-383 12 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-511 13 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-639 10 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-767 5 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::768-895 6 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::896-1023 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1024-1151 3 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1152-1279 3 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1280-1407 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1408-1535 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1536-1663 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1664-1791 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1792-1919 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1920-2047 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2048-2175 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2176-2303 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2432-2559 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2560-2687 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2688-2815 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2944-3071 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3072-3199 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3200-3327 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3584-3711 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3840-3967 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3968-4095 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4224-4351 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4736-4863 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5760-5887 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6528-6655 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 67946 # Writes before turning the bus around for reads -system.physmem.totQLat 53444908202 # Total ticks spent queuing -system.physmem.totMemAccLat 75645058202 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5920040000 # Total ticks spent in databus transfers -system.physmem.avgQLat 45138.98 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 56922 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 56922 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.824971 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.750218 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 638.100533 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-4095 56920 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45056-49151 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 56922 # Writes before turning the bus around for reads +system.physmem.totQLat 43578574020 # Total ticks spent queuing +system.physmem.totMemAccLat 62169667770 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4957625000 # Total ticks spent in databus transfers +system.physmem.avgQLat 43951.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 63888.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.60 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.91 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.91 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 62701.06 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.68 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.68 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.70 # Average write queue length when enqueuing -system.physmem.readRowHits 894156 # Number of row buffer hits during reads -system.physmem.writeRowHits 549489 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.72 # Row buffer hit rate for writes -system.physmem.avgGap 18216309.06 # Average gap between requests -system.physmem.pageHitRate 55.46 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4374828360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2387059125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4546612200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4588332480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3100427903040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1181604436515 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27444754155000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31742683326720 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.706973 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45656629611476 # Time in different power states -system.physmem_0.memoryStateTime::REF 1585085840000 # Time in different power states +system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.75 # Average write queue length when enqueuing +system.physmem.readRowHits 750886 # Number of row buffer hits during reads +system.physmem.writeRowHits 500828 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.31 # Row buffer hit rate for writes +system.physmem.avgGap 21186920.03 # Average gap between requests +system.physmem.pageHitRate 56.03 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3717395640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2028340875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3800456400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4013660160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3094913078400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1158326321940 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27414513105000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31681312358415 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.603367 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45606511009457 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582266400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 227033353524 # Time in different power states +system.physmem_0.memoryStateTime::ACT 195537314293 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4391294040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2396043375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4688572200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4607947440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3100427903040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1183305976290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27443261584500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31743079320885 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.715315 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45654123959514 # Time in different power states -system.physmem_1.memoryStateTime::REF 1585085840000 # Time in different power states +system.physmem_1.actEnergy 3707514720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2022949500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3933399600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4036579920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3094913078400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1156667621085 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27415968105750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31681249248975 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.602035 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45608919765384 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582266400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 229539287986 # Time in different power states +system.physmem_1.memoryStateTime::ACT 193128558366 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -377,19 +350,19 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 132444225 # Number of BP lookups -system.cpu0.branchPred.condPredicted 87787955 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6400754 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 93524644 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 57612051 # Number of BTB hits +system.cpu0.branchPred.lookups 138091637 # Number of BP lookups +system.cpu0.branchPred.condPredicted 91311717 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6789940 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 97223509 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 59866310 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 61.600931 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17778768 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 168825 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4144770 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2586947 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1557823 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 392899 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 61.575961 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 18644167 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 188685 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4389066 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2747803 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1641263 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 409141 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -420,85 +393,88 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 539802 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 539802 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11294 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84152 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 248635 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 291167 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2569.659336 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 15605.583986 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 288567 99.11% 99.11% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1409 0.48% 99.59% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 865 0.30% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 174 0.06% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 52 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 75 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 18 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 291167 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 273980 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 20501.036572 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17496.757374 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 20192.590719 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 271123 98.96% 98.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 705 0.26% 99.21% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1540 0.56% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 149 0.05% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 269 0.10% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 86 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 62 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 25 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 273980 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 529053057016 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.549473 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.550536 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 527876290016 99.78% 99.78% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 603631000 0.11% 99.89% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 259797000 0.05% 99.94% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 123836500 0.02% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 92525500 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 56948500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 16655000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 23145000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 228500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 529053057016 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 84152 88.17% 88.17% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11294 11.83% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 95446 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 539802 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 530338 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 530338 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10426 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79784 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 241995 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 288343 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2099.123266 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 12230.418976 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 286535 99.37% 99.37% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1269 0.44% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 337 0.12% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 138 0.05% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 37 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 22 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 288343 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 261783 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 19021.382214 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 16878.246550 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 10891.763559 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 246122 94.02% 94.02% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 14409 5.50% 99.52% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 656 0.25% 99.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 427 0.16% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 44 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 47 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 25 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 22 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 261783 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 513336492752 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.609866 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.537961 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 512309669252 99.80% 99.80% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 522001000 0.10% 99.90% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 221126000 0.04% 99.94% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 109873500 0.02% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 86703000 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 51185000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 14405500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 21121500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 397500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 10500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 513336492752 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 79785 88.44% 88.44% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10426 11.56% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 90211 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 530338 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 539802 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 95446 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 530338 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90211 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 95446 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 635248 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90211 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 620549 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 96092667 # DTB read hits -system.cpu0.dtb.read_misses 371231 # DTB read misses -system.cpu0.dtb.write_hits 80108557 # DTB write hits -system.cpu0.dtb.write_misses 168571 # DTB write misses -system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 99690232 # DTB read hits +system.cpu0.dtb.read_misses 367422 # DTB read misses +system.cpu0.dtb.write_hits 83046551 # DTB write hits +system.cpu0.dtb.write_misses 162916 # DTB write misses +system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 46091 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1084 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 35125 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 346 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 6813 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 35541 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 482 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 6442 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 38936 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 96463898 # DTB read accesses -system.cpu0.dtb.write_accesses 80277128 # DTB write accesses +system.cpu0.dtb.perms_faults 39704 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 100057654 # DTB read accesses +system.cpu0.dtb.write_accesses 83209467 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 176201224 # DTB hits -system.cpu0.dtb.misses 539802 # DTB misses -system.cpu0.dtb.accesses 176741026 # DTB accesses +system.cpu0.dtb.hits 182736783 # DTB hits +system.cpu0.dtb.misses 530338 # DTB misses +system.cpu0.dtb.accesses 183267121 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -528,1164 +504,1165 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 79903 # Table walker walks requested -system.cpu0.itb.walker.walksLong 79903 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 950 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 57315 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 9653 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 70250 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1248.284698 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 10855.060811 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-65535 69985 99.62% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-131071 65 0.09% 99.72% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-196607 177 0.25% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-262143 11 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-393215 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 70250 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 67918 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26250.242940 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 22828.736245 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 25780.781063 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 66522 97.94% 97.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 103 0.15% 98.10% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1066 1.57% 99.67% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 71 0.10% 99.77% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 86 0.13% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 28 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 25 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 8 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 67918 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 408740768228 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.873449 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.332683 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 51752271292 12.66% 12.66% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 356965086936 87.33% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 21879500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 1303500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 81500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 52500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 29500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::7 1000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::8 62500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 408740768228 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 57315 98.37% 98.37% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 950 1.63% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 58265 # Table walker page sizes translated +system.cpu0.itb.walker.walks 81834 # Table walker walks requested +system.cpu0.itb.walker.walksLong 81834 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1030 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58824 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 9805 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 72029 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 864.033931 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 6165.525550 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 71606 99.41% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 296 0.41% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 49 0.07% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 70 0.10% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 72029 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 69659 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 23684.893553 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 21955.996989 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 12765.700584 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 63811 91.60% 91.60% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 5242 7.53% 99.13% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 100 0.14% 99.27% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 402 0.58% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 39 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 8 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 69659 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 375894589280 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.860066 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.347066 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 52618427692 14.00% 14.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 323259257588 86.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 15893500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 943500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 54500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 12500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 375894589280 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 58824 98.28% 98.28% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1030 1.72% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 59854 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 79903 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 79903 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 81834 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 81834 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58265 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58265 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 138168 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 207793696 # ITB inst hits -system.cpu0.itb.inst_misses 79903 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59854 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59854 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 141688 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 216521473 # ITB inst hits +system.cpu0.itb.inst_misses 81834 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 46091 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1084 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24840 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 25342 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 191050 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 198402 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 207873599 # ITB inst accesses -system.cpu0.itb.hits 207793696 # DTB hits -system.cpu0.itb.misses 79903 # DTB misses -system.cpu0.itb.accesses 207873599 # DTB accesses -system.cpu0.numCycles 761315266 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 216603307 # ITB inst accesses +system.cpu0.itb.hits 216521473 # DTB hits +system.cpu0.itb.misses 81834 # DTB misses +system.cpu0.itb.accesses 216603307 # DTB accesses +system.cpu0.numCycles 746014900 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 84074114 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 585063894 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 132444225 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 77977766 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 631770796 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13765762 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1785587 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 318737 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 5559321 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 752999 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 796339 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 207603742 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1586738 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 26136 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 731940774 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.936268 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.209570 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 90433879 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 610172736 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 138091637 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81258280 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 615398287 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14620490 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1715297 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 295776 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 5589619 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 711520 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 813110 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 216323861 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1696724 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 26704 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 722267733 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.989116 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.222569 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 403543312 55.13% 55.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 128205713 17.52% 72.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 43488128 5.94% 78.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 156703621 21.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 380266002 52.65% 52.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 133082578 18.43% 71.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 45433566 6.29% 77.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 163485587 22.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 731940774 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.173968 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.768491 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 100319911 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 372509653 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 217857253 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 36338079 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 4915878 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 18873695 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2004301 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 606758178 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 22350639 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 4915878 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 134368949 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 57393762 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 239367965 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 219640614 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 76253606 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 590337881 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 5891778 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 10879657 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 272900 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 275104 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 42478331 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 10735 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 562575259 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 912365987 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 697390419 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 694396 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 507972674 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 54602579 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15164295 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13334098 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 72899123 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 96066209 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 83257958 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 8637114 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 7533431 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 568637659 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15304177 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 573527019 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2573483 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 51469570 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 33194366 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 252301 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 731940774 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.783570 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.057506 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 722267733 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.185106 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.817910 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 106050198 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 344087060 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 231125881 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 35774912 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5229682 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19752919 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2120005 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 632519077 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 23747295 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5229682 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 140879480 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 46445701 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 235545365 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 231642525 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 62524980 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 614970268 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6274841 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 9683853 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 239254 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 254272 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 29219197 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11058 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 585821211 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 944611426 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 725501320 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 860588 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 527918401 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 57902804 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 14873386 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 12932012 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 72326353 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 100125445 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 86327833 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 8833111 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 7713299 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 593239093 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 14925406 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 596650262 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2740149 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 54305512 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 35087941 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 259840 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 722267733 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.826079 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.071801 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 419086912 57.26% 57.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 131041268 17.90% 75.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 110621862 15.11% 90.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 63525040 8.68% 98.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 7661553 1.05% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 4139 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 398653423 55.19% 55.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 132668388 18.37% 73.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 116695962 16.16% 89.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 66414173 9.20% 98.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 7831504 1.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 4283 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 731940774 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 722267733 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 59257381 45.13% 45.13% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 46667 0.04% 45.16% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 17941 0.01% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 17 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 34285997 26.11% 71.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 37701656 28.71% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 62572261 45.86% 45.86% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 47637 0.03% 45.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 27538 0.02% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 12 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 35025206 25.67% 71.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 38780691 28.42% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 17 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 391712029 68.30% 68.30% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1330798 0.23% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 69152 0.01% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 6 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.54% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 42956 0.01% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 99049842 17.27% 85.82% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 81322170 14.18% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 37 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 408003074 68.38% 68.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1391206 0.23% 68.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 75246 0.01% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 5 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 75513 0.01% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 102801955 17.23% 85.87% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 84303178 14.13% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 573527019 # Type of FU issued -system.cpu0.iq.rate 0.753337 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 131309659 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228951 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2011763518 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 635110276 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 556950573 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1114436 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 438215 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 411063 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 704141671 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 694990 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2575949 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 596650262 # Type of FU issued +system.cpu0.iq.rate 0.799783 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 136453345 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228699 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2053360508 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 662051351 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 579495604 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1401241 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 556367 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 521179 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 732235238 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 868332 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2674563 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 11750995 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 17228 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 138196 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5318019 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 12322480 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 16225 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 138716 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5498195 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2553185 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4584143 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2627025 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4349073 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 4915878 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6708218 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 2698388 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 584066483 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5229682 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6015766 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1577054 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 608291813 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 96066209 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 83257958 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13102761 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 64235 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2566402 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 138196 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 1807441 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2958148 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 4765589 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 565930325 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 96085763 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7069222 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 100125445 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 86327833 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 12661031 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 57348 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1462300 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 138716 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 1920652 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3139987 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5060639 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 588583301 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 99681195 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7546532 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 124647 # number of nop insts executed -system.cpu0.iew.exec_refs 176196325 # number of memory reference insts executed -system.cpu0.iew.exec_branches 106580080 # Number of branches executed -system.cpu0.iew.exec_stores 80110562 # Number of stores executed -system.cpu0.iew.exec_rate 0.743359 # Inst execution rate -system.cpu0.iew.wb_sent 558072531 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 557361636 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 269759058 # num instructions producing a value -system.cpu0.iew.wb_consumers 442874225 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.732104 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609110 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 44855365 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15051876 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4433751 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 723417587 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.736051 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.544488 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 127314 # number of nop insts executed +system.cpu0.iew.exec_refs 182727665 # number of memory reference insts executed +system.cpu0.iew.exec_branches 110905985 # Number of branches executed +system.cpu0.iew.exec_stores 83046470 # Number of stores executed +system.cpu0.iew.exec_rate 0.788970 # Inst execution rate +system.cpu0.iew.wb_sent 580785082 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 580016783 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 281571835 # num instructions producing a value +system.cpu0.iew.wb_consumers 462036259 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.777487 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609415 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 47239068 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 14665566 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4709377 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 713265593 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.776512 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.575400 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 490442876 67.80% 67.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 120876307 16.71% 84.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 51465837 7.11% 91.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 17138323 2.37% 93.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 12635808 1.75% 95.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 8409902 1.16% 96.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5731195 0.79% 97.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3469312 0.48% 98.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 13248027 1.83% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 472345396 66.22% 66.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 122854697 17.22% 83.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 54352038 7.62% 91.07% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 18530727 2.60% 93.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13156863 1.84% 95.51% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 8843989 1.24% 96.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 5973723 0.84% 97.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3646989 0.51% 98.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 13561171 1.90% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 723417587 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 452974919 # Number of instructions committed -system.cpu0.commit.committedOps 532472262 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 713265593 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 471410910 # Number of instructions committed +system.cpu0.commit.committedOps 553858980 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 162255152 # Number of memory references committed -system.cpu0.commit.loads 84315213 # Number of loads committed -system.cpu0.commit.membars 3606698 # Number of memory barriers committed -system.cpu0.commit.branches 101352780 # Number of branches committed -system.cpu0.commit.fp_insts 403239 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 488332622 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13274605 # Number of function calls committed. +system.cpu0.commit.refs 168632602 # Number of memory references committed +system.cpu0.commit.loads 87802964 # Number of loads committed +system.cpu0.commit.membars 3653468 # Number of memory barriers committed +system.cpu0.commit.branches 105429162 # Number of branches committed +system.cpu0.commit.fp_insts 512997 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 508174699 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13889214 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 369012489 69.30% 69.30% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1112277 0.21% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 54460 0.01% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 37842 0.01% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 84315213 15.83% 85.36% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 77939939 14.64% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 383941234 69.32% 69.32% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1156077 0.21% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 59954 0.01% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 69071 0.01% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 87802964 15.85% 85.41% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 80829638 14.59% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 532472262 # Class of committed instruction -system.cpu0.commit.bw_lim_events 13248027 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1283601950 # The number of ROB reads -system.cpu0.rob.rob_writes 1163144719 # The number of ROB writes -system.cpu0.timesIdled 940575 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 29374492 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 94176188727 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 452974919 # Number of Instructions Simulated -system.cpu0.committedOps 532472262 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.680701 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.680701 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.594990 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.594990 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 668586496 # number of integer regfile reads -system.cpu0.int_regfile_writes 395947855 # number of integer regfile writes -system.cpu0.fp_regfile_reads 683579 # number of floating regfile reads -system.cpu0.fp_regfile_writes 295852 # number of floating regfile writes -system.cpu0.cc_regfile_reads 123538962 # number of cc regfile reads -system.cpu0.cc_regfile_writes 124272565 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1278649841 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15273032 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 5802522 # number of replacements -system.cpu0.dcache.tags.tagsinuse 485.093904 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 150368529 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5803033 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 25.912058 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.093904 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947449 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.947449 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 553858980 # Class of committed instruction +system.cpu0.commit.bw_lim_events 13561171 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1296549352 # The number of ROB reads +system.cpu0.rob.rob_writes 1211163120 # The number of ROB writes +system.cpu0.timesIdled 982435 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 23747167 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 94022615466 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 471410910 # Number of Instructions Simulated +system.cpu0.committedOps 553858980 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.582515 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.582515 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.631905 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.631905 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 694459704 # number of integer regfile reads +system.cpu0.int_regfile_writes 413089219 # number of integer regfile writes +system.cpu0.fp_regfile_reads 846069 # number of floating regfile reads +system.cpu0.fp_regfile_writes 429660 # number of floating regfile writes +system.cpu0.cc_regfile_reads 127998327 # number of cc regfile reads +system.cpu0.cc_regfile_writes 128742208 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1288788249 # number of misc regfile reads +system.cpu0.misc_regfile_writes 14832406 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 5793916 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.305765 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 157106373 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5794427 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.113358 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.305765 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986925 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986925 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 336490622 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 336490622 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 77978502 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77978502 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67507915 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 67507915 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199394 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 199394 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 171803 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 171803 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1821693 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1821693 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1835435 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1835435 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 145658220 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 145658220 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 145857614 # number of overall hits -system.cpu0.dcache.overall_hits::total 145857614 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6410027 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6410027 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7429665 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7429665 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 719434 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 719434 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 793389 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 793389 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 238145 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 238145 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 190782 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 190782 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 14633081 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 14633081 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 15352515 # number of overall misses -system.cpu0.dcache.overall_misses::total 15352515 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 109062490500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 109062490500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 171373805000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 171373805000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 50210173040 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 50210173040 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3622154000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3622154000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5311494500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5311494500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5825000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5825000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 330646468540 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 330646468540 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 330646468540 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 330646468540 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 84388529 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 84388529 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74937580 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74937580 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 918828 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 918828 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 965192 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 965192 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2059838 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2059838 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2026217 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2026217 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 160291301 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 160291301 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 161210129 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 161210129 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075959 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.075959 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.099145 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.099145 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.782991 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.782991 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.822001 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.822001 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.115613 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.115613 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.094157 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.094157 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.091291 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.091291 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.095233 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.095233 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17014.357428 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17014.357428 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23066.155069 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23066.155069 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 63285.693449 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 63285.693449 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15209.867938 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15209.867938 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27840.647965 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27840.647965 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 349540400 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 349540400 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 81616032 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 81616032 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 70522769 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 70522769 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213045 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 213045 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259663 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 259663 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1810689 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1810689 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1836259 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1836259 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 152398464 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 152398464 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 152611509 # number of overall hits +system.cpu0.dcache.overall_hits::total 152611509 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6448823 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6448823 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7191873 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7191873 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 676181 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 676181 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 810826 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 810826 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 247493 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 247493 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 187335 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 187335 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 14451522 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 14451522 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 15127703 # number of overall misses +system.cpu0.dcache.overall_misses::total 15127703 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 92981912000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 92981912000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 133998931168 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 133998931168 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29936196189 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 29936196189 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3415607500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3415607500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4687136000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4687136000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3788500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3788500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 256917039357 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 256917039357 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 256917039357 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 256917039357 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 88064855 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 88064855 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 77714642 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 77714642 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 889226 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 889226 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1070489 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1070489 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2058182 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2058182 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2023594 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2023594 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 166849986 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 166849986 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 167739212 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 167739212 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.073228 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.073228 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.092542 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.092542 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760415 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760415 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.757435 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.757435 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.120248 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.120248 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092575 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092575 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086614 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.086614 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.090186 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.090186 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14418.431394 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14418.431394 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18631.993525 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18631.993525 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 36920.616987 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 36920.616987 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13800.824670 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13800.824670 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25020.076334 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25020.076334 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22595.820288 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22595.820288 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21536.957856 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21536.957856 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 15517119 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 25638833 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 732854 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 730129 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.173548 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 35.115484 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5802538 # number of writebacks -system.cpu0.dcache.writebacks::total 5802538 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3327729 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3327729 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5970882 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 5970882 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4398 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4398 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 123286 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 123286 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9303009 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9303009 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9303009 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9303009 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3082298 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3082298 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1458783 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1458783 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 712505 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 712505 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 788991 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 788991 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 114859 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 114859 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 190777 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 190777 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5330072 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5330072 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 6042577 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 6042577 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 19706 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19706 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 21266 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 21266 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40972 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40972 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48302897000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 48302897000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39166129612 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 39166129612 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 19342072500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 19342072500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 49145395540 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 49145395540 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1672767500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1672767500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5120787500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5120787500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5755000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5755000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 136614422152 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 136614422152 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 155956494652 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 155956494652 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3863694500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3863694500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3863694500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3863694500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036525 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036525 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019467 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019467 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775450 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775450 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.817445 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.817445 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055761 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055761 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.094154 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.094154 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033252 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033252 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037483 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.037483 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15671.066522 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15671.066522 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26848.496049 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26848.496049 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27146.577919 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27146.577919 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 62288.917795 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 62288.917795 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14563.660662 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14563.660662 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26841.744550 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26841.744550 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17777.853389 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17777.853389 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16983.215453 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16983.215453 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9060649 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 19650869 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 747322 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 698056 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.124157 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 28.150849 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 5793928 # number of writebacks +system.cpu0.dcache.writebacks::total 5793928 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3323367 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3323367 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5758852 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 5758852 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4670 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4670 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 128237 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 128237 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9086889 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9086889 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9086889 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9086889 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3125456 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3125456 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1433021 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1433021 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 669278 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 669278 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 806156 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 806156 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 119256 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 119256 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 187331 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 187331 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5364633 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5364633 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6033911 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6033911 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32527 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32527 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32351 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32351 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 64878 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 64878 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43142423000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43142423000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30169010620 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30169010620 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14964455000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14964455000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28947099689 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28947099689 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564593500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564593500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4499876000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4499876000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3717500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3717500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102258533309 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 102258533309 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 117222988309 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 117222988309 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6208668000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6208668000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6208668000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6208668000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035490 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035490 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018440 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018440 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.752652 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752652 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.753073 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.753073 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057942 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057942 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092573 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092573 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032152 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032152 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035972 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.035972 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13803.561144 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13803.561144 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21052.734482 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21052.734482 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22359.101898 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22359.101898 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 35907.565892 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 35907.565892 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13119.620816 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13119.620816 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24020.989585 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24020.989585 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25630.877435 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25630.877435 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25809.599886 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25809.599886 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196066.908556 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196066.908556 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 94300.851801 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 94300.851801 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 5681079 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.944679 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 201561746 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5681591 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.476286 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 18014203000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.944679 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999892 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999892 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19061.608373 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19061.608373 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19427.364492 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19427.364492 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190877.363421 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190877.363421 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95697.586239 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95697.586239 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 6136519 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.962391 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 209807209 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6137031 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.187086 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 12886295000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962391 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999927 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 420833426 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 420833426 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 201561746 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 201561746 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 201561746 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 201561746 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 201561746 # number of overall hits -system.cpu0.icache.overall_hits::total 201561746 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6014149 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6014149 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6014149 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6014149 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6014149 # 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average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 11404.019027 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11404.019027 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11404.019027 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10444384 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1542 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 695799 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.010634 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 118.615385 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 5681079 # number of writebacks -system.cpu0.icache.writebacks::total 5681079 # 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number of overall MSHR misses +system.cpu0.icache.tags.tag_accesses 438728804 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 438728804 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 209807209 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 209807209 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 209807209 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 209807209 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 209807209 # number of overall hits +system.cpu0.icache.overall_hits::total 209807209 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6488653 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6488653 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6488653 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6488653 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6488653 # number of overall misses +system.cpu0.icache.overall_misses::total 6488653 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 69596700450 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 69596700450 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 69596700450 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 69596700450 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 69596700450 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 69596700450 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 216295862 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 216295862 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 216295862 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 216295862 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 216295862 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 216295862 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029999 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029999 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029999 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029999 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029999 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029999 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10725.908821 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10725.908821 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10725.908821 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10725.908821 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10725.908821 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10725.908821 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 10132412 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 737599 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.737020 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 48.444444 # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 6136519 # number of writebacks +system.cpu0.icache.writebacks::total 6136519 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 351573 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 351573 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 351573 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 351573 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 351573 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 351573 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6137080 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6137080 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6137080 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6137080 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6137080 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6137080 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 61685306454 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 61685306454 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 61685306454 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 61685306454 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 61685306454 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 61685306454 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939780498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939780498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939780498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027371 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027371 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027371 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.027371 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027371 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.027371 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10856.962054 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10856.962054 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10856.962054 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10856.962054 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10856.962054 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10856.962054 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.236651 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.236651 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.236651 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.236651 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7915167 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7926437 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 10130 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62984871633 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 62984871633 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62984871633 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 62984871633 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62984871633 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 62984871633 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1885677498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1885677498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028374 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028374 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028374 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10263.003193 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7743703 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7754051 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 9277 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1009963 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2664029 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16072.729216 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 16415073 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2680041 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.124934 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 3423391000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14987.796585 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 47.087094 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 49.541309 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 988.304228 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.914783 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002874 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003024 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.060321 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.981002 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1464 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14480 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 48 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 590 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 290 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 526 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 10 # 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mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021375 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046070 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.098631 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.253963 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.162774 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021375 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046070 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.098631 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.253963 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231953 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231953 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.093508 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093508 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.247573 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247573 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.747519 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.747519 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.019556 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.039775 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.093508 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.243943 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.153253 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.019556 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.039775 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.093508 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.243943 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.232345 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 47059.326253 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 45780.002308 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 46524.206004 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 71210.429271 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 71210.429271 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29077.941831 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29077.941831 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19327.799487 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19327.799487 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 871500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 871500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 59061.823294 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 59061.823294 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33530.157161 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33530.157161 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36936.760880 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36936.760880 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70704.254236 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70704.254236 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 47059.326253 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 45780.002308 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33530.157161 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41701.755914 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39318.158299 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47059.326253 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 45780.002308 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33530.157161 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41701.755914 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 71210.429271 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48867.682111 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188040.393789 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158189.370472 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 90440.398321 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104161.342648 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 23859843 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12280153 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1945 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 2008292 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2007802 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 490 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 875651 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 10557046 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 21267 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 21266 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5532941 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 7629125 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2654810 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1033772 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 476440 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348822 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 520615 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1237465 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1213308 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5681636 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4942147 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 844889 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 786739 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17086897 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18759020 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 394013 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1192566 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 37432496 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 727551888 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 705113777 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1504832 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4510600 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1438681097 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 7112172 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 19795414 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.118782 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.323609 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.217839 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27568.864230 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46845.335420 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46845.335420 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20843.655320 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20843.655320 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16505.909731 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16505.909731 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 454785.571429 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 454785.571429 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40291.912662 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40291.912662 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28979.940194 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28953.724719 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28953.724719 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36518.816670 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36518.816670 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31458.731460 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30644.561078 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31458.731460 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46845.335420 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35447.837007 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182858.994066 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142583.305463 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91677.525509 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89053.550498 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 24754475 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12719207 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1997962 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1997498 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 464 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 885324 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11040535 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 32352 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32351 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5471965 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 8067317 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2568559 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 991385 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 10 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 475065 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 341372 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 522361 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 76 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1216718 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1192935 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6137080 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4901216 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 866556 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 803970 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18453192 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18807742 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 402695 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1170958 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 38834587 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 785846352 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 704525389 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1531416 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4405792 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1496308949 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6903738 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 20024554 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.116908 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.321383 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 17444556 88.12% 88.12% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2350368 11.87% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 490 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 17683990 88.31% 88.31% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2340100 11.69% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 464 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 19795414 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 23702360441 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 185100538 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 20024554 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 24612511939 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 212521499 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 8549815301 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9233457820 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8326796053 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8324768239 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 206206896 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 211573883 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 629446573 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 620908635 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 144214101 # Number of BP lookups -system.cpu1.branchPred.condPredicted 95658264 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 7037471 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 101536339 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 63283833 # Number of BTB hits +system.cpu1.branchPred.lookups 127244460 # Number of BP lookups +system.cpu1.branchPred.condPredicted 83927531 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6411720 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 89791062 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 55539581 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 62.326290 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 19487906 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 205159 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 4571638 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2870819 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1700819 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 415354 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 61.854242 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17406269 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 177185 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 4036084 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2495247 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1540837 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 386993 # Number of mispredicted indirect branches. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1715,89 +1692,83 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 655828 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 655828 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 14723 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 107099 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 315531 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 340297 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2456.990511 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 14831.918999 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 337419 99.15% 99.15% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1530 0.45% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 1096 0.32% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 124 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 45 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 65 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 10 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::786432-851967 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 340297 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 353965 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 21023.430283 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17819.927272 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 22140.509228 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 349562 98.76% 98.76% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1039 0.29% 99.05% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 2363 0.67% 99.72% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 142 0.04% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 520 0.15% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 154 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 109 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 57 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 353965 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 524755655220 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.627277 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.547876 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 523184603720 99.70% 99.70% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 876126000 0.17% 99.87% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 338256000 0.06% 99.93% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 142712500 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 110713000 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 57399000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 19068500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 26227000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 540000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 6500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-21 1500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::22-23 1500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 524755655220 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 107100 87.91% 87.91% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 14723 12.09% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 121823 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 655828 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 579824 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 579824 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12232 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93540 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 278610 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 301214 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2385.289196 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 13264.000730 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 298702 99.17% 99.17% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1877 0.62% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 425 0.14% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 126 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 47 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 33 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 301214 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 311038 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 20491.173104 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17661.433181 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 17134.136599 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 306887 98.67% 98.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 3006 0.97% 99.63% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 404 0.13% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 531 0.17% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 109 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 60 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 29 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 311038 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 427436234332 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.596252 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.559035 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 426093627832 99.69% 99.69% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 733360500 0.17% 99.86% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 289523500 0.07% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 124054000 0.03% 99.95% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 101131500 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 55199000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 17877500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 20812500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 638500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 9500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 427436234332 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 93540 88.44% 88.44% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 12232 11.56% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 105772 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 579824 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 655828 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 121823 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 579824 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105772 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 121823 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 777651 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105772 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 685596 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 106468062 # DTB read hits -system.cpu1.dtb.read_misses 473211 # DTB read misses -system.cpu1.dtb.write_hits 85858726 # DTB write hits -system.cpu1.dtb.write_misses 182617 # DTB write misses -system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 94100008 # DTB read hits +system.cpu1.dtb.read_misses 416726 # DTB read misses +system.cpu1.dtb.write_hits 75732153 # DTB write hits +system.cpu1.dtb.write_misses 163098 # DTB write misses +system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 46091 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1084 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 44338 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 492 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 7273 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 40949 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 397 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6052 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 40937 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 106941273 # DTB read accesses -system.cpu1.dtb.write_accesses 86041343 # DTB write accesses +system.cpu1.dtb.perms_faults 38110 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 94516734 # DTB read accesses +system.cpu1.dtb.write_accesses 75895251 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 192326788 # DTB hits -system.cpu1.dtb.misses 655828 # DTB misses -system.cpu1.dtb.accesses 192982616 # DTB accesses +system.cpu1.dtb.hits 169832161 # DTB hits +system.cpu1.dtb.misses 579824 # DTB misses +system.cpu1.dtb.accesses 170411985 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1827,1148 +1798,1151 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 90500 # Table walker walks requested -system.cpu1.itb.walker.walksLong 90500 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1174 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 63013 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 10919 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 79581 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1858.653447 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 14270.720139 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-65535 78947 99.20% 99.20% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-131071 217 0.27% 99.48% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-196607 367 0.46% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-262143 26 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-327679 15 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 79581 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 75106 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 27703.186164 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23129.879308 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 30256.665627 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 72610 96.68% 96.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 191 0.25% 96.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1968 2.62% 99.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 115 0.15% 99.70% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 133 0.18% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 46 0.06% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 16 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 75106 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 438856254800 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.887236 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.316700 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 49536953716 11.29% 11.29% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 389273644084 88.70% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 42101500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 2811500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 744000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 438856254800 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 63013 98.17% 98.17% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 1174 1.83% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 64187 # Table walker page sizes translated +system.cpu1.itb.walker.walks 86146 # Table walker walks requested +system.cpu1.itb.walker.walksLong 86146 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 983 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61109 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 10267 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 75879 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1365.727013 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 9905.301438 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 74992 98.83% 98.83% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 442 0.58% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 265 0.35% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 132 0.17% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 11 0.01% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 75879 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 72359 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25927.458920 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22905.536509 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 21012.178040 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 70191 97.00% 97.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1833 2.53% 99.54% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 132 0.18% 99.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 128 0.18% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 41 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 21 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 7 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 72359 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 388687033168 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.860499 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.346749 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 54258161808 13.96% 13.96% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 334394621860 86.03% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 32560000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1626500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 63000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 388687033168 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 61109 98.42% 98.42% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 983 1.58% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 62092 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 90500 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 90500 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 86146 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 86146 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 64187 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 64187 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 154687 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 226870355 # ITB inst hits -system.cpu1.itb.inst_misses 90500 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62092 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62092 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 148238 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 200179962 # ITB inst hits +system.cpu1.itb.inst_misses 86146 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 46091 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1084 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 32400 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 29991 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 223247 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 205105 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 226960855 # ITB inst accesses -system.cpu1.itb.hits 226870355 # DTB hits -system.cpu1.itb.misses 90500 # DTB misses -system.cpu1.itb.accesses 226960855 # DTB accesses -system.cpu1.numCycles 812532558 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 200266108 # ITB inst accesses +system.cpu1.itb.hits 200179962 # DTB hits +system.cpu1.itb.misses 86146 # DTB misses +system.cpu1.itb.accesses 200266108 # DTB accesses +system.cpu1.numCycles 683375860 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 91759705 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 638580491 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 144214101 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 85642558 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 676433492 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 15215298 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2168545 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 336979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 6484962 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 887415 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 890942 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 226625049 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1736948 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 29701 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 786569689 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.951781 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.213726 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 83886783 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 563469851 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 127244460 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 75441097 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 564344995 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13807906 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2007349 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 258832 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 5872913 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 777107 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 768148 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 199953853 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1622392 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 27919 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 664820080 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.994147 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.223667 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 428022323 54.42% 54.42% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 139668800 17.76% 72.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 47662444 6.06% 78.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 171216122 21.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 348468390 52.42% 52.42% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 123001690 18.50% 70.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 42123132 6.34% 77.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 151226868 22.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 786569689 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.177487 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.785914 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 110960591 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 393393476 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 236254465 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 40475350 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5485807 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 20188292 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 2163849 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 661116472 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 24295467 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5485807 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 148680347 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 59294510 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 260447701 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 238523513 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 74137811 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 642734014 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 6463851 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 12050420 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 431614 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1024133 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 35807802 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 12087 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 613144176 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 993338486 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 758389620 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 787806 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 551826661 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 61317509 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 17340731 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 15198476 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 81471302 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 106673767 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 89326102 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 10094322 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 8631476 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 618122262 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 17529509 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 623787865 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2873824 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 57783921 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 37389903 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 307135 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 786569689 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.793048 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.056857 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 664820080 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.186200 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.824539 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 100313259 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 315334519 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 208757120 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 35486026 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4929156 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 17976704 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 2012194 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 582722672 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22029645 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4929156 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 133756265 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 43242401 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 214462360 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 210347945 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 58081953 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 566482483 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5736321 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 9739688 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 342221 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 843279 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 24527700 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 11906 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 538415916 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 871757488 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 668460678 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 644937 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 483561743 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 54854172 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15093428 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13190698 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 71341154 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 94469141 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 78816060 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 9208116 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7878049 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 544809829 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15364466 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 549398452 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2550658 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 51789954 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 33366441 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 282362 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 664820080 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.826387 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.065764 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 444068370 56.46% 56.46% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 146437024 18.62% 75.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 119059525 15.14% 90.21% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 68792645 8.75% 98.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 8206769 1.04% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 5356 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 363096071 54.62% 54.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 129026402 19.41% 74.02% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 104942160 15.79% 89.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 60539163 9.11% 98.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7211179 1.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 5105 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 786569689 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 664820080 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 62505184 44.18% 44.18% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 68578 0.05% 44.23% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 15954 0.01% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 29 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 38525280 27.23% 71.47% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 40370294 28.53% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 54936992 44.00% 44.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 69872 0.06% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 6570 0.01% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 17 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 34367116 27.52% 71.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 35481157 28.42% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 56 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 425111535 68.15% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1458161 0.23% 68.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 82493 0.01% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 4 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 1 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 1 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 80022 0.01% 68.41% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.41% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.41% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.41% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 109884961 17.62% 86.03% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 87170631 13.97% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 373883416 68.05% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1335155 0.24% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 74884 0.01% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 48854 0.01% 68.32% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 97153433 17.68% 86.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 76902643 14.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 623787865 # Type of FU issued -system.cpu1.iq.rate 0.767708 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 141485319 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.226816 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 2177185436 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 693073885 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 605244442 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1319124 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 525529 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 491804 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 764456486 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 816642 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2875534 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 549398452 # Type of FU issued +system.cpu1.iq.rate 0.803948 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 124861724 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.227270 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1889962970 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 611689245 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 533047508 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1066396 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 424008 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 393622 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 673596915 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 663205 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2524444 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 13536096 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 19732 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 165171 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5907805 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 12144847 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 16403 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 149896 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5262071 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2920913 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 4601873 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2572719 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 4009144 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5485807 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 8833718 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2787810 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 635796262 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4929156 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 7182655 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1646879 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 560304926 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 106673767 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 89326102 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 14923932 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 69191 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2639688 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 165171 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2071854 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 3210854 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 5282708 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 615332242 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 106464546 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 7808914 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 94469141 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 78816060 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12974148 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 56258 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1524659 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 149896 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1843431 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2924818 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4768249 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 541845400 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 94094962 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6980663 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 144491 # number of nop insts executed -system.cpu1.iew.exec_refs 192321367 # number of memory reference insts executed -system.cpu1.iew.exec_branches 115394599 # Number of branches executed -system.cpu1.iew.exec_stores 85856821 # Number of stores executed -system.cpu1.iew.exec_rate 0.757302 # Inst execution rate -system.cpu1.iew.wb_sent 606557665 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 605736246 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 294174085 # num instructions producing a value -system.cpu1.iew.wb_consumers 482464820 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.745492 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.609732 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 50535620 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 17222374 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4915629 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 776983088 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.743733 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.546908 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 130631 # number of nop insts executed +system.cpu1.iew.exec_refs 169824676 # number of memory reference insts executed +system.cpu1.iew.exec_branches 101510793 # Number of branches executed +system.cpu1.iew.exec_stores 75729714 # Number of stores executed +system.cpu1.iew.exec_rate 0.792895 # Inst execution rate +system.cpu1.iew.wb_sent 534152020 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 533441130 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 258912640 # num instructions producing a value +system.cpu1.iew.wb_consumers 423656459 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.780597 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.611138 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 45293147 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15082103 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4436923 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 656213363 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.774724 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.573400 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 522401316 67.23% 67.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 133381083 17.17% 84.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 55837578 7.19% 91.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 18787317 2.42% 94.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 13118953 1.69% 95.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 9117290 1.17% 96.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 6295998 0.81% 97.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3737021 0.48% 98.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 14306532 1.84% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 432598016 65.92% 65.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 117091486 17.84% 83.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 49126445 7.49% 91.25% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 16229930 2.47% 93.73% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11628277 1.77% 95.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 8033144 1.22% 96.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5546832 0.85% 97.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3283510 0.50% 98.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12675723 1.93% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 776983088 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 491216523 # Number of instructions committed -system.cpu1.commit.committedOps 577867843 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 656213363 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 431870837 # Number of instructions committed +system.cpu1.commit.committedOps 508384340 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 176555967 # Number of memory references committed -system.cpu1.commit.loads 93137670 # Number of loads committed -system.cpu1.commit.membars 4128399 # Number of memory barriers committed -system.cpu1.commit.branches 109594417 # Number of branches committed -system.cpu1.commit.fp_insts 483207 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 530271703 # Number of committed integer instructions. -system.cpu1.commit.function_calls 14440728 # Number of function calls committed. +system.cpu1.commit.refs 155878283 # Number of memory references committed +system.cpu1.commit.loads 82324294 # Number of loads committed +system.cpu1.commit.membars 3722309 # Number of memory barriers committed +system.cpu1.commit.branches 96290107 # Number of branches committed +system.cpu1.commit.fp_insts 384716 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 467163355 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12903273 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 399975864 69.22% 69.22% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1198206 0.21% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 65313 0.01% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 72493 0.01% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 93137670 16.12% 85.56% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 83418297 14.44% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 351312000 69.10% 69.10% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1092238 0.21% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 59391 0.01% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 42428 0.01% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 82324294 16.19% 85.53% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 73553989 14.47% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 577867843 # Class of committed instruction -system.cpu1.commit.bw_lim_events 14306532 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1386603636 # The number of ROB reads -system.cpu1.rob.rob_writes 1266352729 # The number of ROB writes -system.cpu1.timesIdled 1031751 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 25962869 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94124971438 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 491216523 # Number of Instructions Simulated -system.cpu1.committedOps 577867843 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.654123 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.654123 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.604550 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.604550 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 726234004 # number of integer regfile reads -system.cpu1.int_regfile_writes 431188126 # number of integer regfile writes -system.cpu1.fp_regfile_reads 774766 # number of floating regfile reads -system.cpu1.fp_regfile_writes 462404 # number of floating regfile writes -system.cpu1.cc_regfile_reads 133303662 # number of cc regfile reads -system.cpu1.cc_regfile_writes 133988748 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1377831690 # number of misc regfile reads -system.cpu1.misc_regfile_writes 17262707 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 6040824 # number of replacements -system.cpu1.dcache.tags.tagsinuse 459.378668 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 164299100 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 6041336 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.195822 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8482617709500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 459.378668 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.897224 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.897224 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 366496301 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 366496301 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 86507946 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 86507946 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 72726229 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 72726229 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 199332 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 199332 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 142639 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 142639 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1934214 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1934214 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1984655 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1984655 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 159376814 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 159376814 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 159576146 # number of overall hits -system.cpu1.dcache.overall_hits::total 159576146 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 7084890 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 7084890 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 7887926 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 7887926 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 742812 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 742812 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 468512 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 468512 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 301623 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 301623 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202162 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 202162 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 15441328 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 15441328 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 16184140 # number of overall misses -system.cpu1.dcache.overall_misses::total 16184140 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 122386342500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 122386342500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 173974758337 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 173974758337 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20327422974 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 20327422974 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 5004935500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 5004935500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5709587500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5709587500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3496000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3496000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 316688523811 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 316688523811 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 316688523811 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 316688523811 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 93592836 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 93592836 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 80614155 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 80614155 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 942144 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 942144 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 611151 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 611151 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2235837 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2235837 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2186817 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2186817 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 174818142 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 174818142 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 175760286 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 175760286 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.075699 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.075699 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.097848 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.097848 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.788427 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.788427 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.766606 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.766606 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.134904 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.134904 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092446 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092446 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088328 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.088328 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.092081 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.092081 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17274.275606 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 17274.275606 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22055.830435 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22055.830435 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 43387.198138 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 43387.198138 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16593.348319 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16593.348319 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28242.634620 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28242.634620 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 508384340 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12675723 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1193390155 # The number of ROB reads +system.cpu1.rob.rob_writes 1115923607 # The number of ROB writes +system.cpu1.timesIdled 934929 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 18555780 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94085254498 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 431870837 # Number of Instructions Simulated +system.cpu1.committedOps 508384340 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.582362 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.582362 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.631967 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.631967 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 639570382 # number of integer regfile reads +system.cpu1.int_regfile_writes 380109427 # number of integer regfile writes +system.cpu1.fp_regfile_reads 631427 # number of floating regfile reads +system.cpu1.fp_regfile_writes 338972 # number of floating regfile writes +system.cpu1.cc_regfile_reads 115255782 # number of cc regfile reads +system.cpu1.cc_regfile_writes 115917819 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1185795918 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15045931 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5420466 # number of replacements +system.cpu1.dcache.tags.tagsinuse 437.277482 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 144971712 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5420977 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 26.742728 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8477404255000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 437.277482 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.854058 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.854058 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 323922794 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 323922794 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 76466425 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 76466425 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 64110613 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 64110613 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170428 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 170428 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 51164 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 51164 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1700918 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1700918 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1741756 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1741756 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 140628202 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 140628202 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 140798630 # number of overall hits +system.cpu1.dcache.overall_hits::total 140798630 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6372316 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6372316 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 7014697 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 7014697 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 658076 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 658076 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 445973 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 445973 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 278553 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 278553 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193453 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 193453 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13832986 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13832986 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 14491062 # number of overall misses +system.cpu1.dcache.overall_misses::total 14491062 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 93736923500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 93736923500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 131113304741 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 131113304741 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11858807099 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 11858807099 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4107251000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 4107251000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4806521000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4806521000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3714500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3714500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 236709035340 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 236709035340 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 236709035340 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 236709035340 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 82838741 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 82838741 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 71125310 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 71125310 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 828504 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 828504 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 497137 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 497137 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1979471 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1979471 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1935209 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1935209 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 154461188 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 154461188 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 155289692 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 155289692 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.076924 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.076924 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098624 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.098624 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794294 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794294 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.897083 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.897083 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.140721 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.140721 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099965 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099965 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.089556 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.089556 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.093316 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.093316 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14710.024346 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14710.024346 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18691.228536 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18691.228536 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 26590.863346 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 26590.863346 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14744.953384 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14744.953384 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24845.936739 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24845.936739 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20509.150755 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20509.150755 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19567.831458 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19567.831458 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 5568492 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 28779495 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 387755 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 802381 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 14.360852 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 35.867618 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 6040976 # number of writebacks -system.cpu1.dcache.writebacks::total 6040976 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3573916 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3573916 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6375716 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 6375716 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3475 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3475 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 153685 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 153685 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 9953107 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 9953107 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 9953107 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 9953107 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3510974 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3510974 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1512210 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1512210 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 742708 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 742708 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 465037 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 465037 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 147938 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 147938 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202156 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 202156 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 5488221 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 5488221 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 6230929 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 6230929 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 18701 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 18701 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 17029 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 17029 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 35730 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 35730 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 55262810500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 55262810500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 37074565990 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 37074565990 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 18477747500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 18477747500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19695654974 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19695654974 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 2170800500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 2170800500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5507478500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5507478500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3449000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3449000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 112033031464 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 112033031464 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 130510778964 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 130510778964 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3038329000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3038329000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3038329000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3038329000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037513 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037513 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018759 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018759 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.788317 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.788317 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.760920 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.760920 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066167 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066167 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092443 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092443 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031394 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031394 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035451 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035451 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15740.022712 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15740.022712 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24516.810489 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24516.810489 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24878.885780 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24878.885780 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 42352.877242 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 42352.877242 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14673.718044 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14673.718044 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27243.705356 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27243.705356 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17111.926184 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17111.926184 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16334.830072 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16334.830072 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 3137293 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 21285332 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 376632 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 706469 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.329863 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 30.129180 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 5420571 # number of writebacks +system.cpu1.dcache.writebacks::total 5420571 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3225514 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3225514 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5658563 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5658563 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3397 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3397 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 142581 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 142581 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8887474 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8887474 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8887474 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8887474 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3146802 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3146802 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1356134 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1356134 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 657988 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 657988 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 442576 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 442576 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 135972 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 135972 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193443 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 193443 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4945512 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4945512 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5603500 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5603500 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6118 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6118 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 6183 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 6183 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 12301 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 12301 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43613350000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43613350000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26794309953 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26794309953 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14059014500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14059014500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11316204599 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11316204599 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1866790500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1866790500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4613147000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4613147000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3645500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3645500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 81723864552 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 81723864552 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 95782879052 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 95782879052 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 749898500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 749898500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749898500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749898500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037987 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037987 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019067 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019067 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794188 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794188 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.890250 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.890250 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068691 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068691 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099960 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099960 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032018 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.032018 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036084 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.036084 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13859.578709 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13859.578709 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19757.863126 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19757.863126 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21366.673100 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21366.673100 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 25568.952223 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 25568.952223 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13729.227341 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13729.227341 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23847.577839 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23847.577839 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20413.360079 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20413.360079 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20945.637314 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20945.637314 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162468.798460 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162468.798460 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 85035.796250 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 85035.796250 # average overall mshr uncacheable latency -system.cpu1.icache.tags.replacements 6229961 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.669710 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 220025292 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 6230473 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 35.314380 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8522353535000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.669710 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979824 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.979824 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16524.854161 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16524.854161 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17093.402169 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17093.402169 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122572.491010 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 122572.491010 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 60962.401431 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 60962.401431 # average overall mshr uncacheable latency +system.cpu1.icache.tags.replacements 5742782 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.536552 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 193871102 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5743294 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 33.756082 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8517126060000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.536552 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979564 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.979564 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 396 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 459465626 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 459465626 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 220025292 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 220025292 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 220025292 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 220025292 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 220025292 # number of overall hits -system.cpu1.icache.overall_hits::total 220025292 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 6592262 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 6592262 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 6592262 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 6592262 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 6592262 # number of overall misses -system.cpu1.icache.overall_misses::total 6592262 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 74756974451 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 74756974451 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 74756974451 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 74756974451 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 74756974451 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 74756974451 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 226617554 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 226617554 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 226617554 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 226617554 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 226617554 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 226617554 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029090 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.029090 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029090 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.029090 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029090 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.029090 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11340.109730 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 11340.109730 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11340.109730 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 11340.109730 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11340.109730 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 11340.109730 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 11528745 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 835 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 773545 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.903781 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 139.166667 # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 6229961 # number of writebacks -system.cpu1.icache.writebacks::total 6229961 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 361744 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 361744 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 361744 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 361744 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 361744 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 361744 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 6230518 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 6230518 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 6230518 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 6230518 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 6230518 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 6230518 # number of overall MSHR misses +system.cpu1.icache.tags.tag_accesses 405638078 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 405638078 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 193871102 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 193871102 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 193871102 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 193871102 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 193871102 # number of overall hits +system.cpu1.icache.overall_hits::total 193871102 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 6076268 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 6076268 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 6076268 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 6076268 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 6076268 # number of overall misses +system.cpu1.icache.overall_misses::total 6076268 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64119298557 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 64119298557 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 64119298557 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 64119298557 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 64119298557 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 64119298557 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 199947370 # 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number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 67349232950 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 67349232950 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8957498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8957498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8957498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8957498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027494 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027494 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027494 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027494 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027494 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027494 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10809.572005 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10809.572005 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10809.572005 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10809.572005 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10809.572005 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10809.572005 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133694 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133694 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133694 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133694 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.num_hwpf_issued 8304723 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 8311187 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 5839 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58166889552 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 58166889552 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58166889552 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 58166889552 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58166889552 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 58166889552 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6789498 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6789498 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6789498 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6789498 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028724 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.028724 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.028724 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10127.714850 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101335.791045 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101335.791045 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7416585 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7422175 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 5069 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 1024317 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2528309 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13413.609149 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 18251408 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2544361 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.173278 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9891515003500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12660.361458 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 61.649049 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 73.939309 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000012 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 617.659322 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.772727 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003763 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004513 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.000000 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.037699 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.818702 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1288 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14705 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 259 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 581 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 431 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 38 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1409 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5268 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4214 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3711 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078613 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.897522 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 421641447 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 421641447 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 670573 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 201040 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 871613 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3790012 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3790012 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 8479233 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 8479233 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 992 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 992 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 953658 # 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number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 670573 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 201040 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5605859 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 4270897 # number of overall hits -system.cpu1.l2cache.overall_hits::total 10748369 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13735 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10344 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 24079 # number of ReadReq misses -system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses -system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses +system.cpu1.l2cache.prefetcher.pfSpanPage 930081 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2216875 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13443.573819 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 16807540 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2232789 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 7.527599 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9871196159000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 12560.451650 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 62.875087 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 63.205555 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 757.041527 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.766629 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003838 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003858 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.046206 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.820531 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1320 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14527 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 25 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 72 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 681 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 425 # 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mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048892 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.100252 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234709 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154677 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020068 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048892 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.100252 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234709 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.219635 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.219635 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.095429 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.095429 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.245367 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245367 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.597664 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.597664 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021697 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048118 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.095429 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.239612 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153689 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021697 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048118 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.095429 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.239612 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.222549 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 50012.451759 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 57121.770682 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 53065.252618 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 75599.634138 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 75599.634138 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31401.281357 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31401.281357 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19728.755439 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19728.755439 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1031832.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1031832.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 52054.180063 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 52054.180063 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32502.808930 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32502.808930 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 37531.909259 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 37531.909259 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 53902.662763 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 53902.662763 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 50012.451759 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 57121.770682 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32502.808930 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 40323.146607 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 38009.686354 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 50012.451759 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 57121.770682 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32502.808930 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 40323.146607 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 75599.634138 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 49473.708995 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126179.104478 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154459.895193 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154358.935422 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126179.104478 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 80843.954660 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 80928.806883 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 25472686 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 13111869 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1712 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 2149417 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2149008 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 409 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 1009964 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 11730214 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 17029 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 17029 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 5169290 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 8480923 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2927219 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1103039 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 459055 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 356155 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 515583 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 73 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1297103 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1275135 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 6230518 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5372910 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 516382 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 463121 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18691087 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 19440124 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 443982 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1442906 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 40018099 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 797468912 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 755702222 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1691072 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 5474464 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1560336670 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 7082459 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 20668727 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.122834 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.328306 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.220233 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38409.213974 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52588.772093 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 52588.772093 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20699.721837 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20699.721837 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16333.391896 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16333.391896 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 782000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 782000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36110.304736 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36110.304736 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26962.650321 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28763.842481 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28763.842481 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 28069.480634 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 28069.480634 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30269.894802 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29359.627093 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30269.894802 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52588.772093 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36378.343549 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93820.895522 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 114548.545276 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114324.009701 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93820.895522 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 56971.628323 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57171.248383 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 23197310 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11940096 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1942556 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1942287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 900600 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10671947 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 6183 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6183 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4554023 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 7810324 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2589255 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 981692 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 441382 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 342905 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 485827 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1162425 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1140502 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5743338 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4866994 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 495411 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 441012 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17229566 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17476902 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 425595 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1276864 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 36408927 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 735111088 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 677743701 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1625328 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4839024 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1419319141 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6390553 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 18731260 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.122712 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.328150 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 18130322 87.72% 87.72% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2537996 12.28% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 409 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 16432977 87.73% 87.73% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2298014 12.27% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 269 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 20668727 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 25335696459 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 177629109 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 18731260 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 23041315974 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 175324271 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 9352273561 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8621166733 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8995491238 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8059431425 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 232944299 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 222762323 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 759270636 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 672656647 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40305 # Transaction distribution -system.iobus.trans_dist::ReadResp 40305 # Transaction distribution -system.iobus.trans_dist::WriteReq 136595 # Transaction distribution -system.iobus.trans_dist::WriteResp 136595 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47570 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40341 # Transaction distribution +system.iobus.trans_dist::ReadResp 40341 # Transaction distribution +system.iobus.trans_dist::WriteReq 136646 # Transaction distribution +system.iobus.trans_dist::WriteResp 136646 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47790 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2979,15 +2953,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122504 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231216 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231216 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231222 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231222 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353800 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47590 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353974 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47810 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2998,103 +2972,103 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155611 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338880 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155802 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338904 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496577 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36858001 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37061004 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 13500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 24204504 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 24283001 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36391000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36403501 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567248472 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569028004 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92640000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92757000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147912000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115604 # number of replacements -system.iocache.tags.tagsinuse 11.311799 # Cycle average of tags in use +system.iocache.tags.replacements 115592 # number of replacements +system.iocache.tags.tagsinuse 11.302694 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115620 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115608 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9121271629000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.400215 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.911583 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.462513 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.244474 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706987 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9115775800000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.842796 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.459898 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240175 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466244 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706418 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040829 # Number of tag accesses -system.iocache.tags.data_accesses 1040829 # Number of data accesses +system.iocache.tags.tag_accesses 1040856 # Number of tag accesses +system.iocache.tags.data_accesses 1040856 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8880 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8917 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115608 # number of demand (read+write) misses -system.iocache.demand_misses::total 115648 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115611 # number of demand (read+write) misses +system.iocache.demand_misses::total 115651 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115608 # number of overall misses -system.iocache.overall_misses::total 115648 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5214500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1674617085 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1679831585 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115611 # number of overall misses +system.iocache.overall_misses::total 115651 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5246000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1667860010 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1673106010 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13548349887 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13548349887 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5583500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15222966972 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15228550472 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5583500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15222966972 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15228550472 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12956345994 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12956345994 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5615000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14624206004 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14629821004 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5615000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14624206004 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14629821004 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8880 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8917 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115608 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115648 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115611 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115651 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115608 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115648 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115611 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115651 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3108,53 +3082,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140932.432432 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 188583.005068 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 188385.284849 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141783.783784 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 187758.641225 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 187567.938341 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126942.788087 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126942.788087 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139587.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 131677.452875 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 131680.188780 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139587.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 131677.452875 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 131680.188780 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33801 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121395.941028 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 121395.941028 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 140375 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 126494.935638 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126499.736310 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 140375 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 126494.935638 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126499.736310 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33436 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3396 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3541 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.953180 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.442530 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8880 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8917 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115608 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115648 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115611 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115651 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115608 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115648 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3364500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1230617085 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1233981585 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115611 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115651 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3396000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1223710010 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1227106010 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8205400767 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8205400767 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3583500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9436017852 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9439601352 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3583500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9436017852 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9439601352 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7611309187 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7611309187 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3615000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8835019197 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8838634197 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3615000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8835019197 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8838634197 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3168,643 +3142,641 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90932.432432 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138583.005068 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 138385.284849 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91783.783784 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137758.641225 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 137567.938341 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76881.425371 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76881.425371 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89587.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 81620.803508 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 81623.559007 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89587.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 81620.803508 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 81623.559007 # average overall mshr miss latency -system.l2c.tags.replacements 1658646 # number of replacements -system.l2c.tags.tagsinuse 63614.355421 # Cycle average of tags in use -system.l2c.tags.total_refs 6503693 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1717473 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.786780 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 4906135000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 21778.868920 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 77.174149 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 104.892582 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3369.245029 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4690.877672 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5127.772728 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 275.118534 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 421.752346 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3923.044466 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 10215.764671 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13629.844323 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.332319 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001178 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001601 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.051411 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.071577 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.078244 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004198 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006435 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.059861 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.155880 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.207975 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.970678 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9349 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 246 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49232 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 12 # 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miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.515876 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.272951 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.291517 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.284424 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.098464 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.244580 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.476117 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.339405 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.427712 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.090787 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.234830 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.515876 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.272951 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16591.167041 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17052.495837 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 16831.525036 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14902.991453 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17354.262978 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 16202.229363 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 141568.153388 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 141799.482866 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 141667.158630 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 143760.926410 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 143657.407407 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 138045.218116 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 148066.737775 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 187060.844213 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 142242.815249 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 138625.420618 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137454.026840 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 146629.530336 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 185155.876040 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 169025.023911 # average ReadSharedReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 329.067334 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 1089.516749 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::total 516.847728 # average InvalidateReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 143760.926410 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 143657.407407 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 138045.218116 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 145653.864549 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 187060.844213 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 142242.815249 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138625.420618 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 137454.026840 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 145250.023026 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 185155.876040 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 165622.881347 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 143760.926410 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 143657.407407 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 138045.218116 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 145653.864549 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 187060.844213 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 142242.815249 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138625.420618 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 137454.026840 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 145250.023026 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 185155.876040 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 165622.881347 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 15923 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71315.017493 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71315.017493 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency +system.l2c.tags.replacements 1423185 # number of replacements +system.l2c.tags.tagsinuse 63448.336905 # Cycle average of tags in use +system.l2c.tags.total_refs 6060449 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1482600 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.087717 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 3022937500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 20826.975184 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.832374 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 12.742051 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3854.622142 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3569.542843 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 2315.690288 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 335.622211 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 552.279614 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2996.807733 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11095.009846 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17872.212619 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.317794 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000257 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000194 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.058817 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.054467 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.035335 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005121 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.008427 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.045728 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.169296 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.272708 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.968145 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10702 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 222 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 48491 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 11 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 1377 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 482 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 8826 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 218 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2760 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5614 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 39761 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.163300 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.739914 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 76659871 # Number of tag accesses +system.l2c.tags.data_accesses 76659871 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 2799563 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2799563 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 175772 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 127713 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 303485 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 39800 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 41169 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 80969 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 55176 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 52470 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107646 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6441 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4632 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 512914 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 602529 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 321191 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6205 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4222 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 506602 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 564191 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 285940 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2814867 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 134470 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 123510 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 257980 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6441 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4632 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 512914 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 657705 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 321191 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6205 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4222 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 506602 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 616661 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 285940 # number of demand (read+write) hits +system.l2c.demand_hits::total 2922513 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6441 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4632 # number of overall hits +system.l2c.overall_hits::cpu0.inst 512914 # number of overall hits +system.l2c.overall_hits::cpu0.data 657705 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 321191 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6205 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4222 # number of overall hits +system.l2c.overall_hits::cpu1.inst 506602 # number of overall hits +system.l2c.overall_hits::cpu1.data 616661 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 285940 # number of overall hits +system.l2c.overall_hits::total 2922513 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 65800 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 60076 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 125876 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 12292 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 11651 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 23943 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 76423 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 57499 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133922 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1380 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 911 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 60940 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 127468 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 217255 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3149 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2958 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 41472 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 123752 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 256869 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 836154 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 453643 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 128024 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 581667 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1380 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 911 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 60940 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 203891 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 217255 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3149 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2958 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 41472 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 181251 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 256869 # number of demand (read+write) misses +system.l2c.demand_misses::total 970076 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1380 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 911 # number of overall misses +system.l2c.overall_misses::cpu0.inst 60940 # number of overall misses +system.l2c.overall_misses::cpu0.data 203891 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 217255 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3149 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2958 # number of overall misses +system.l2c.overall_misses::cpu1.inst 41472 # number of overall misses +system.l2c.overall_misses::cpu1.data 181251 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 256869 # number of overall misses +system.l2c.overall_misses::total 970076 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 448544000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 390663000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 839207000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 74504000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 75234500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 149738500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6937615986 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5199044498 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 12136660484 # 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mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.234807 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.515876 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.272872 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.291190 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.284424 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.098174 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.244543 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.476117 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.339405 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.427712 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.090605 # 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average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127488.239500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 136630.231188 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175152.027500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 159033.895931 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70271.633390 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69591.955264 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 70103.798129 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 133765.908003 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 133651.337566 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 128053.317774 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135649.713205 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177054.217697 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 132241.790909 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128624.046803 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127488.239500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135248.758735 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175152.027500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 155628.884125 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 133765.908003 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 133651.337566 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 128053.317774 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135649.713205 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177054.217697 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 132241.790909 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128624.046803 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127488.239500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135248.758735 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175152.027500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 155628.884125 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170027.531412 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108171.641791 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136469.009894 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138985.217937 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81776.885043 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108171.641791 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 71423.925661 # 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mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.336647 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.411978 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.075470 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.179875 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.473222 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.228951 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.771353 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.508973 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.692752 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.176448 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.164351 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.106001 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.236620 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403485 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.336647 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.411978 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.075470 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.227147 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.473222 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.249147 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.176448 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.164351 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.106001 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.236620 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403485 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.336647 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.411978 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.075470 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.227147 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.473222 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.249147 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21800.630729 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21481.090535 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21648.125910 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24728.644566 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24529.095872 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24631.541369 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80776.871426 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80418.080175 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80622.825503 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 85612.682609 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 83498.902305 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 77339.847556 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 84367.373235 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130476.040469 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82095.111146 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79805.781271 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 78119.746029 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 86410.878491 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 127706.883719 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109127.534756 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 25238.478491 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20854.531182 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24273.578522 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 85612.682609 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 83498.902305 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 77339.847556 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83021.439189 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130476.040469 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82095.111146 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79805.781271 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 78119.746029 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84509.674525 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 127706.883719 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 105191.364969 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 85612.682609 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 83498.902305 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 77339.847556 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83021.439189 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130476.040469 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82095.111146 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79805.781271 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 78119.746029 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84509.674525 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 127706.883719 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 105191.364969 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164853.967627 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75813.432836 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 96561.069817 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 121669.858307 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82650.590416 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 75813.432836 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48017.521994 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74089.494383 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3952559 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2414080 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 60003 # Transaction distribution +system.membus.trans_dist::ReadResp 904829 # Transaction distribution +system.membus.trans_dist::WriteReq 38534 # Transaction distribution +system.membus.trans_dist::WriteResp 38534 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1242017 # Transaction distribution +system.membus.trans_dist::CleanEvict 238236 # Transaction distribution +system.membus.trans_dist::UpgradeReq 446737 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 299659 # Transaction distribution system.membus.trans_dist::UpgradeResp 23 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 153866 # Transaction distribution -system.membus.trans_dist::ReadExResp 139435 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1026904 # Transaction distribution -system.membus.trans_dist::InvalidateReq 703178 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122504 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 144708 # Transaction distribution +system.membus.trans_dist::ReadExResp 128413 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 844826 # Transaction distribution +system.membus.trans_dist::InvalidateReq 684897 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122672 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25676 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5303073 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5451329 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237588 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237588 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5688917 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155611 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4681290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4830500 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238195 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238195 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5068695 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155802 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51352 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 158370176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 158577695 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7233920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7233920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 165811615 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 603403 # Total snoops (count) -system.membus.snoop_fanout::samples 4427877 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52924 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 134692416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 134901698 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7273344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7273344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 142175042 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 606585 # Total snoops (count) +system.membus.snoop_fanout::samples 2519367 # Request fanout histogram +system.membus.snoop_fanout::mean 0.015113 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.122002 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4427877 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2481292 98.49% 98.49% # Request fanout histogram +system.membus.snoop_fanout::1 38075 1.51% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4427877 # Request fanout histogram -system.membus.reqLayer0.occupancy 97877995 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2519367 # Request fanout histogram +system.membus.reqLayer0.occupancy 98170994 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21789496 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22248500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9855054431 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8723892621 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6236968511 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5223815230 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45519188 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45514707 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3858,58 +3830,58 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 12681630 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6883923 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2005926 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 170885 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 155146 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 15739 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 59767 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4843433 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38295 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38295 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 4463947 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 11842018 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6441759 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1913591 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 133722 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 121814 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 11908 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 60005 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4492996 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38534 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38534 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3934886 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2878269 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 761897 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 392804 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1154700 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 117 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 312867 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 312867 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4790902 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 969633 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 862905 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9568329 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9002574 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 18570903 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 239712817 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 228526446 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 468239263 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3311598 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9100879 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.338787 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.476937 # Request fanout histogram +system.toL2Bus.trans_dist::CleanEvict 2625367 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 741215 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 380628 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1121842 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 140 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295903 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295903 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4433512 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 874748 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 839647 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9358904 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7932274 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17291178 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 230390413 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198586357 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 428976770 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2884507 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8248846 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.358423 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.482538 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 6033358 66.29% 66.29% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3051782 33.53% 99.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 15739 0.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5304178 64.30% 64.30% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2932760 35.55% 99.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 11908 0.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9100879 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9916846796 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8248846 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9216694138 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2612852 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2593163 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4354241663 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4234968582 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4394264623 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3934186551 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4933 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 13240 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 14218 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 5626 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index ff7be42c7..3e88f4b72 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.327140 # Nu sim_ticks 51327139864000 # Number of ticks simulated final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139449 # Simulator instruction rate (inst/s) -host_op_rate 163855 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8438816943 # Simulator tick rate (ticks/s) -host_mem_usage 688284 # Number of bytes of host memory used -host_seconds 6082.27 # Real time elapsed on the host +host_inst_rate 181298 # Simulator instruction rate (inst/s) +host_op_rate 213029 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10971364807 # Simulator tick rate (ticks/s) +host_mem_usage 680328 # Number of bytes of host memory used +host_seconds 4678.28 # Real time elapsed on the host sim_insts 848164321 # Number of instructions simulated sim_ops 996610207 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt index dd0bedb40..ce7451dc8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu sim_ticks 51111167216500 # Number of ticks simulated final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1195823 # Simulator instruction rate (inst/s) -host_op_rate 1405350 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62227318824 # Simulator tick rate (ticks/s) -host_mem_usage 678332 # Number of bytes of host memory used -host_seconds 821.36 # Real time elapsed on the host +host_inst_rate 1222140 # Simulator instruction rate (inst/s) +host_op_rate 1436279 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63596815146 # Simulator tick rate (ticks/s) +host_mem_usage 673192 # Number of bytes of host memory used +host_seconds 803.68 # Real time elapsed on the host sim_insts 982203438 # Number of instructions simulated sim_ops 1154301153 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 72aef18b4..9aa72b24a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -1,77 +1,77 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.256536 # Number of seconds simulated -sim_ticks 47256535705500 # Number of ticks simulated -final_tick 47256535705500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.216815 # Number of seconds simulated +sim_ticks 47216814802000 # Number of ticks simulated +final_tick 47216814802000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1118024 # Simulator instruction rate (inst/s) -host_op_rate 1315296 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54153885278 # Simulator tick rate (ticks/s) -host_mem_usage 690972 # Number of bytes of host memory used -host_seconds 872.63 # Real time elapsed on the host -sim_insts 975625723 # Number of instructions simulated -sim_ops 1147772483 # Number of ops (including micro ops) simulated +host_inst_rate 1112312 # Simulator instruction rate (inst/s) +host_op_rate 1308465 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53753255119 # Simulator tick rate (ticks/s) +host_mem_usage 687512 # Number of bytes of host memory used +host_seconds 878.40 # Real time elapsed on the host +sim_insts 977053655 # Number of instructions simulated +sim_ops 1149354696 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 156864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 131392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3883124 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 35607176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 217792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 214080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2613000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 38038064 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 430464 # Number of bytes read from this memory -system.physmem.bytes_read::total 81291956 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3883124 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2613000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6496124 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 101151552 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 150336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 124416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3895860 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 34948936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 222016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 222656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2668232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 38725552 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 417728 # Number of bytes read from this memory +system.physmem.bytes_read::total 81375732 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3895860 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2668232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6564092 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 101375872 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 101172136 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2451 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2053 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 101081 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 556375 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3345 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 40935 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 594361 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6726 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1310730 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1580493 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 101396456 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2349 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1944 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 101280 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 546090 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3469 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3479 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 41798 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 605103 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6527 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1312039 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1583998 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1583067 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 82171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 753487 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 55294 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 804927 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1720227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 82171 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 55294 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 137465 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2140478 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1586572 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 82510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 740180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 4716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 820164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1723448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82510 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56510 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 139020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2147029 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2140913 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2140478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 82171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 753922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 55294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 804927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3861140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2147465 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2147029 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 82510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 740616 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 4716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 820165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3870913 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -134,45 +134,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 124170 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 124170 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 124170 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 124170 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 124170 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 124420 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 124420 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 124420 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 124420 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 124420 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 95903 89.91% 89.91% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10758 10.09% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 106661 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 124170 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 95857 89.92% 89.92% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10751 10.08% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 106608 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 124420 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 124170 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 124420 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106608 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106661 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 230831 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106608 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 231028 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91996645 # DTB read hits -system.cpu0.dtb.read_misses 87944 # DTB read misses -system.cpu0.dtb.write_hits 85085804 # DTB write hits -system.cpu0.dtb.write_misses 36226 # DTB write misses +system.cpu0.dtb.read_hits 91801710 # DTB read hits +system.cpu0.dtb.read_misses 88193 # DTB read misses +system.cpu0.dtb.write_hits 84999619 # DTB write hits +system.cpu0.dtb.write_misses 36227 # DTB write misses system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36305 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 36369 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 5760 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 5198 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10368 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 92084589 # DTB read accesses -system.cpu0.dtb.write_accesses 85122030 # DTB write accesses +system.cpu0.dtb.perms_faults 10393 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 91889903 # DTB read accesses +system.cpu0.dtb.write_accesses 85035846 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 177082449 # DTB hits -system.cpu0.dtb.misses 124170 # DTB misses -system.cpu0.dtb.accesses 177206619 # DTB accesses +system.cpu0.dtb.hits 176801329 # DTB hits +system.cpu0.dtb.misses 124420 # DTB misses +system.cpu0.dtb.accesses 176925749 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -202,76 +202,76 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 60706 # Table walker walks requested -system.cpu0.itb.walker.walksLong 60706 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 60706 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 60706 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 60706 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 60852 # Table walker walks requested +system.cpu0.itb.walker.walksLong 60852 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 60852 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 60852 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 60852 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54677 98.81% 98.81% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 656 1.19% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 55333 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 54793 98.83% 98.83% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 650 1.17% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 55443 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60706 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60706 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60852 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60852 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55333 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55333 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 116039 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 494456191 # ITB inst hits -system.cpu0.itb.inst_misses 60706 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55443 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55443 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 116295 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 493637993 # ITB inst hits +system.cpu0.itb.inst_misses 60852 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25125 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 25117 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 494516897 # ITB inst accesses -system.cpu0.itb.hits 494456191 # DTB hits -system.cpu0.itb.misses 60706 # DTB misses -system.cpu0.itb.accesses 494516897 # DTB accesses -system.cpu0.numCycles 94513084765 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 493698845 # ITB inst accesses +system.cpu0.itb.hits 493637993 # DTB hits +system.cpu0.itb.misses 60852 # DTB misses +system.cpu0.itb.accesses 493698845 # DTB accesses +system.cpu0.numCycles 94433642835 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13353 # number of quiesce instructions executed -system.cpu0.committedInsts 494222683 # Number of instructions committed -system.cpu0.committedOps 581244792 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 532690974 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 523276 # Number of float alu accesses -system.cpu0.num_func_calls 28754621 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 75975087 # number of instructions that are conditional controls -system.cpu0.num_int_insts 532690974 # number of integer instructions -system.cpu0.num_fp_insts 523276 # number of float instructions -system.cpu0.num_int_register_reads 780604880 # number of times the integer registers were read -system.cpu0.num_int_register_writes 422748329 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 843639 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 445096 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 132982449 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 132652363 # number of times the CC registers were written -system.cpu0.num_mem_refs 177183712 # number of memory refs -system.cpu0.num_load_insts 92070454 # Number of load instructions -system.cpu0.num_store_insts 85113258 # Number of store instructions -system.cpu0.num_idle_cycles 93931503589.334885 # Number of idle cycles -system.cpu0.num_busy_cycles 581581175.665107 # Number of busy cycles -system.cpu0.not_idle_fraction 0.006153 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.993847 # Percentage of idle cycles -system.cpu0.Branches 110567658 # Number of branches fetched +system.cpu0.kern.inst.quiesce 13230 # number of quiesce instructions executed +system.cpu0.committedInsts 493402150 # Number of instructions committed +system.cpu0.committedOps 580232432 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 531778274 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 521057 # Number of float alu accesses +system.cpu0.num_func_calls 28738017 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 75812609 # number of instructions that are conditional controls +system.cpu0.num_int_insts 531778274 # number of integer instructions +system.cpu0.num_fp_insts 521057 # number of float instructions +system.cpu0.num_int_register_reads 778807297 # number of times the integer registers were read +system.cpu0.num_int_register_writes 421918818 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 841474 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 439940 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 132610797 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 132275173 # number of times the CC registers were written +system.cpu0.num_mem_refs 176902115 # number of memory refs +system.cpu0.num_load_insts 91875039 # Number of load instructions +system.cpu0.num_store_insts 85027076 # Number of store instructions +system.cpu0.num_idle_cycles 93853071494.060760 # Number of idle cycles +system.cpu0.num_busy_cycles 580571340.939238 # Number of busy cycles +system.cpu0.not_idle_fraction 0.006148 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.993852 # Percentage of idle cycles +system.cpu0.Branches 110403926 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 403027649 69.30% 69.30% # Class of executed instruction -system.cpu0.op_class::IntMult 1232673 0.21% 69.51% # Class of executed instruction -system.cpu0.op_class::IntDiv 59610 0.01% 69.52% # Class of executed instruction +system.cpu0.op_class::IntAlu 402310075 69.30% 69.30% # Class of executed instruction +system.cpu0.op_class::IntMult 1222689 0.21% 69.51% # Class of executed instruction +system.cpu0.op_class::IntDiv 59704 0.01% 69.52% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction @@ -294,341 +294,342 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Cl system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 73071 0.01% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 72217 0.01% 69.53% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::MemRead 92070454 15.83% 85.37% # Class of executed instruction -system.cpu0.op_class::MemWrite 85113258 14.63% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 91875039 15.83% 85.35% # Class of executed instruction +system.cpu0.op_class::MemWrite 85027076 14.65% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 581576758 # Class of executed instruction -system.cpu0.dcache.tags.replacements 6248192 # number of replacements -system.cpu0.dcache.tags.tagsinuse 500.818994 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 170762721 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6248704 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.327702 # Average number of references to valid blocks. +system.cpu0.op_class::total 580566843 # Class of executed instruction +system.cpu0.dcache.tags.replacements 6218107 # number of replacements +system.cpu0.dcache.tags.tagsinuse 503.352532 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 170512705 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6218619 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.419706 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.818994 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978162 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.978162 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.352532 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983110 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.983110 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 360582168 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 360582168 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 85561344 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 85561344 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80310144 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80310144 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214412 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 214412 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259689 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 259689 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2079285 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2079285 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2039805 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2039805 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 166131177 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 166131177 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 166345589 # number of overall hits -system.cpu0.dcache.overall_hits::total 166345589 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3292661 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3292661 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1484857 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1484857 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 774558 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 774558 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 823193 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 823193 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 118361 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 118361 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 156654 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 156654 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5600711 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5600711 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6375269 # number of overall misses -system.cpu0.dcache.overall_misses::total 6375269 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 88854005 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 88854005 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81795001 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81795001 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 988970 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 988970 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1082882 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1082882 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2197646 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2197646 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2196459 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2196459 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 171731888 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 171731888 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 172720858 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 172720858 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037057 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037057 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018153 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018153 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783197 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.783197 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760187 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760187 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053858 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053858 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071321 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.071321 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032613 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.032613 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036911 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.036911 # miss rate for overall accesses +system.cpu0.dcache.tags.tag_accesses 359988587 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 359988587 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 85387960 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 85387960 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80242803 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80242803 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214677 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 214677 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 260385 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 260385 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076595 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2076595 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2038168 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2038168 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 165891148 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 165891148 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 166105825 # number of overall hits +system.cpu0.dcache.overall_hits::total 166105825 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3280646 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3280646 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1472125 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1472125 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 768471 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 768471 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 819890 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 819890 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 117360 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 117360 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154684 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 154684 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5572661 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5572661 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6341132 # number of overall misses +system.cpu0.dcache.overall_misses::total 6341132 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 88668606 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 88668606 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81714928 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81714928 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 983148 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 983148 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1080275 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1080275 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2193955 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2193955 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2192852 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2192852 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 171463809 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 171463809 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 172446957 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 172446957 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036999 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036999 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018015 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018015 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781643 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781643 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.758964 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.758964 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053492 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053492 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.070540 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.070540 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032501 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.032501 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036771 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.036771 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6248192 # number of writebacks -system.cpu0.dcache.writebacks::total 6248192 # number of writebacks -system.cpu0.icache.tags.replacements 5479450 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.989014 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 489031557 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5479962 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 89.239954 # Average number of references to valid blocks. +system.cpu0.dcache.writebacks::writebacks 6218107 # number of writebacks +system.cpu0.dcache.writebacks::total 6218107 # number of writebacks +system.cpu0.icache.tags.replacements 5488502 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 488204417 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5489014 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 88.942097 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989014 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 994503015 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 994503015 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 489031557 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 489031557 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 489031557 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 489031557 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 489031557 # number of overall hits -system.cpu0.icache.overall_hits::total 489031557 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5479967 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5479967 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5479967 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5479967 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5479967 # number of overall misses -system.cpu0.icache.overall_misses::total 5479967 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 494511524 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 494511524 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 494511524 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 494511524 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 494511524 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 494511524 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011082 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011082 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011082 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011082 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011082 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011082 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 992875891 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 992875891 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 488204417 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 488204417 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 488204417 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 488204417 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 488204417 # number of overall hits +system.cpu0.icache.overall_hits::total 488204417 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5489019 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5489019 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5489019 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5489019 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5489019 # number of overall misses +system.cpu0.icache.overall_misses::total 5489019 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 493693436 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 493693436 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 493693436 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 493693436 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 493693436 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 493693436 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011118 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011118 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011118 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011118 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011118 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011118 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 5479450 # number of writebacks -system.cpu0.icache.writebacks::total 5479450 # number of writebacks +system.cpu0.icache.writebacks::writebacks 5488502 # number of writebacks +system.cpu0.icache.writebacks::total 5488502 # number of writebacks system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2651590 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16092.484650 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 15457113 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2667587 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.794418 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 2643580 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16147.870386 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 15444293 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2659582 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.807038 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15991.608429 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 49.291374 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 51.584847 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.976050 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003009 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003148 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.982207 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15920 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1478 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4821 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4797 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4598 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.971680 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 394865177 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 394865177 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 294372 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 156640 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 451012 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 4430802 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 4430802 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 7295441 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 7295441 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 774 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 774 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 631554 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 631554 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4983798 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 4983798 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2949332 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2949332 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 218231 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 218231 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 294372 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 156640 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4983798 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3580886 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 9015696 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 294372 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 156640 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4983798 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3580886 # number of overall hits -system.cpu0.l2cache.overall_hits::total 9015696 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11531 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8761 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 20292 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 140614 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 140614 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 156654 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 156654 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 712280 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 712280 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 496169 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 496169 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1236248 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 1236248 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 604597 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 604597 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11531 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8761 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 496169 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1948528 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2464989 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11531 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8761 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 496169 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1948528 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2464989 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 305903 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165401 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 471304 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4430802 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 4430802 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 7295441 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 7295441 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 141388 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 141388 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 156654 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 156654 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1343834 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1343834 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5479967 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 5479967 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4185580 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 4185580 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 822828 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 822828 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 305903 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165401 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5479967 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5529414 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11480685 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 305903 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165401 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5479967 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5529414 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11480685 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052968 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.043055 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994526 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994526 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 16070.787170 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 39.567916 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 37.515300 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.980883 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002415 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002290 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.985588 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 53 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15949 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1503 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4323 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5407 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4485 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973450 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 394033422 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 394033422 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 293436 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155846 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 449282 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 4423360 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 4423360 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 7281875 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 7281875 # number of WritebackClean hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 738 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 738 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 633298 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 633298 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4991790 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 4991790 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2937635 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 2937635 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 218374 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 218374 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 293436 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 155846 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 4991790 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3570933 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 9012005 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 293436 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 155846 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 4991790 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3570933 # number of overall hits +system.cpu0.l2cache.overall_hits::total 9012005 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11306 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8709 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 20015 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 136695 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 136695 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154684 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 154684 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 701772 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 701772 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 497229 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 497229 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1228842 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1228842 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601138 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 601138 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11306 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8709 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 497229 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1930614 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2447858 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11306 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8709 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 497229 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1930614 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2447858 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 304742 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164555 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 469297 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4423360 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 4423360 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 7281875 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 7281875 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 137433 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 137433 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154684 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 154684 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1335070 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1335070 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5489019 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 5489019 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4166477 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 4166477 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 819512 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 819512 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 304742 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164555 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5489019 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5501547 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11459863 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 304742 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164555 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5489019 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5501547 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 11459863 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052925 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.042649 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994630 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994630 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.530036 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.530036 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090542 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090542 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.295359 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.295359 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.734779 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.734779 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052968 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090542 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.352393 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.214707 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052968 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090542 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.352393 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.214707 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.525644 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.525644 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090586 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090586 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294936 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294936 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.733532 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.733532 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052925 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090586 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.350922 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.213603 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052925 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090586 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.350922 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.213603 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.writebacks::writebacks 1558575 # number of writebacks -system.cpu0.l2cache.writebacks::total 1558575 # number of writebacks -system.cpu0.toL2Bus.snoop_filter.tot_requests 24117057 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12284855 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1785822 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1785488 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 334 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 618755 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 10284302 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 33226 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 33226 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 4430802 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 7296840 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 141388 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 156654 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 298042 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1343834 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1343834 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5479967 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4185580 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 822828 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 822828 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16525634 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19681390 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 362662 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 722420 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 37292106 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 701575188 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753965416 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1450648 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2889680 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1459880932 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6124419 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 30450834 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.067260 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.250516 # Request fanout histogram +system.cpu0.l2cache.writebacks::writebacks 1554149 # number of writebacks +system.cpu0.l2cache.writebacks::total 1554149 # number of writebacks +system.cpu0.toL2Bus.snoop_filter.tot_requests 24067586 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12257514 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1374 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1770017 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1769681 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 336 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 619965 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 10275461 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 33238 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 33238 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 4423360 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 7283249 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 137433 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154684 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 292117 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1335070 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1335070 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5489019 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4166477 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 819512 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 819512 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16552790 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19577101 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 363556 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 723958 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 37217405 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 702733844 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 750256336 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1454224 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2895832 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1457340236 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6073545 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 30354370 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.066939 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.249960 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 28403043 93.28% 93.28% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2047457 6.72% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 334 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 28322817 93.31% 93.31% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2031217 6.69% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 336 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 30450834 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 30354370 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -658,45 +659,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 145097 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 145097 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 145097 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 145097 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 145097 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 144355 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 144355 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 144355 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 144355 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 144355 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 112288 88.82% 88.82% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 14132 11.18% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 126420 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 145097 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 111959 88.88% 88.88% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 14012 11.12% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 125971 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144355 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 145097 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126420 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144355 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125971 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126420 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 271517 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125971 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 270326 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 90839106 # DTB read hits -system.cpu1.dtb.read_misses 112437 # DTB read misses -system.cpu1.dtb.write_hits 81787747 # DTB write hits -system.cpu1.dtb.write_misses 32660 # DTB write misses +system.cpu1.dtb.read_hits 91325952 # DTB read hits +system.cpu1.dtb.read_misses 111931 # DTB read misses +system.cpu1.dtb.write_hits 82141676 # DTB write hits +system.cpu1.dtb.write_misses 32424 # DTB write misses system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 44645 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 44858 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4653 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4450 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11499 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 90951543 # DTB read accesses -system.cpu1.dtb.write_accesses 81820407 # DTB write accesses +system.cpu1.dtb.perms_faults 11485 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 91437883 # DTB read accesses +system.cpu1.dtb.write_accesses 82174100 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 172626853 # DTB hits -system.cpu1.dtb.misses 145097 # DTB misses -system.cpu1.dtb.accesses 172771950 # DTB accesses +system.cpu1.dtb.hits 173467628 # DTB hits +system.cpu1.dtb.misses 144355 # DTB misses +system.cpu1.dtb.accesses 173611983 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -726,438 +727,438 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 61573 # Table walker walks requested -system.cpu1.itb.walker.walksLong 61573 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 61573 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 61573 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 61573 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 61638 # Table walker walks requested +system.cpu1.itb.walker.walksLong 61638 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 61638 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 61638 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 61638 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 54551 99.05% 99.05% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 525 0.95% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55076 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 54650 99.05% 99.05% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 526 0.95% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55176 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61573 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61573 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61638 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61638 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55076 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55076 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 116649 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 481656543 # ITB inst hits -system.cpu1.itb.inst_misses 61573 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55176 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55176 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 116814 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 483902380 # ITB inst hits +system.cpu1.itb.inst_misses 61638 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 31343 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 31512 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 481718116 # ITB inst accesses -system.cpu1.itb.hits 481656543 # DTB hits -system.cpu1.itb.misses 61573 # DTB misses -system.cpu1.itb.accesses 481718116 # DTB accesses -system.cpu1.numCycles 94513077683 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 483964018 # ITB inst accesses +system.cpu1.itb.hits 483902380 # DTB hits +system.cpu1.itb.misses 61638 # DTB misses +system.cpu1.itb.accesses 483964018 # DTB accesses +system.cpu1.numCycles 94433635768 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 6271 # number of quiesce instructions executed -system.cpu1.committedInsts 481403040 # Number of instructions committed -system.cpu1.committedOps 566527691 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 519926686 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 376275 # Number of float alu accesses -system.cpu1.num_func_calls 28379648 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 73708476 # number of instructions that are conditional controls -system.cpu1.num_int_insts 519926686 # number of integer instructions -system.cpu1.num_fp_insts 376275 # number of float instructions -system.cpu1.num_int_register_reads 767885454 # number of times the integer registers were read -system.cpu1.num_int_register_writes 413863113 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 612543 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 304496 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 127271010 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 126985650 # number of times the CC registers were written -system.cpu1.num_mem_refs 172748485 # number of memory refs -system.cpu1.num_load_insts 90938541 # Number of load instructions -system.cpu1.num_store_insts 81809944 # Number of store instructions -system.cpu1.num_idle_cycles 93946236472.485764 # Number of idle cycles -system.cpu1.num_busy_cycles 566841210.514243 # Number of busy cycles -system.cpu1.not_idle_fraction 0.005997 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.994003 # Percentage of idle cycles -system.cpu1.Branches 107246711 # Number of branches fetched +system.cpu1.kern.inst.quiesce 6163 # number of quiesce instructions executed +system.cpu1.committedInsts 483651505 # Number of instructions committed +system.cpu1.committedOps 569122264 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 522328734 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 379089 # Number of float alu accesses +system.cpu1.num_func_calls 28525698 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 74077236 # number of instructions that are conditional controls +system.cpu1.num_int_insts 522328734 # number of integer instructions +system.cpu1.num_fp_insts 379089 # number of float instructions +system.cpu1.num_int_register_reads 771436981 # number of times the integer registers were read +system.cpu1.num_int_register_writes 415765246 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 615128 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 311192 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 127876698 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 127597836 # number of times the CC registers were written +system.cpu1.num_mem_refs 173588529 # number of memory refs +system.cpu1.num_load_insts 91424864 # Number of load instructions +system.cpu1.num_store_insts 82163665 # Number of store instructions +system.cpu1.num_idle_cycles 93864202487.047195 # Number of idle cycles +system.cpu1.num_busy_cycles 569433280.952807 # Number of busy cycles +system.cpu1.not_idle_fraction 0.006030 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.993970 # Percentage of idle cycles +system.cpu1.Branches 107756231 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 392852056 69.31% 69.31% # Class of executed instruction -system.cpu1.op_class::IntMult 1138487 0.20% 69.51% # Class of executed instruction -system.cpu1.op_class::IntDiv 60879 0.01% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 36493 0.01% 69.52% # Class of executed instruction +system.cpu1.op_class::IntAlu 394594292 69.30% 69.30% # Class of executed instruction +system.cpu1.op_class::IntMult 1146816 0.20% 69.50% # Class of executed instruction +system.cpu1.op_class::IntDiv 61459 0.01% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 37349 0.01% 69.52% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::MemRead 90938541 16.04% 85.57% # Class of executed instruction -system.cpu1.op_class::MemWrite 81809944 14.43% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 91424864 16.06% 85.57% # Class of executed instruction +system.cpu1.op_class::MemWrite 82163665 14.43% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 566836400 # Class of executed instruction -system.cpu1.dcache.tags.replacements 5963482 # number of replacements -system.cpu1.dcache.tags.tagsinuse 422.067067 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 166672957 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5963994 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.946533 # Average number of references to valid blocks. +system.cpu1.op_class::total 569428445 # Class of executed instruction +system.cpu1.dcache.tags.replacements 6003966 # number of replacements +system.cpu1.dcache.tags.tagsinuse 423.687505 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 167475451 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 6004478 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.891759 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 422.067067 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.824350 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.824350 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 423.687505 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.827515 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.827515 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 348 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 248 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 351517490 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 351517490 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 84375671 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 84375671 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 77626026 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 77626026 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188285 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 188285 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64910 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 64910 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062470 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 2062470 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2047982 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 2047982 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 162066607 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 162066607 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 162254892 # number of overall hits -system.cpu1.dcache.overall_hits::total 162254892 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3369907 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3369907 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1463877 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1463877 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 790298 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 790298 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 435843 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 435843 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 145888 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 145888 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158992 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 158992 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5269627 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5269627 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6059925 # number of overall misses -system.cpu1.dcache.overall_misses::total 6059925 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 87745578 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 87745578 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 79089903 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 79089903 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 978583 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 978583 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 500753 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 500753 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2208358 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2208358 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2206974 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2206974 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 167336234 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 167336234 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 168314817 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 168314817 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038405 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.038405 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018509 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018509 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.807594 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.807594 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870375 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870375 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066062 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066062 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072041 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072041 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031491 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031491 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036004 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.036004 # miss rate for overall accesses +system.cpu1.dcache.tags.tag_accesses 353236361 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 353236361 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 84832048 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 84832048 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 77963660 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 77963660 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187526 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 187526 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 65427 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 65427 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2067288 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 2067288 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2056969 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2056969 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 162861135 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 162861135 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 163048661 # number of overall hits +system.cpu1.dcache.overall_hits::total 163048661 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3388721 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3388721 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1469364 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1469364 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 795051 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 795051 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 438458 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 438458 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 148516 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 148516 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 157576 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 157576 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5296543 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5296543 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6091594 # number of overall misses +system.cpu1.dcache.overall_misses::total 6091594 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 88220769 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 88220769 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 79433024 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 79433024 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 982577 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 982577 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 503885 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 503885 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2215804 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2215804 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2214545 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2214545 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 168157678 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 168157678 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 169140255 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 169140255 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038412 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.038412 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018498 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018498 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.809149 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.809149 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870155 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870155 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067026 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067026 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071155 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071155 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031497 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031497 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036015 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.036015 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5963482 # number of writebacks -system.cpu1.dcache.writebacks::total 5963482 # number of writebacks -system.cpu1.icache.tags.replacements 4804881 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.439171 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 476906226 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4805393 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 99.243959 # Average number of references to valid blocks. +system.cpu1.dcache.writebacks::writebacks 6003966 # number of writebacks +system.cpu1.dcache.writebacks::total 6003966 # number of writebacks +system.cpu1.icache.tags.replacements 4799154 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 479157890 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4799666 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 99.831507 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.439171 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969608 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969608 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 968228631 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 968228631 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 476906226 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 476906226 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 476906226 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 476906226 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 476906226 # number of overall hits -system.cpu1.icache.overall_hits::total 476906226 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4805393 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4805393 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4805393 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4805393 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4805393 # number of overall misses -system.cpu1.icache.overall_misses::total 4805393 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 481711619 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 481711619 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 481711619 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 481711619 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 481711619 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 481711619 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009976 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.009976 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009976 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.009976 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009976 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.009976 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 972714778 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 972714778 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 479157890 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 479157890 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 479157890 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 479157890 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 479157890 # number of overall hits +system.cpu1.icache.overall_hits::total 479157890 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4799666 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4799666 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4799666 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4799666 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4799666 # number of overall misses +system.cpu1.icache.overall_misses::total 4799666 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 483957556 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 483957556 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 483957556 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 483957556 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 483957556 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 483957556 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009918 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.009918 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009918 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.009918 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009918 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.009918 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 4804881 # number of writebacks -system.cpu1.icache.writebacks::total 4804881 # number of writebacks +system.cpu1.icache.writebacks::writebacks 4799154 # number of writebacks +system.cpu1.icache.writebacks::total 4799154 # number of writebacks system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2274505 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13370.273853 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 14355408 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2290637 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.266994 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9713557342500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 13266.664229 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 44.449121 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 59.160502 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.809733 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002713 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003611 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.816057 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 16066 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 37 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 307 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1542 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5867 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4427 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3923 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004028 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.980591 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 364664430 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 364664430 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 349739 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155441 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 505180 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 4030758 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 4030758 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 6737219 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 6737219 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1036 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1036 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 606945 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 606945 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4338204 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4338204 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3075973 # 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Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 13228.741418 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 51.265537 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.948066 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.807418 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003129 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004025 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.814572 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15957 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 53 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1511 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4384 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3784 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973938 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 365657601 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 365657601 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 347777 # 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number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 144957 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 157576 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 157576 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1324652 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1324652 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4799666 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 4799666 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4332288 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 4332288 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 438213 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 438213 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 360110 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165353 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 4799666 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5656940 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10982069 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 360110 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165353 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 4799666 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5656940 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 10982069 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.058179 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.041778 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.992729 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.992729 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.538617 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.538617 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097222 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097222 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.285670 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.285670 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.625907 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.625907 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059336 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097222 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.344861 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.221649 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059336 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097222 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.344861 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.221649 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.535264 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.535264 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097215 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097215 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.282838 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.282838 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.620897 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.620897 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.058179 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097215 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.341947 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.220626 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.058179 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097215 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.341947 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.220626 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.writebacks::writebacks 1199052 # number of writebacks -system.cpu1.l2cache.writebacks::total 1199052 # number of writebacks -system.cpu1.toL2Bus.snoop_filter.tot_requests 22219600 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11357015 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1768706 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1768522 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 184 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 610577 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9722063 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 5621 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5621 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4030758 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6737605 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 148621 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158992 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 307613 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1315491 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1315491 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4805393 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4306093 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 435608 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 435608 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14415927 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18716020 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368094 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 841114 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 34341155 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 615058056 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 741477723 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472376 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3364456 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1361372611 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5725702 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 28118123 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.072932 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.260049 # Request fanout histogram +system.cpu1.l2cache.writebacks::writebacks 1211269 # number of writebacks +system.cpu1.l2cache.writebacks::total 1211269 # number of writebacks +system.cpu1.toL2Bus.snoop_filter.tot_requests 22276444 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11381625 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1756231 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1756065 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 166 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 608590 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9740544 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 5562 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5562 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4070389 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6732731 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 144957 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 157576 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 302533 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1324652 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1324652 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4799666 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4332288 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 438213 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 438213 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14398746 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18822028 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368476 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 836878 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 34426128 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 614325000 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 746331191 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1473904 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3347512 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1365477607 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5687998 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 28144557 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.072239 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.258905 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 26067606 92.71% 92.71% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2050333 7.29% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 184 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 26111598 92.78% 92.78% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2032793 7.22% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 166 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 28118123 # Request fanout histogram -system.iobus.trans_dist::ReadReq 40311 # Transaction distribution -system.iobus.trans_dist::ReadResp 40311 # Transaction distribution +system.cpu1.toL2Bus.snoop_fanout::total 28144557 # Request fanout histogram +system.iobus.trans_dist::ReadReq 40301 # Transaction distribution +system.iobus.trans_dist::ReadResp 40301 # Transaction distribution system.iobus.trans_dist::WriteReq 136636 # Transaction distribution system.iobus.trans_dist::WriteResp 136636 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47642 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1170,13 +1171,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231230 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231230 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231218 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231218 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353894 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353874 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47662 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1189,54 +1190,54 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338936 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338936 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155683 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496713 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.replacements 115596 # number of replacements -system.iocache.tags.tagsinuse 11.294855 # Cycle average of tags in use +system.iobus.pkt_size::total 7496657 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115590 # number of replacements +system.iocache.tags.tagsinuse 11.289214 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115612 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.848747 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.446108 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240547 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465382 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705928 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9107775784009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.856196 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.433018 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.241012 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.464564 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705576 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040892 # Number of tag accesses -system.iocache.tags.data_accesses 1040892 # Number of data accesses +system.iocache.tags.tag_accesses 1040838 # Number of tag accesses +system.iocache.tags.data_accesses 1040838 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8924 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115615 # number of demand (read+write) misses -system.iocache.demand_misses::total 115655 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115609 # number of demand (read+write) misses +system.iocache.demand_misses::total 115649 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115615 # number of overall misses -system.iocache.overall_misses::total 115655 # number of overall misses +system.iocache.overall_misses::realview.ide 115609 # number of overall misses +system.iocache.overall_misses::total 115649 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8881 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8918 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115615 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115655 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115609 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115649 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115615 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115655 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115609 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115649 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1258,254 +1259,260 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks -system.l2c.tags.replacements 1766126 # number of replacements -system.l2c.tags.tagsinuse 63106.596515 # Cycle average of tags in use -system.l2c.tags.total_refs 4618110 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1825499 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.529780 # Average number of references to valid blocks. +system.l2c.tags.replacements 1772279 # number of replacements +system.l2c.tags.tagsinuse 63191.056766 # Cycle average of tags in use +system.l2c.tags.total_refs 4630026 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1831889 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.527460 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 34858.975183 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.002297 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 102.298868 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3405.442592 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8003.318713 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 244.723732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 389.512702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2881.151775 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 13153.170652 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.531906 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001561 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.051963 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.122121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003734 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.005943 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.043963 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.200701 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.962930 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 203 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 59170 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 472 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3156 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5264 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50220 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003098 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.902863 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 73355182 # Number of tag accesses -system.l2c.tags.data_accesses 73355182 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 2757627 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2757627 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 19019 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 16164 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 35183 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2641 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2463 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 5104 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 198159 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 177179 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 375338 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6315 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4649 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 438189 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 723007 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5487 # 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number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 12865 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 376689 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 423433 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 800122 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2349 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1944 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 58179 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 178934 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3469 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3479 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 41697 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 188396 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 478447 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 477304 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 163191 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 640495 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2349 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1944 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 58179 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 555623 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3469 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 3479 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 41697 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 611829 # number of demand (read+write) misses +system.l2c.demand_misses::total 1278569 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2349 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1944 # number of overall misses +system.l2c.overall_misses::cpu0.inst 58179 # number of overall misses +system.l2c.overall_misses::cpu0.data 555623 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3469 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 3479 # number of overall misses +system.l2c.overall_misses::cpu1.inst 41697 # number of overall misses +system.l2c.overall_misses::cpu1.data 611829 # number of overall misses +system.l2c.overall_misses::total 1278569 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 2765418 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 2765418 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 82685 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 75606 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 158291 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 9067 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 8790 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 17857 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 576975 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 599647 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1176622 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8759 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6790 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 497229 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 905976 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9172 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7168 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 466598 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 873556 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 2775248 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 592993 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 265991 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 858984 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8759 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6790 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 497229 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1482951 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 9172 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7168 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 466598 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1473203 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3951870 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8759 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6790 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 497229 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1482951 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 9172 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7168 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 466598 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1473203 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3951870 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.784979 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.793998 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.789287 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.714569 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.726507 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.720446 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.652869 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.706137 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.680016 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.286303 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.117006 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.197504 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.485352 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.089364 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.215666 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.172398 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.804907 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.613521 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.745643 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.286303 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.117006 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.374674 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.485352 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.089364 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.415305 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.323535 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.286303 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.117006 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.374674 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.485352 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.089364 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.415305 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.323535 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1473799 # number of writebacks -system.l2c.writebacks::total 1473799 # number of writebacks -system.membus.trans_dist::ReadReq 82185 # Transaction distribution -system.membus.trans_dist::ReadResp 568654 # Transaction distribution -system.membus.trans_dist::WriteReq 38847 # Transaction distribution -system.membus.trans_dist::WriteResp 38847 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1580493 # Transaction distribution -system.membus.trans_dist::CleanEvict 246676 # Transaction distribution -system.membus.trans_dist::UpgradeReq 346899 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 310542 # Transaction distribution -system.membus.trans_dist::UpgradeResp 162598 # Transaction distribution -system.membus.trans_dist::ReadExReq 787734 # Transaction distribution -system.membus.trans_dist::ReadExResp 783864 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 486469 # Transaction distribution -system.membus.trans_dist::InvalidateReq 741739 # Transaction distribution -system.membus.trans_dist::InvalidateResp 741739 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes) +system.l2c.writebacks::writebacks 1477304 # number of writebacks +system.l2c.writebacks::total 1477304 # number of writebacks +system.membus.snoop_filter.tot_requests 4491425 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2595543 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3224 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 82119 # Transaction distribution +system.membus.trans_dist::ReadResp 569484 # Transaction distribution +system.membus.trans_dist::WriteReq 38800 # Transaction distribution +system.membus.trans_dist::WriteResp 38800 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1583998 # Transaction distribution +system.membus.trans_dist::CleanEvict 246737 # Transaction distribution +system.membus.trans_dist::UpgradeReq 335468 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 307268 # Transaction distribution +system.membus.trans_dist::UpgradeResp 157952 # Transaction distribution +system.membus.trans_dist::ReadExReq 787861 # Transaction distribution +system.membus.trans_dist::ReadExResp 784470 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 487365 # Transaction distribution +system.membus.trans_dist::InvalidateReq 742728 # Transaction distribution +system.membus.trans_dist::InvalidateResp 742728 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27742 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6419962 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6570380 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6917286 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27524 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6408698 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6558890 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346888 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346888 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6905778 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155683 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55484 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175247068 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 175458447 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7399552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 182857999 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175567900 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 175778835 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7399168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 183178003 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4621584 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 4612344 # Request fanout histogram +system.membus.snoop_fanout::mean 0.007156 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.084293 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4621584 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4579336 99.28% 99.28% # Request fanout histogram +system.membus.snoop_fanout::1 33008 0.72% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4621584 # Request fanout histogram +system.membus.snoop_fanout::total 4612344 # Request fanout histogram system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks @@ -1558,43 +1565,43 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 11149977 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5745476 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1663139 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 131712 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 118684 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 13028 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 82187 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3554361 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38847 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38847 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 2757627 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2018256 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 359820 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 315646 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 675466 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1363961 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1363961 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3472174 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 862491 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 862491 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9530168 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8235967 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17766135 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255951612 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 230454307 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 486405919 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1999071 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 13268387 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.283691 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.452962 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 11113814 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5721773 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1636305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 133991 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 120343 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 13648 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 82121 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3542094 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38800 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38800 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 2765418 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2011530 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 348672 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 312260 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 660932 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1356975 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1356975 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3459973 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 858984 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 858984 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9470177 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8222341 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17692518 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 254644772 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 231031359 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 485676131 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1806287 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 13039342 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.283997 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.453251 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 9517290 71.73% 71.73% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3738069 28.17% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 13028 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 9349855 71.70% 71.70% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3675839 28.19% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 13648 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13268387 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 13039342 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index a0709a582..8deb7dd1b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu sim_ticks 51111167216500 # Number of ticks simulated final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1114977 # Simulator instruction rate (inst/s) -host_op_rate 1310339 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58020354238 # Simulator tick rate (ticks/s) -host_mem_usage 675736 # Number of bytes of host memory used -host_seconds 880.92 # Real time elapsed on the host +host_inst_rate 1142928 # Simulator instruction rate (inst/s) +host_op_rate 1343188 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59474849541 # Simulator tick rate (ticks/s) +host_mem_usage 670860 # Number of bytes of host memory used +host_seconds 859.37 # Real time elapsed on the host sim_insts 982203438 # Number of instructions simulated sim_ops 1154301153 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 3b055f28d..b7a4b232f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.460623 # Number of seconds simulated -sim_ticks 47460623015500 # Number of ticks simulated -final_tick 47460623015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.522770 # Number of seconds simulated +sim_ticks 47522770414500 # Number of ticks simulated +final_tick 47522770414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 734945 # Simulator instruction rate (inst/s) -host_op_rate 864481 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39854660745 # Simulator tick rate (ticks/s) -host_mem_usage 745756 # Number of bytes of host memory used -host_seconds 1190.84 # Real time elapsed on the host -sim_insts 875204273 # Number of instructions simulated -sim_ops 1029460892 # Number of ops (including micro ops) simulated +host_inst_rate 771698 # Simulator instruction rate (inst/s) +host_op_rate 907739 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41601502224 # Simulator tick rate (ticks/s) +host_mem_usage 746908 # Number of bytes of host memory used +host_seconds 1142.33 # Real time elapsed on the host +sim_insts 881535802 # Number of instructions simulated +sim_ops 1036940641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 81920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 78144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3183732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 11874696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 12415040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 115712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 117120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2511992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9752208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 13330752 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 455552 # Number of bytes read from this memory -system.physmem.bytes_read::total 53916868 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3183732 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2511992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5695724 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 73320768 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 93760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 96448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3323828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13811400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 14713664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 137344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 135424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2499960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9313680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 12080896 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 425472 # Number of bytes read from this memory +system.physmem.bytes_read::total 56631876 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3323828 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2499960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5823788 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75221696 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 73341352 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1280 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1221 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 90153 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 185555 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 193985 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1808 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1830 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 39338 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 152391 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 208293 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 7118 # Number of read requests responded to by this memory -system.physmem.num_reads::total 882972 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1145637 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 75242280 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1465 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1507 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 92342 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 215816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 229901 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2146 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2116 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 39150 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 145539 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 188764 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6648 # Number of read requests responded to by this memory +system.physmem.num_reads::total 925394 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1175339 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1148211 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 67082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 250201 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 261586 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52928 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 205480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 280880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1136034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 67082 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52928 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 120009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1544876 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1177913 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2030 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 290627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 309613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52606 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 195984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 254213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1191679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69942 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52606 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 122547 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1582856 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1545310 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1544876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1726 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 67082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 250635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 261586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 205480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 280880 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2681343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 882972 # Number of read requests accepted -system.physmem.writeReqs 1148211 # Number of write requests accepted -system.physmem.readBursts 882972 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1148211 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 56486656 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23552 # Total number of bytes read from write queue -system.physmem.bytesWritten 73339968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 53916868 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 73341352 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 368 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2256 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1583289 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1582856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 291060 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 309613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 195984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 254213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2774968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 925394 # Number of read requests accepted +system.physmem.writeReqs 1177913 # Number of write requests accepted +system.physmem.readBursts 925394 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1177913 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59200512 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 24704 # Total number of bytes read from write queue +system.physmem.bytesWritten 75241664 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56631876 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 75242280 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 386 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 53897 # Per bank write bursts -system.physmem.perBankRdBursts::1 57581 # Per bank write bursts -system.physmem.perBankRdBursts::2 50596 # Per bank write bursts -system.physmem.perBankRdBursts::3 56941 # Per bank write bursts -system.physmem.perBankRdBursts::4 52224 # Per bank write bursts -system.physmem.perBankRdBursts::5 57867 # Per bank write bursts -system.physmem.perBankRdBursts::6 48622 # Per bank write bursts -system.physmem.perBankRdBursts::7 53589 # Per bank write bursts -system.physmem.perBankRdBursts::8 50057 # Per bank write bursts -system.physmem.perBankRdBursts::9 95322 # Per bank write bursts -system.physmem.perBankRdBursts::10 46946 # Per bank write bursts -system.physmem.perBankRdBursts::11 52908 # Per bank write bursts -system.physmem.perBankRdBursts::12 47194 # Per bank write bursts -system.physmem.perBankRdBursts::13 52526 # Per bank write bursts -system.physmem.perBankRdBursts::14 52237 # Per bank write bursts -system.physmem.perBankRdBursts::15 54097 # Per bank write bursts -system.physmem.perBankWrBursts::0 68696 # Per bank write bursts -system.physmem.perBankWrBursts::1 73430 # Per bank write bursts -system.physmem.perBankWrBursts::2 69832 # Per bank write bursts -system.physmem.perBankWrBursts::3 74009 # Per bank write bursts -system.physmem.perBankWrBursts::4 72053 # Per bank write bursts -system.physmem.perBankWrBursts::5 74820 # Per bank write bursts -system.physmem.perBankWrBursts::6 69700 # Per bank write bursts -system.physmem.perBankWrBursts::7 72497 # Per bank write bursts -system.physmem.perBankWrBursts::8 69824 # Per bank write bursts -system.physmem.perBankWrBursts::9 74930 # Per bank write bursts -system.physmem.perBankWrBursts::10 66965 # Per bank write bursts -system.physmem.perBankWrBursts::11 71787 # Per bank write bursts -system.physmem.perBankWrBursts::12 69900 # Per bank write bursts -system.physmem.perBankWrBursts::13 73092 # Per bank write bursts -system.physmem.perBankWrBursts::14 71437 # Per bank write bursts -system.physmem.perBankWrBursts::15 72965 # Per bank write bursts +system.physmem.perBankRdBursts::0 52385 # Per bank write bursts +system.physmem.perBankRdBursts::1 62471 # Per bank write bursts +system.physmem.perBankRdBursts::2 52469 # Per bank write bursts +system.physmem.perBankRdBursts::3 57006 # Per bank write bursts +system.physmem.perBankRdBursts::4 52192 # Per bank write bursts +system.physmem.perBankRdBursts::5 61065 # Per bank write bursts +system.physmem.perBankRdBursts::6 52770 # Per bank write bursts +system.physmem.perBankRdBursts::7 53841 # Per bank write bursts +system.physmem.perBankRdBursts::8 49119 # Per bank write bursts +system.physmem.perBankRdBursts::9 95933 # Per bank write bursts +system.physmem.perBankRdBursts::10 50791 # Per bank write bursts +system.physmem.perBankRdBursts::11 57135 # Per bank write bursts +system.physmem.perBankRdBursts::12 57588 # Per bank write bursts +system.physmem.perBankRdBursts::13 62036 # Per bank write bursts +system.physmem.perBankRdBursts::14 54549 # Per bank write bursts +system.physmem.perBankRdBursts::15 53658 # Per bank write bursts +system.physmem.perBankWrBursts::0 70290 # Per bank write bursts +system.physmem.perBankWrBursts::1 77699 # Per bank write bursts +system.physmem.perBankWrBursts::2 70837 # Per bank write bursts +system.physmem.perBankWrBursts::3 75524 # Per bank write bursts +system.physmem.perBankWrBursts::4 70767 # Per bank write bursts +system.physmem.perBankWrBursts::5 75365 # Per bank write bursts +system.physmem.perBankWrBursts::6 70544 # Per bank write bursts +system.physmem.perBankWrBursts::7 72537 # Per bank write bursts +system.physmem.perBankWrBursts::8 71114 # Per bank write bursts +system.physmem.perBankWrBursts::9 74364 # Per bank write bursts +system.physmem.perBankWrBursts::10 70757 # Per bank write bursts +system.physmem.perBankWrBursts::11 75591 # Per bank write bursts +system.physmem.perBankWrBursts::12 74466 # Per bank write bursts +system.physmem.perBankWrBursts::13 78806 # Per bank write bursts +system.physmem.perBankWrBursts::14 73579 # Per bank write bursts +system.physmem.perBankWrBursts::15 73411 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 49 # Number of times write queue was full causing retry -system.physmem.totGap 47460619650000 # Total gap between requests +system.physmem.numWrRetry 43 # Number of times write queue was full causing retry +system.physmem.totGap 47522767065000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 839747 # Read request sizes (log2) +system.physmem.readPktSize::6 882169 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1145637 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 632223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 71339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 35282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 27029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 24072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 21057 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 14779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1175339 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 655692 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 79783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38713 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 28749 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 25275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 22122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17971 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2679 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,164 +188,169 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 33201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 52179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 57658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 63950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 67460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 69091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 68874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 71191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 73992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 71007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 71950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 78189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 71162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 66652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 64454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 141 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 939668 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 138.161751 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 95.082106 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 185.728908 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 647019 68.86% 68.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 180648 19.22% 88.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 40379 4.30% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 17830 1.90% 94.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14299 1.52% 95.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8441 0.90% 96.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5223 0.56% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4905 0.52% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20924 2.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 939668 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60779 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.521496 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 130.920998 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60776 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 31337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 39682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 50193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 64392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 67139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 68853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 71615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 71812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 75238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 77530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 73364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 73677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 78266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 71127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 65923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 63783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 126 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 971842 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 138.337154 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 95.235739 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 185.809364 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 667325 68.67% 68.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 188611 19.41% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 42123 4.33% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 19056 1.96% 94.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13469 1.39% 95.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8562 0.88% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6056 0.62% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5131 0.53% 97.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21509 2.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 971842 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61007 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.162244 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 130.580515 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 61004 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60779 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60779 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.854160 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.212866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.632019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 48749 80.21% 80.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 9610 15.81% 96.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 589 0.97% 96.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 189 0.31% 97.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 137 0.23% 97.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 124 0.20% 97.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 218 0.36% 98.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 91 0.15% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 270 0.44% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 61 0.10% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 30 0.05% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 50 0.08% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 255 0.42% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 52 0.09% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 24 0.04% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 99 0.16% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 170 0.28% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 22 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 13 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60779 # Writes before turning the bus around for reads -system.physmem.totQLat 27990688881 # Total ticks spent queuing -system.physmem.totMemAccLat 44539513881 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4413020000 # Total ticks spent in databus transfers -system.physmem.avgQLat 31713.76 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 61007 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61007 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.270756 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.528593 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.773323 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 49057 80.41% 80.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4844 7.94% 88.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 2913 4.77% 93.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1752 2.87% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 961 1.58% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 299 0.49% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 177 0.29% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 148 0.24% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 74 0.12% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 52 0.09% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 27 0.04% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 55 0.09% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 405 0.66% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 51 0.08% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 50 0.08% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 40 0.07% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 25 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 4 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 8 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 7 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 8 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61007 # Writes before turning the bus around for reads +system.physmem.totQLat 29196891613 # Total ticks spent queuing +system.physmem.totMemAccLat 46540791613 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4625040000 # Total ticks spent in databus transfers +system.physmem.avgQLat 31563.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 50463.76 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 50313.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing -system.physmem.readRowHits 659544 # Number of row buffer hits during reads -system.physmem.writeRowHits 429323 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 37.46 # Row buffer hit rate for writes -system.physmem.avgGap 23365998.85 # Average gap between requests -system.physmem.pageHitRate 53.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3575759040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1951059000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3364272600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3726194400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3099896966400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1199863250505 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27423860344500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31736237846445 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.685699 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45621402632571 # Time in different power states -system.physmem_0.memoryStateTime::REF 1584814400000 # Time in different power states +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing +system.physmem.readRowHits 690198 # Number of row buffer hits during reads +system.physmem.writeRowHits 438618 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 37.31 # Row buffer hit rate for writes +system.physmem.avgGap 22594308.42 # Average gap between requests +system.physmem.pageHitRate 53.74 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3631876920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1981678875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3464752200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3781488240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3103956292320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1186873055955 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27472545160500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31776234305010 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.652826 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45702691627494 # Time in different power states +system.physmem_0.memoryStateTime::REF 1586889720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 254405603429 # Time in different power states +system.physmem_0.memoryStateTime::ACT 233188460006 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3528047880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1925026125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3519999600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3699373680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3099896966400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1198418138910 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27425127986250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31736115538845 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.683122 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45623502554973 # Time in different power states -system.physmem_1.memoryStateTime::REF 1584814400000 # Time in different power states +system.physmem_1.actEnergy 3715248600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2027169375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3750271200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3836730240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3103956292320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1194406095015 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27465937231500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31777629038250 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.682174 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45691606890492 # Time in different power states +system.physmem_1.memoryStateTime::REF 1586889720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 252305273527 # Time in different power states +system.physmem_1.memoryStateTime::ACT 244273354008 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -409,69 +414,73 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 102194 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 102194 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9208 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76624 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 102185 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.254440 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 81.335431 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 102184 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 111522 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 111522 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12043 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84023 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 24 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 111498 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.224219 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 74.869765 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 111497 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 102185 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 85841 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22586.042800 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 20965.618936 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16893.735669 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 85046 99.07% 99.07% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 170 0.20% 99.27% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 522 0.61% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 25 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 28 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 14 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 28 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 85841 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 4536625496 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.282786 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.450353 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 3253731032 71.72% 71.72% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 1282894464 28.28% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 4536625496 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 76625 89.27% 89.27% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9208 10.73% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 85833 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 102194 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 111498 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 96090 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22204.527006 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 20954.891968 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 12694.708371 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 91679 95.41% 95.41% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3478 3.62% 99.03% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 141 0.15% 99.18% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 658 0.68% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 17 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 14 0.01% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 32 0.03% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 16 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 20 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 23 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 96090 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 2194735056 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.089935 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -197382796 -8.99% -8.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 2392117852 108.99% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 2194735056 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 84024 87.46% 87.46% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 12043 12.54% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 96067 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 111522 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 102194 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85833 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 111522 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96067 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85833 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 188027 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96067 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 207589 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 85563003 # DTB read hits -system.cpu0.dtb.read_misses 75756 # DTB read misses -system.cpu0.dtb.write_hits 77475573 # DTB write hits -system.cpu0.dtb.write_misses 26438 # DTB write misses +system.cpu0.dtb.read_hits 86856517 # DTB read hits +system.cpu0.dtb.read_misses 84644 # DTB read misses +system.cpu0.dtb.write_hits 78666499 # DTB write hits +system.cpu0.dtb.write_misses 26878 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 34001 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 37476 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4044 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4693 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 8915 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 85638759 # DTB read accesses -system.cpu0.dtb.write_accesses 77502011 # DTB write accesses +system.cpu0.dtb.perms_faults 9143 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 86941161 # DTB read accesses +system.cpu0.dtb.write_accesses 78693377 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 163038576 # DTB hits -system.cpu0.dtb.misses 102194 # DTB misses -system.cpu0.dtb.accesses 163140770 # DTB accesses +system.cpu0.dtb.hits 165523016 # DTB hits +system.cpu0.dtb.misses 111522 # DTB misses +system.cpu0.dtb.accesses 165634538 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -501,854 +510,854 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 56381 # Table walker walks requested -system.cpu0.itb.walker.walksLong 56381 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 642 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 50009 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 56381 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 56381 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 56381 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 50651 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25304.495469 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23033.115990 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 21560.503846 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 49913 98.54% 98.54% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 55 0.11% 98.65% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 593 1.17% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 11 0.02% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 28 0.06% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.03% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 34 0.07% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 57441 # Table walker walks requested +system.cpu0.itb.walker.walksLong 57441 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 633 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51280 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 57441 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 57441 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 57441 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 51913 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 24992.593377 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23133.831517 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 17289.167601 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 50947 98.14% 98.14% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 829 1.60% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 33 0.06% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 47 0.09% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 45 0.09% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 50651 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 50009 98.73% 98.73% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 642 1.27% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 50651 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 51913 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -282313796 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -282313796 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -282313796 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 51280 98.78% 98.78% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 633 1.22% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 51913 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56381 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 56381 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57441 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57441 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50651 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50651 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 107032 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 455204971 # ITB inst hits -system.cpu0.itb.inst_misses 56381 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51913 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51913 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 109354 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 461199865 # ITB inst hits +system.cpu0.itb.inst_misses 57441 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24108 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26626 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 455261352 # ITB inst accesses -system.cpu0.itb.hits 455204971 # DTB hits -system.cpu0.itb.misses 56381 # DTB misses -system.cpu0.itb.accesses 455261352 # DTB accesses -system.cpu0.numCycles 94921246031 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 461257306 # ITB inst accesses +system.cpu0.itb.hits 461199865 # DTB hits +system.cpu0.itb.misses 57441 # DTB misses +system.cpu0.itb.accesses 461257306 # DTB accesses +system.cpu0.numCycles 95045540829 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13214 # number of quiesce instructions executed -system.cpu0.committedInsts 454926589 # Number of instructions committed -system.cpu0.committedOps 534313943 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 491049300 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 395385 # Number of float alu accesses -system.cpu0.num_func_calls 27308099 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 68959046 # number of instructions that are conditional controls -system.cpu0.num_int_insts 491049300 # number of integer instructions -system.cpu0.num_fp_insts 395385 # number of float instructions -system.cpu0.num_int_register_reads 709557386 # number of times the integer registers were read -system.cpu0.num_int_register_writes 389375063 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 654866 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 293356 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 117980325 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 117652107 # number of times the CC registers were written -system.cpu0.num_mem_refs 163029477 # number of memory refs -system.cpu0.num_load_insts 85557806 # Number of load instructions -system.cpu0.num_store_insts 77471671 # Number of store instructions -system.cpu0.num_idle_cycles 93727706914.782028 # Number of idle cycles -system.cpu0.num_busy_cycles 1193539116.217975 # Number of busy cycles -system.cpu0.not_idle_fraction 0.012574 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.987426 # Percentage of idle cycles -system.cpu0.Branches 101606994 # Number of branches fetched +system.cpu0.kern.inst.quiesce 13927 # number of quiesce instructions executed +system.cpu0.committedInsts 460929213 # Number of instructions committed +system.cpu0.committedOps 541179982 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 497492129 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 434558 # Number of float alu accesses +system.cpu0.num_func_calls 27781850 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 69589132 # number of instructions that are conditional controls +system.cpu0.num_int_insts 497492129 # number of integer instructions +system.cpu0.num_fp_insts 434558 # number of float instructions +system.cpu0.num_int_register_reads 719293830 # number of times the integer registers were read +system.cpu0.num_int_register_writes 394367415 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 718787 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 331792 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 119457726 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 119087316 # number of times the CC registers were written +system.cpu0.num_mem_refs 165514046 # number of memory refs +system.cpu0.num_load_insts 86852092 # Number of load instructions +system.cpu0.num_store_insts 78661954 # Number of store instructions +system.cpu0.num_idle_cycles 93905101360.384018 # Number of idle cycles +system.cpu0.num_busy_cycles 1140439468.615976 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011999 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988001 # Percentage of idle cycles +system.cpu0.Branches 102755128 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 370328410 69.27% 69.27% # Class of executed instruction -system.cpu0.op_class::IntMult 1177627 0.22% 69.49% # Class of executed instruction -system.cpu0.op_class::IntDiv 60510 0.01% 69.50% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 39424 0.01% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::MemRead 85557806 16.00% 85.51% # Class of executed instruction -system.cpu0.op_class::MemWrite 77471671 14.49% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 374676211 69.19% 69.19% # Class of executed instruction +system.cpu0.op_class::IntMult 1194745 0.22% 69.41% # Class of executed instruction +system.cpu0.op_class::IntDiv 63344 0.01% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 45411 0.01% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::MemRead 86852092 16.04% 85.47% # Class of executed instruction +system.cpu0.op_class::MemWrite 78661954 14.53% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 534635449 # Class of executed instruction -system.cpu0.dcache.tags.replacements 5459134 # number of replacements -system.cpu0.dcache.tags.tagsinuse 479.881862 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 157334556 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5459646 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.817721 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.881862 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937269 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.937269 # Average percentage of cache occupancy +system.cpu0.op_class::total 541493758 # Class of executed instruction +system.cpu0.dcache.tags.replacements 5689621 # number of replacements +system.cpu0.dcache.tags.tagsinuse 508.423656 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 159582136 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5690133 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.045414 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.423656 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.993015 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.993015 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 331496751 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 331496751 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 79723477 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 79723477 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73152105 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73152105 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199556 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 199556 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 181390 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 181390 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1847375 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1847375 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1814831 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1814831 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 153056972 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 153056972 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 153256528 # number of overall hits -system.cpu0.dcache.overall_hits::total 153256528 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2983943 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 2983943 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1350734 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1350734 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 619590 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 619590 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 750130 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 750130 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 159632 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 159632 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 191006 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 191006 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5084807 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5084807 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5704397 # number of overall misses -system.cpu0.dcache.overall_misses::total 5704397 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47916762500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 47916762500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34952130000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 34952130000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46124909500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 46124909500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2449383000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2449383000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5329904000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5329904000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5776000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5776000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 128993802000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 128993802000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 128993802000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 128993802000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 82707420 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 82707420 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74502839 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74502839 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 819146 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 819146 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 931520 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 931520 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2007007 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2007007 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2005837 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2005837 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 158141779 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 158141779 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 158960925 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 158960925 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036078 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036078 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018130 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018130 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.756385 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.756385 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.805275 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.805275 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079537 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079537 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095225 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095225 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032153 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.032153 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.035886 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.035886 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16058.203022 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16058.203022 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25876.397573 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25876.397573 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 61489.221202 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 61489.221202 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15343.934800 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15343.934800 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27904.379967 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27904.379967 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 336711039 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 336711039 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 80892970 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 80892970 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 74279623 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 74279623 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199389 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 199389 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 162229 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 162229 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1824290 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1824290 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1791894 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1791894 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 155334822 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 155334822 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 155534211 # number of overall hits +system.cpu0.dcache.overall_hits::total 155534211 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3104051 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3104051 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1401631 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1401631 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 634089 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 634089 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 792659 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 792659 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 174131 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 174131 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 205146 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 205146 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5298341 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5298341 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5932430 # number of overall misses +system.cpu0.dcache.overall_misses::total 5932430 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46355544000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 46355544000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29179707500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 29179707500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25804948000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 25804948000 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2634324500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2634324500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5093103500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5093103500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3129500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3129500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 101340199500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 101340199500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 101340199500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 101340199500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 83997021 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 83997021 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 75681254 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 75681254 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 833478 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 833478 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 954888 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 954888 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1998421 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1998421 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1997040 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1997040 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 160633163 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 160633163 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 161466641 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 161466641 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036954 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036954 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018520 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018520 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760775 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760775 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.830107 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.830107 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087134 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087134 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102725 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102725 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032984 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.032984 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036741 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.036741 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14933.886073 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14933.886073 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20818.394784 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20818.394784 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32554.917058 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32554.917058 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15128.406200 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15128.406200 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24826.725844 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24826.725844 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25368.475539 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25368.475539 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.047795 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22613.047795 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19126.779401 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19126.779401 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17082.409653 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17082.409653 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5459134 # number of writebacks -system.cpu0.dcache.writebacks::total 5459134 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 24235 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 24235 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21402 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21402 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43300 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43300 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 45637 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 45637 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 45637 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 45637 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2959708 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2959708 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1329332 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1329332 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 618446 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 618446 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 750130 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 750130 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 116332 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 116332 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191006 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 191006 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5039170 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5039170 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5657616 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5657616 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29450 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29450 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28924 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28924 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 58374 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58374 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43283569500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43283569500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 33090463000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33090463000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14878889500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14878889500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 45374779500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 45374779500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1623777500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1623777500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5138961000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5138961000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5713000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5713000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 121748812000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 121748812000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 136627701500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 136627701500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5439516500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5439516500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5439516500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5439516500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035785 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035785 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017843 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017843 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.754989 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.754989 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.805275 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.805275 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057963 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057963 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095225 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095225 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031865 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.031865 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035591 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.035591 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14624.270198 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14624.270198 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24892.549792 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24892.549792 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24058.510363 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24058.510363 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60489.221202 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60489.221202 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13958.132758 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13958.132758 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26904.709800 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26904.709800 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5689621 # number of writebacks +system.cpu0.dcache.writebacks::total 5689621 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25484 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25484 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21272 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21272 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45280 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45280 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 46756 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 46756 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 46756 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 46756 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3078567 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3078567 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1380359 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1380359 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 632927 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 632927 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792659 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 792659 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128851 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128851 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 205146 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 205146 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5251585 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5251585 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5884512 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5884512 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 27617 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 27617 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26565 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26565 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 54182 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 54182 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42188847000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42188847000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27459987000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27459987000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13648405000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13648405000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25012289000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25012289000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1718421000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1718421000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4888014500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4888014500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3072500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3072500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 94661123000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 94661123000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108309528000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 108309528000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5072174500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5072174500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5072174500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5072174500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036651 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036651 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018239 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018239 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759381 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759381 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.830107 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.830107 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064476 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064476 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102725 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102725 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032693 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032693 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036444 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.036444 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13704.053542 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13704.053542 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19893.366146 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19893.366146 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21563.948133 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21563.948133 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31554.917058 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31554.917058 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13336.497194 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13336.497194 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23827.003695 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23827.003695 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24160.489128 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24160.489128 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24149.341613 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24149.341613 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184703.446520 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184703.446520 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93183.891801 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93183.891801 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 5000286 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.853700 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 450204172 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5000798 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 90.026466 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 46470060000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.853700 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999714 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999714 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18025.248187 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18025.248187 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18405.864072 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18405.864072 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183661.313684 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183661.313684 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93613.644753 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93613.644753 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 5142905 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.908178 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 456056448 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5143417 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 88.667990 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 29905343000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.908178 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999821 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999821 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 134 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 915410741 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 915410741 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 450204172 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 450204172 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 450204172 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 450204172 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 450204172 # number of overall hits -system.cpu0.icache.overall_hits::total 450204172 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5000799 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5000799 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5000799 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5000799 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5000799 # number of overall misses -system.cpu0.icache.overall_misses::total 5000799 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 55488072500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 55488072500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 55488072500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 55488072500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 55488072500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 55488072500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 455204971 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 455204971 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 455204971 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 455204971 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 455204971 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 455204971 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010986 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.010986 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010986 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.010986 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010986 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.010986 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11095.841385 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 11095.841385 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11095.841385 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 11095.841385 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11095.841385 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11095.841385 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 927543147 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 927543147 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 456056448 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 456056448 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 456056448 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 456056448 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 456056448 # number of overall hits +system.cpu0.icache.overall_hits::total 456056448 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5143417 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5143417 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5143417 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5143417 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5143417 # number of overall misses +system.cpu0.icache.overall_misses::total 5143417 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54463305000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 54463305000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 54463305000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 54463305000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 54463305000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 54463305000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 461199865 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 461199865 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 461199865 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 461199865 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 461199865 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 461199865 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011152 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011152 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011152 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011152 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011152 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011152 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10588.934360 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10588.934360 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10588.934360 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10588.934360 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10588.934360 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10588.934360 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 5000286 # number of writebacks -system.cpu0.icache.writebacks::total 5000286 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5000799 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 5000799 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 5000799 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 5000799 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 5000799 # 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average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10088.934360 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10088.934360 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10088.934360 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7619798 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7619814 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 14 # 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Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 76.415973 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 899.486557 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.925151 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003244 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004664 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054900 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.987959 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1325 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14699 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 20 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 683 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 429 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1043 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4210 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6256 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3119 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.080872 # 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number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18926305000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18926305000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 275943500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 240837500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 13280903500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 37826279000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 51623963500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 275943500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 240837500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 13280903500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 37826279000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32427966574 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 84051930074 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4850886500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8346919000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4850886500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8346919000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.034474 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047549 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.039214 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998394 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998394 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998390 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998390 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221718 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221718 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.091775 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091775 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.245719 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245719 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755778 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755778 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039628 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.050848 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.091775 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240188 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.159779 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039628 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.050848 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.091775 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240188 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.212561 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.212561 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.089571 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.089571 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.244101 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.244101 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.730498 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.730498 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.034474 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047549 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.089571 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.236805 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157133 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.034474 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047549 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.089571 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.236805 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226157 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35218.843326 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55618.555748 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55618.555748 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30327.980817 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30327.980817 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19401.010006 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19401.010006 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 308176.294118 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 308176.294118 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57887.022480 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57887.022480 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33672.786836 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33686.225156 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33686.225156 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70074.831676 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70074.831676 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38834.979997 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37342.411589 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38834.979997 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55618.555748 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42706.485834 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176686.417657 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149282.624871 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89139.257204 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 106741.805338 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 21678176 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128402 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 962 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1759585 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1759287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 298 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 537700 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9321471 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28925 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28924 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5081322 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 6856856 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2248329 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 834927 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 427184 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348871 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 496915 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 134 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1135852 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1114697 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5000799 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4556956 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 799366 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 748142 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15088134 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17701155 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 319339 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 542421 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 33651049 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 640241940 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 663021135 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1207824 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1965272 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1306436171 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6076865 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 17397756 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.114750 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.318774 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.225203 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30740.646006 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45077.596675 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45077.596675 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20773.248301 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20773.248301 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16322.336666 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16322.336666 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 330625 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 330625 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43135.713443 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43135.713443 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28827.661168 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29046.893485 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29046.893485 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32766.637985 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32766.637985 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31972.336095 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31087.443131 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31972.336095 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45077.596675 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35316.144748 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175648.567911 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117990.995448 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89529.483961 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85779.224516 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 22441141 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11511110 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 870 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1820685 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1820422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 263 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 564136 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9642625 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 26565 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26565 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5274768 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 7068022 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2298392 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 883953 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 441648 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 374962 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 517397 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 66 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1188175 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1165072 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5143417 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4741538 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 839102 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 790706 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15515989 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18442402 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 326965 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 595128 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 34880484 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 658497108 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 690726071 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1243360 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2186248 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1352652787 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6279047 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 18012222 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.113865 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.317693 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 15401661 88.53% 88.53% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 1995797 11.47% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 298 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 15961520 88.61% 88.61% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2050439 11.38% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 263 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 17397756 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 21478508994 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 18012222 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 22247152499 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 177190009 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 190413774 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7544323500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7758250500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7836374127 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8155256101 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 168361000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 171545000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 296762000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 321847000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1379,69 +1388,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 108457 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 108457 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9827 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84631 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 108435 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.073777 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 24.294348 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-511 108434 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 105013 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 105013 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10670 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 79078 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 105006 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.076186 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 24.687831 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 105005 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 108435 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 94480 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23264.092930 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21359.678554 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 19330.218287 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 93351 98.81% 98.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 176 0.19% 98.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 798 0.84% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 40 0.04% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 45 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 27 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 24 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 94480 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 3353012192 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 1.550742 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1846644332 -55.07% -55.07% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 5199656524 155.07% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 3353012192 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 84631 89.60% 89.60% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 9827 10.40% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 94458 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108457 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 105006 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 89755 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22913.865523 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21179.498457 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15867.258739 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 88364 98.45% 98.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1205 1.34% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 34 0.04% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 69 0.08% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 59 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 89755 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -3159480544 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.804201 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.396815 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -618623648 19.58% 19.58% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -2540856896 80.42% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -3159480544 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 79078 88.11% 88.11% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10670 11.89% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 89748 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 105013 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 108457 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 94458 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 105013 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 89748 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 94458 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 202915 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 89748 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 194761 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 79507348 # DTB read hits -system.cpu1.dtb.read_misses 80723 # DTB read misses -system.cpu1.dtb.write_hits 72319570 # DTB write hits -system.cpu1.dtb.write_misses 27734 # DTB write misses +system.cpu1.dtb.read_hits 79229823 # DTB read hits +system.cpu1.dtb.read_misses 76992 # DTB read misses +system.cpu1.dtb.write_hits 72255246 # DTB write hits +system.cpu1.dtb.write_misses 28021 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 39844 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 37178 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4607 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4820 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10580 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 79588071 # DTB read accesses -system.cpu1.dtb.write_accesses 72347304 # DTB write accesses +system.cpu1.dtb.perms_faults 10425 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 79306815 # DTB read accesses +system.cpu1.dtb.write_accesses 72283267 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 151826918 # DTB hits -system.cpu1.dtb.misses 108457 # DTB misses -system.cpu1.dtb.accesses 151935375 # DTB accesses +system.cpu1.dtb.hits 151485069 # DTB hits +system.cpu1.dtb.misses 105013 # DTB misses +system.cpu1.dtb.accesses 151590082 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1471,857 +1478,868 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 59789 # Table walker walks requested -system.cpu1.itb.walker.walksLong 59789 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 555 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54230 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 59789 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 59789 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 59789 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 54785 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 26806.178699 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23797.611376 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 25937.791406 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 53612 97.86% 97.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 36 0.07% 97.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 992 1.81% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 28 0.05% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 57 0.10% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 37 0.07% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 54785 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1988115332 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1988115332 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1988115332 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 54230 98.99% 98.99% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 555 1.01% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 54785 # Table walker page sizes translated +system.cpu1.itb.walker.walks 58945 # Table walker walks requested +system.cpu1.itb.walker.walksLong 58945 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53052 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 58945 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 58945 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 58945 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 53613 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26471.741928 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23919.780193 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 20610.282304 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 48130 89.77% 89.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 4065 7.58% 97.36% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 53 0.10% 97.45% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 1140 2.13% 99.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.06% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 18 0.03% 99.67% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 57 0.11% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 23 0.04% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 51 0.10% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 22 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 16 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 53613 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1503172148 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1503172148 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1503172148 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 53052 98.95% 98.95% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 561 1.05% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 53613 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59789 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59789 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58945 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58945 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54785 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54785 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 114574 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 420546617 # ITB inst hits -system.cpu1.itb.inst_misses 59789 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53613 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53613 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 112558 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 420888418 # ITB inst hits +system.cpu1.itb.inst_misses 58945 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 27682 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25875 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 420606406 # ITB inst accesses -system.cpu1.itb.hits 420546617 # DTB hits -system.cpu1.itb.misses 59789 # DTB misses -system.cpu1.itb.accesses 420606406 # DTB accesses -system.cpu1.numCycles 94920662633 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 420947363 # ITB inst accesses +system.cpu1.itb.hits 420888418 # DTB hits +system.cpu1.itb.misses 58945 # DTB misses +system.cpu1.itb.accesses 420947363 # DTB accesses +system.cpu1.numCycles 95045540824 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5531 # number of quiesce instructions executed -system.cpu1.committedInsts 420277684 # Number of instructions committed -system.cpu1.committedOps 495146949 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 454880180 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 506575 # Number of float alu accesses -system.cpu1.num_func_calls 25039229 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 63957319 # number of instructions that are conditional controls -system.cpu1.num_int_insts 454880180 # number of integer instructions -system.cpu1.num_fp_insts 506575 # number of float instructions -system.cpu1.num_int_register_reads 664278142 # number of times the integer registers were read -system.cpu1.num_int_register_writes 361063382 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 809640 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 450820 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 110083158 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 109779727 # number of times the CC registers were written -system.cpu1.num_mem_refs 151817768 # number of memory refs -system.cpu1.num_load_insts 79504880 # Number of load instructions -system.cpu1.num_store_insts 72312888 # Number of store instructions -system.cpu1.num_idle_cycles 93883487625.302155 # Number of idle cycles -system.cpu1.num_busy_cycles 1037175007.697842 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010927 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989073 # Percentage of idle cycles -system.cpu1.Branches 93646526 # Number of branches fetched +system.cpu1.kern.inst.quiesce 4988 # number of quiesce instructions executed +system.cpu1.committedInsts 420606589 # Number of instructions committed +system.cpu1.committedOps 495760659 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 455422102 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 465343 # Number of float alu accesses +system.cpu1.num_func_calls 25050170 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 64233743 # number of instructions that are conditional controls +system.cpu1.num_int_insts 455422102 # number of integer instructions +system.cpu1.num_fp_insts 465343 # number of float instructions +system.cpu1.num_int_register_reads 665130045 # number of times the integer registers were read +system.cpu1.num_int_register_writes 361560137 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 742394 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 410584 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 110025684 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 109785328 # number of times the CC registers were written +system.cpu1.num_mem_refs 151477231 # number of memory refs +system.cpu1.num_load_insts 79227868 # Number of load instructions +system.cpu1.num_store_insts 72249363 # Number of store instructions +system.cpu1.num_idle_cycles 94048242615.068481 # Number of idle cycles +system.cpu1.num_busy_cycles 997298208.931515 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010493 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989507 # Percentage of idle cycles +system.cpu1.Branches 93889993 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 342430715 69.12% 69.12% # Class of executed instruction -system.cpu1.op_class::IntMult 1035788 0.21% 69.33% # Class of executed instruction -system.cpu1.op_class::IntDiv 58966 0.01% 69.34% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.34% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 72713 0.01% 69.36% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction -system.cpu1.op_class::MemRead 79504880 16.05% 85.40% # Class of executed instruction -system.cpu1.op_class::MemWrite 72312888 14.60% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 343412693 69.23% 69.23% # Class of executed instruction +system.cpu1.op_class::IntMult 1029907 0.21% 69.44% # Class of executed instruction +system.cpu1.op_class::IntDiv 56328 0.01% 69.45% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 66396 0.01% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::MemRead 79227868 15.97% 85.43% # Class of executed instruction +system.cpu1.op_class::MemWrite 72249363 14.57% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 495415992 # Class of executed instruction -system.cpu1.dcache.tags.replacements 5111729 # number of replacements -system.cpu1.dcache.tags.tagsinuse 453.815972 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 146515734 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5112105 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.660549 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8395596843000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 453.815972 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.886359 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.886359 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 376 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 373 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 308802786 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 308802786 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 74029008 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 74029008 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 68561672 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 68561672 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 171099 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 171099 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 145458 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 145458 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1631683 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1631683 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1602426 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1602426 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 142736138 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 142736138 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 142907237 # number of overall hits -system.cpu1.dcache.overall_hits::total 142907237 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2875045 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2875045 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1313230 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1313230 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 626301 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 626301 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 483495 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 483495 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 165519 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 165519 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193387 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 193387 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4671770 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4671770 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5298071 # number of overall misses -system.cpu1.dcache.overall_misses::total 5298071 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 45279528500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 45279528500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 30099423000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 30099423000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 18095848000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 18095848000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2729020500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2729020500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5550193500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5550193500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6333000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6333000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 93474799500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 93474799500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 93474799500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 93474799500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 76904053 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 76904053 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 69874902 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 69874902 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 797400 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 797400 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 628953 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 628953 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1797202 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1797202 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1795813 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1795813 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 147407908 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 147407908 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 148205308 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 148205308 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037385 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.037385 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018794 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018794 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.785429 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.785429 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.768730 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.768730 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092098 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092098 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.107688 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.107688 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031693 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031693 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035748 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035748 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15749.154709 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15749.154709 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22920.145748 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22920.145748 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37427.166775 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37427.166775 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16487.657006 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16487.657006 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28699.930709 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28699.930709 # average StoreCondReq miss latency +system.cpu1.op_class::total 496042597 # Class of executed instruction +system.cpu1.dcache.tags.replacements 5018466 # number of replacements +system.cpu1.dcache.tags.tagsinuse 434.493139 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 146277741 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5018977 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.144932 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8378732349000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 434.493139 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.848619 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.848619 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 308017993 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 308017993 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 73753622 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 73753622 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 68485479 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 68485479 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 174561 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 174561 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 162110 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 162110 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1665176 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1665176 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1621987 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1621987 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 142401211 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 142401211 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 142575772 # number of overall hits +system.cpu1.dcache.overall_hits::total 142575772 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2838030 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2838030 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1310627 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1310627 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 624714 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 624714 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 447850 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 447850 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162703 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 162703 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 204676 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 204676 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4596507 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4596507 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5221221 # number of overall misses +system.cpu1.dcache.overall_misses::total 5221221 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40862074000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 40862074000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24688918000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 24688918000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10778682000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10778682000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2442456000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2442456000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5069864000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5069864000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3108000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3108000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 76329674000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 76329674000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 76329674000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 76329674000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 76591652 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 76591652 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 69796106 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 69796106 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 799275 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 799275 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 609960 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 609960 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1827879 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1827879 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1826663 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1826663 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 146997718 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 146997718 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 147796993 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 147796993 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037054 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.037054 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018778 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018778 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.781601 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.781601 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.734228 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.734228 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089012 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089012 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112049 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112049 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031269 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031269 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035327 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035327 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14398.041599 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14398.041599 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18837.486180 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18837.486180 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24067.616389 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24067.616389 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15011.745327 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15011.745327 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24770.192890 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24770.192890 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20008.433527 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20008.433527 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17643.176073 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17643.176073 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16606.017134 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16606.017134 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14619.123381 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14619.123381 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5111729 # number of writebacks -system.cpu1.dcache.writebacks::total 5111729 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16692 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 16692 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 402 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 402 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44979 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44979 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 17094 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 17094 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 17094 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 17094 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2858353 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2858353 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1312828 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1312828 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 626301 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 626301 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 483495 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 483495 # number of WriteLineReq MSHR misses +system.cpu1.dcache.writebacks::writebacks 5018466 # number of writebacks +system.cpu1.dcache.writebacks::total 5018466 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16365 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 16365 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 405 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 405 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42163 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 42163 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 16770 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 16770 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 16770 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 16770 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2821665 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2821665 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1310222 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1310222 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 624714 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 624714 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 447850 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 447850 # number of WriteLineReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120540 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120540 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193387 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 193387 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4654676 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4654676 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5280977 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5280977 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8711 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8711 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9093 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9093 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17804 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17804 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40977017000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40977017000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 28757951500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 28757951500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14279978500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14279978500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 17612353000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 17612353000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1713373500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1713373500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5356877500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5356877500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6262000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6262000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 87347321500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 87347321500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101627300000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 101627300000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1460511000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1460511000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1460511000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1460511000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037168 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037168 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018788 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018788 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.785429 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.785429 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.768730 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.768730 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067071 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067071 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.107688 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.107688 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031577 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031577 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035633 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035633 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14335.883986 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14335.883986 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21905.345940 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21905.345940 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22800.504071 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22800.504071 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36427.166775 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36427.166775 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14214.148830 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14214.148830 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27700.297848 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27700.297848 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 204676 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 204676 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4579737 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4579737 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5204451 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5204451 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 11035 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 11035 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11949 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11949 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 22984 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 22984 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 37160053500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 37160053500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23356658000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23356658000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12967475000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12967475000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10330832000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10330832000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1654542500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1654542500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4865246000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4865246000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3050000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3050000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 70847543500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 70847543500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83815018500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 83815018500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1894238000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1894238000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1894238000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1894238000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036840 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036840 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018772 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018772 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.781601 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.781601 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.734228 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.734228 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065945 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065945 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112049 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112049 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031155 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031155 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035214 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035214 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13169.548299 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13169.548299 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17826.488946 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17826.488946 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20757.458613 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20757.458613 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23067.616389 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23067.616389 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13726.086776 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13726.086776 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23770.476265 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23770.476265 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18765.499790 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18765.499790 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19244.033822 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19244.033822 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167662.840087 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 167662.840087 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82032.745450 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82032.745450 # average overall mshr uncacheable latency -system.cpu1.icache.tags.replacements 4920276 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.059748 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 415625824 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4920788 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 84.463266 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8395565369000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.059748 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968867 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.968867 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15469.784291 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15469.784291 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16104.487966 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16104.487966 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171657.272315 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171657.272315 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82415.506439 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82415.506439 # average overall mshr uncacheable latency +system.cpu1.icache.tags.replacements 4797887 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.259979 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 416090013 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4798399 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 86.714342 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8378704245000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.259979 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969258 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969258 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 109 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 277 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 180 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 846014027 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 846014027 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 415625824 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 415625824 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 415625824 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 415625824 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 415625824 # number of overall hits -system.cpu1.icache.overall_hits::total 415625824 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4920793 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4920793 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4920793 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4920793 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4920793 # number of overall misses -system.cpu1.icache.overall_misses::total 4920793 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 53750624000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 53750624000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 53750624000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 53750624000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 53750624000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 53750624000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 420546617 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 420546617 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 420546617 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 420546617 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 420546617 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 420546617 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011701 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011701 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011701 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011701 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011701 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011701 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10923.162994 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10923.162994 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10923.162994 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10923.162994 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10923.162994 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10923.162994 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 846575240 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 846575240 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 416090013 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 416090013 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 416090013 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 416090013 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 416090013 # number of overall hits +system.cpu1.icache.overall_hits::total 416090013 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4798405 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4798405 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4798405 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4798405 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4798405 # number of overall misses +system.cpu1.icache.overall_misses::total 4798405 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50998473000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 50998473000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 50998473000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 50998473000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 50998473000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 50998473000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 420888418 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 420888418 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 420888418 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 420888418 # 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average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10628.213542 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10628.213542 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10628.213542 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 4920276 # number of writebacks -system.cpu1.icache.writebacks::total 4920276 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4920793 # 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number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4396610500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3329007000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3329007000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2614499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2614499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8260901500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8260901500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 12580419500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 12580419500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 23624853500 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 23624853500 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6839135500 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6839135500 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 356751500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 329343500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12580419500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 31885755000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 45152269500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 356751500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 329343500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12580419500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 31885755000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27876431726 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 73028701226 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9401500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1805437500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1814839000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9401500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1805437500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1814839000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.042585 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.058337 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.048696 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997567 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997567 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997389 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997389 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.212405 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.212405 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.091496 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091496 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.237963 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.237963 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.551002 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.551002 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.036189 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048991 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091496 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.231908 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.155189 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.036189 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048991 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091496 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.231908 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.226104 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.226104 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.095639 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.095639 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.251611 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.251611 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.565082 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.565082 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.042585 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.058337 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.095639 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245591 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.164542 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.042585 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.058337 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.095639 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245591 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.223558 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 43725.358499 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58844.826929 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58844.826929 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32316.734905 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32316.734905 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20196.741531 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20196.741531 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 409178.428571 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 409178.428571 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47670.371889 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47670.371889 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31865.767877 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33190.039911 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33190.039911 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 52151.457317 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 52151.457317 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36331.942504 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35129.272040 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36331.942504 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58844.826929 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42382.031452 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159620.192860 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 159209.840154 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78097.702763 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78396.226415 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 20782124 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10655468 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1707466 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1707307 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 159 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 502417 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9121363 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 9093 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 9093 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4367100 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6772532 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2206652 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 838214 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 373270 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 349428 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 455882 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 134 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1149239 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1127446 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4920793 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4454860 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 528061 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 481641 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14762082 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16505656 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 342155 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 581136 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 32191029 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 629828856 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 636046096 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1307840 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2129720 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1269312512 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5644458 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 16439732 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.118176 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.322847 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.234134 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 34156.170658 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40544.234544 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 40544.234544 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20963.093200 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20963.093200 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16265.559497 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16265.559497 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 261449.900000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261449.900000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33154.607626 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33154.607626 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27413.278436 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26323.631135 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26323.631135 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27139.318892 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27139.318892 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27807.991174 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27775.004552 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27807.991174 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40544.234544 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31570.422456 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85468.181818 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163610.104214 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162838.851503 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85468.181818 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78551.927428 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78584.870529 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 20384822 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10471744 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 887 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1760623 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1760449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 174 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 491097 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 8950741 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11949 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11949 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4279928 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6642170 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2284917 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 836860 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 390891 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 375101 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 483493 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1131381 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1109621 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4798405 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4426002 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 496716 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 445955 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14394916 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16294669 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 336160 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 556294 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 31582039 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 614163064 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 626579614 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1280144 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2019872 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1244042694 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5755928 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 16349135 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.122449 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.327837 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 14497106 88.18% 88.18% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1942467 11.82% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 159 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 14347367 87.76% 87.76% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2001594 12.24% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 174 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 16439732 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 20566237996 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 16349135 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 20146131499 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 185505924 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 187574309 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7381299500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7197716000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7535601373 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7451139989 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 178675000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 176142000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 314921000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 303810499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40334 # Transaction distribution -system.iobus.trans_dist::ReadResp 40334 # Transaction distribution -system.iobus.trans_dist::WriteReq 136621 # Transaction distribution -system.iobus.trans_dist::WriteResp 136621 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40346 # Transaction distribution +system.iobus.trans_dist::ReadResp 40346 # Transaction distribution +system.iobus.trans_dist::WriteReq 136634 # Transaction distribution +system.iobus.trans_dist::WriteResp 136634 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47740 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2334,13 +2352,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122616 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231214 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231214 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122674 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231206 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231206 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353910 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47760 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2353,17 +2371,17 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155723 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338872 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155781 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338840 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338840 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496681 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36912500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496707 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36949503 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 323000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -2373,81 +2391,81 @@ system.iobus.reqLayer10.occupancy 8000 # La system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26561500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26494000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 37416000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 37417500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567387857 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569020926 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92726000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92771000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147910000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147902000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115602 # number of replacements -system.iocache.tags.tagsinuse 11.206206 # Cycle average of tags in use +system.iocache.tags.replacements 115585 # number of replacements +system.iocache.tags.tagsinuse 11.243817 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115618 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9192082489000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.403530 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.802676 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.462721 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.237667 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.700388 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9095565849000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.827817 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.416000 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239239 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.463500 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.702739 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040820 # Number of tag accesses -system.iocache.tags.data_accesses 1040820 # Number of data accesses +system.iocache.tags.tag_accesses 1040784 # Number of tag accesses +system.iocache.tags.data_accesses 1040784 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8879 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8916 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8875 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8912 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115607 # number of demand (read+write) misses -system.iocache.demand_misses::total 115647 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115603 # number of demand (read+write) misses +system.iocache.demand_misses::total 115643 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115607 # number of overall misses -system.iocache.overall_misses::total 115647 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1680349949 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1685547949 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115603 # number of overall misses +system.iocache.overall_misses::total 115643 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1623231612 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1628431112 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13547011908 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13547011908 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15227361857 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15232928857 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15227361857 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15232928857 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12905416814 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12905416814 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14528648426 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14534216926 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14528648426 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14534216926 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8879 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8916 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8875 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8912 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115607 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115647 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115603 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115643 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115607 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115647 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115603 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115643 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2461,53 +2479,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 189249.909787 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 189047.549237 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182899.336563 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182723.419210 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126930.251743 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126930.251743 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 131716.607619 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 131719.187329 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 131716.607619 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 131719.187329 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33462 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120918.754348 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120918.754348 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125677.088190 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125681.769982 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125677.088190 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125681.769982 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31595 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3547 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3437 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.433888 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.192610 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106693 # number of writebacks -system.iocache.writebacks::total 106693 # number of writebacks +system.iocache.writebacks::writebacks 106695 # number of writebacks +system.iocache.writebacks::total 106695 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8879 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8916 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8875 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8912 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # 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number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8739459323 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8743027823 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2521,632 +2539,638 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # 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average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 81660.665816 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 81663.264875 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 81660.665816 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 81663.264875 # average overall mshr miss latency -system.l2c.tags.replacements 1288575 # number of replacements -system.l2c.tags.tagsinuse 63334.482670 # Cycle average of tags in use -system.l2c.tags.total_refs 5304464 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1347256 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.937235 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 17731050500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 24026.415823 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 182.847205 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 272.174490 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3917.360352 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 7074.037074 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11678.333096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 109.068959 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 171.850259 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3448.642027 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6022.848319 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6430.905066 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.366614 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002790 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004153 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.059774 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.107941 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.178197 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001664 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002622 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.052622 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.091901 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.098128 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.966408 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9960 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 230 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48491 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 46 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 303 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9611 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 230 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1722 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5705 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 40867 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.151978 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 269.420690 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2932.882407 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5116.369986 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10693.582513 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.352418 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003358 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062040 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.125440 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.127034 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002502 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124737.940144 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 127974.476238 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 160885.420087 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 142793.482590 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130436.335938 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128401.316953 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125250.014682 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 127289.062269 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 158491.805667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130757.481195 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129439.901639 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124737.940144 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127974.476238 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 160885.420087 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 142793.482590 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158683.209610 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 141646.746814 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 132359.879610 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80056.540977 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69295.670037 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 90220.331804 # average overall mshr uncacheable latency -system.membus.trans_dist::ReadReq 81394 # Transaction distribution -system.membus.trans_dist::ReadResp 801457 # Transaction distribution -system.membus.trans_dist::WriteReq 38017 # Transaction distribution -system.membus.trans_dist::WriteResp 38017 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1145637 # Transaction distribution -system.membus.trans_dist::CleanEvict 202586 # Transaction distribution -system.membus.trans_dist::UpgradeReq 388021 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 309846 # Transaction distribution -system.membus.trans_dist::UpgradeResp 24 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 139521 # Transaction distribution -system.membus.trans_dist::ReadExResp 122200 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 720063 # Transaction distribution -system.membus.trans_dist::InvalidateReq 663960 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122616 # Packet count per connected master and slave (bytes) +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.279334 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.314256 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.295560 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.261727 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.254174 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.257959 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.637146 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.479442 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.563792 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.238794 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.311107 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.106911 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.203478 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461026 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.263313 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.284830 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085105 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.150063 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.400238 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.231467 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.789622 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.483301 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.699157 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.238794 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.311107 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.106911 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.271982 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461026 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.263313 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.284830 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085105 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.198571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.400238 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.254149 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.238794 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.311107 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.106911 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.271982 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461026 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.263313 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.284830 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085105 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.198571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.400238 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.254149 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21804.686224 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21789.373306 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21797.121392 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24741.881127 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24821.487996 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24781.010243 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77565.508997 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73518.653872 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 75964.793177 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75346.409144 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78972.962237 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75860.663099 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81122.516121 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96202.092831 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19963.677770 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20378.857088 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20048.436388 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75346.409144 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78452.136670 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75860.663099 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78418.732639 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 93138.115636 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75346.409144 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78452.136670 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75860.663099 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78418.732639 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 93138.115636 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 157644.476482 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67463.636364 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145634.098069 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106095.762484 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80352.654147 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67463.636364 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69914.759551 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 72157.173324 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3697678 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2246661 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3188 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 81885 # Transaction distribution +system.membus.trans_dist::ReadResp 837971 # Transaction distribution +system.membus.trans_dist::WriteReq 38514 # Transaction distribution +system.membus.trans_dist::WriteResp 38514 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1175339 # Transaction distribution +system.membus.trans_dist::CleanEvict 216465 # Transaction distribution +system.membus.trans_dist::UpgradeReq 402269 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 335845 # Transaction distribution +system.membus.trans_dist::UpgradeResp 22 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 147056 # Transaction distribution +system.membus.trans_dist::ReadExResp 129063 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 756086 # Transaction distribution +system.membus.trans_dist::InvalidateReq 664574 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122674 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24516 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4262617 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4409841 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238367 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238367 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4648208 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155723 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26434 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4433526 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4582726 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237876 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237876 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4820602 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155781 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 119974316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 120179275 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7283904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7283904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 127463179 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 565217 # Total snoops (count) -system.membus.snoop_fanout::samples 3689099 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52868 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124620204 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 124829057 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7253952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 132083009 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 605187 # Total snoops (count) +system.membus.snoop_fanout::samples 2426230 # Request fanout histogram +system.membus.snoop_fanout::mean 0.013777 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.116566 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3689099 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2392803 98.62% 98.62% # Request fanout histogram +system.membus.snoop_fanout::1 33427 1.38% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3689099 # Request fanout histogram -system.membus.reqLayer0.occupancy 101296000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2426230 # Request fanout histogram +system.membus.reqLayer0.occupancy 101268497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20132498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21861496 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7983633356 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8209418227 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4606610325 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4835085635 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45425919 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45398182 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3200,53 +3224,53 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 10607741 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5778542 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1706398 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 126357 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 115095 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 11262 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 81396 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3972795 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38017 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38017 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3722299 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2264546 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 665609 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 384259 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1049868 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 134 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 134 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 281631 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 281631 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3898638 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 910400 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 803672 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8440853 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7105433 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15546286 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 205041299 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 177324920 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 382366219 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2848440 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7664337 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.347835 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.479358 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 10840157 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5896724 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1754214 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 132701 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 121224 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 11477 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 81887 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4082535 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38514 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38514 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3675345 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2314292 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 683405 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 409707 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1093112 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 115 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 292338 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 292338 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4001459 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 832376 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 802179 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8623692 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7234411 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15858103 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 210145531 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 178915910 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 389061441 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2781791 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7676067 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.360389 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.483218 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5009678 65.36% 65.36% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2643397 34.49% 99.85% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 11262 0.15% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4921172 64.11% 64.11% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2743418 35.74% 99.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 11477 0.15% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7664337 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8363064932 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7676067 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8520913919 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2585436 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2554437 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3816515270 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3920667694 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3482933794 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3580148330 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index 9849a9aeb..cc4952e71 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.759374 # Nu sim_ticks 51759374264500 # Number of ticks simulated final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 729832 # Simulator instruction rate (inst/s) -host_op_rate 857659 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45135767006 # Simulator tick rate (ticks/s) -host_mem_usage 675484 # Number of bytes of host memory used -host_seconds 1146.75 # Real time elapsed on the host +host_inst_rate 790659 # Simulator instruction rate (inst/s) +host_op_rate 929140 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48897567060 # Simulator tick rate (ticks/s) +host_mem_usage 670860 # Number of bytes of host memory used +host_seconds 1058.53 # Real time elapsed on the host sim_insts 836933434 # Number of instructions simulated sim_ops 983519389 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index a460c7e41..485528e29 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -1,74 +1,74 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.111167 # Number of seconds simulated -sim_ticks 51111167216500 # Number of ticks simulated -final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.111166 # Number of seconds simulated +sim_ticks 51111166190000 # Number of ticks simulated +final_tick 51111166190000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1129745 # Simulator instruction rate (inst/s) -host_op_rate 1327694 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58788800163 # Simulator tick rate (ticks/s) -host_mem_usage 676512 # Number of bytes of host memory used -host_seconds 869.40 # Real time elapsed on the host -sim_insts 982203438 # Number of instructions simulated -sim_ops 1154301153 # Number of ops (including micro ops) simulated +host_inst_rate 1183514 # Simulator instruction rate (inst/s) +host_op_rate 1390863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61528862033 # Simulator tick rate (ticks/s) +host_mem_usage 673932 # Number of bytes of host memory used +host_seconds 830.69 # Real time elapsed on the host +sim_insts 983128290 # Number of instructions simulated +sim_ops 1155370468 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 206336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 188160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3278004 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 38030280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 207616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 185216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2205952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 36881856 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory -system.physmem.bytes_read::total 81620220 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3278004 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2205952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5483956 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103277568 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 206080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 186880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3298228 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 38035976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 206656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 186304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2187520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 36841280 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 435200 # Number of bytes read from this memory +system.physmem.bytes_read::total 81584124 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3298228 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2187520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5485748 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103274624 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103298148 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3224 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2940 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 91626 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 594236 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3244 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2894 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 34468 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 576279 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315736 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613712 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 103295204 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2920 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 91942 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 594325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3229 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2911 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 34180 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 575645 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6800 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1315172 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1613666 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616285 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 4037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 64135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 744070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4062 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 43160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 721601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1596916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 64135 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 43160 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107295 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020646 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1616239 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 4032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 64530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 744181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4043 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 42799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 720807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1596209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 64530 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 42799 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107330 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2020588 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2021049 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 64135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 744473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 43160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 721601 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3617964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2020991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2020588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 64530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 744584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 42799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 720807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3617200 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -121,45 +121,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 145509 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 145509 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 145509 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 145509 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 145509 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 145178 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 145178 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 145178 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 145178 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 145178 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 108299 85.66% 85.66% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 18127 14.34% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 126426 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 145509 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 108127 85.58% 85.58% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 18215 14.42% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 126342 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 145178 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 145509 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126426 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 145178 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126342 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126426 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 271935 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126342 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 271520 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91814095 # DTB read hits -system.cpu0.dtb.read_misses 108271 # DTB read misses -system.cpu0.dtb.write_hits 84019310 # DTB write hits -system.cpu0.dtb.write_misses 37238 # DTB write misses +system.cpu0.dtb.read_hits 91916513 # DTB read hits +system.cpu0.dtb.read_misses 107962 # DTB read misses +system.cpu0.dtb.write_hits 84123596 # DTB write hits +system.cpu0.dtb.write_misses 37216 # DTB write misses system.cpu0.dtb.flush_tlb 51122 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 25423 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 574 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 56716 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 25185 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 570 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 56806 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4781 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4849 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 10952 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 91922366 # DTB read accesses -system.cpu0.dtb.write_accesses 84056548 # DTB write accesses +system.cpu0.dtb.read_accesses 92024475 # DTB read accesses +system.cpu0.dtb.write_accesses 84160812 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 175833405 # DTB hits -system.cpu0.dtb.misses 145509 # DTB misses -system.cpu0.dtb.accesses 175978914 # DTB accesses +system.cpu0.dtb.hits 176040109 # DTB hits +system.cpu0.dtb.misses 145178 # DTB misses +system.cpu0.dtb.accesses 176185287 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -189,289 +189,289 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 70811 # Table walker walks requested -system.cpu0.itb.walker.walksLong 70811 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 70811 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 70811 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 70811 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 70488 # Table walker walks requested +system.cpu0.itb.walker.walksLong 70488 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 70488 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 70488 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 70488 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 62036 96.03% 96.03% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2564 3.97% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 64600 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 61740 96.00% 96.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2570 4.00% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 64310 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70811 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70811 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70488 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70488 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64600 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64600 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 135411 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 492376819 # ITB inst hits -system.cpu0.itb.inst_misses 70811 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64310 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64310 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 134798 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 493160707 # ITB inst hits +system.cpu0.itb.inst_misses 70488 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 51122 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 25423 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 574 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40510 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 25185 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 570 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 40500 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 492447630 # ITB inst accesses -system.cpu0.itb.hits 492376819 # DTB hits -system.cpu0.itb.misses 70811 # DTB misses -system.cpu0.itb.accesses 492447630 # DTB accesses -system.cpu0.numCycles 98037037144 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 493231195 # ITB inst accesses +system.cpu0.itb.hits 493160707 # DTB hits +system.cpu0.itb.misses 70488 # DTB misses +system.cpu0.itb.accesses 493231195 # DTB accesses +system.cpu0.numCycles 98036837820 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu0.committedInsts 492158167 # Number of instructions committed -system.cpu0.committedOps 578111598 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 529632754 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 450817 # Number of float alu accesses -system.cpu0.num_func_calls 28493916 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 76040779 # number of instructions that are conditional controls -system.cpu0.num_int_insts 529632754 # number of integer instructions -system.cpu0.num_fp_insts 450817 # number of float instructions -system.cpu0.num_int_register_reads 782886511 # number of times the integer registers were read -system.cpu0.num_int_register_writes 420745648 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 732502 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 369640 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 132702438 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 132380757 # number of times the CC registers were written -system.cpu0.num_mem_refs 175957130 # number of memory refs -system.cpu0.num_load_insts 91908746 # Number of load instructions -system.cpu0.num_store_insts 84048384 # Number of store instructions -system.cpu0.num_idle_cycles 96929538971.519501 # Number of idle cycles -system.cpu0.num_busy_cycles 1107498172.480497 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011297 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988703 # Percentage of idle cycles -system.cpu0.Branches 110098677 # Number of branches fetched +system.cpu0.committedInsts 492942676 # Number of instructions committed +system.cpu0.committedOps 578945163 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 530362809 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 453024 # Number of float alu accesses +system.cpu0.num_func_calls 28530371 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 76157318 # number of instructions that are conditional controls +system.cpu0.num_int_insts 530362809 # number of integer instructions +system.cpu0.num_fp_insts 453024 # number of float instructions +system.cpu0.num_int_register_reads 784322084 # number of times the integer registers were read +system.cpu0.num_int_register_writes 421327896 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 740492 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 361708 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 133053105 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 132724899 # number of times the CC registers were written +system.cpu0.num_mem_refs 176163553 # number of memory refs +system.cpu0.num_load_insts 92011132 # Number of load instructions +system.cpu0.num_store_insts 84152421 # Number of store instructions +system.cpu0.num_idle_cycles 96928545322.027405 # Number of idle cycles +system.cpu0.num_busy_cycles 1108292497.972592 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011305 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988695 # Percentage of idle cycles +system.cpu0.Branches 110262676 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 401203105 69.36% 69.36% # Class of executed instruction -system.cpu0.op_class::IntMult 1174268 0.20% 69.56% # Class of executed instruction -system.cpu0.op_class::IntDiv 49936 0.01% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 53536 0.01% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::MemRead 91908746 15.89% 85.47% # Class of executed instruction -system.cpu0.op_class::MemWrite 84048384 14.53% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 401826971 69.37% 69.37% # Class of executed instruction +system.cpu0.op_class::IntMult 1176436 0.20% 69.57% # Class of executed instruction +system.cpu0.op_class::IntDiv 51169 0.01% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 52500 0.01% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::MemRead 92011132 15.88% 85.47% # Class of executed instruction +system.cpu0.op_class::MemWrite 84152421 14.53% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 578437975 # Class of executed instruction -system.cpu0.dcache.tags.replacements 11606642 # number of replacements +system.cpu0.op_class::total 579270629 # Class of executed instruction +system.cpu0.dcache.tags.replacements 11609443 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 339855015 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 11607154 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 29.279789 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 340216355 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 11609955 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 29.303848 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 263.642285 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 248.357434 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.514926 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.485073 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 262.381327 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 249.618393 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.512464 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.487536 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1417455895 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1417455895 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 85600779 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 85509781 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 171110560 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 79545514 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 79528016 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 159073530 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209330 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 214983 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 424313 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 144241 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 192044 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 336285 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2149130 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2154418 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 4303548 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2275074 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2280572 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165290534 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 165229841 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 330520375 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 165499864 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 165444824 # number of overall hits -system.cpu0.dcache.overall_hits::total 330944688 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3016518 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2987065 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6003583 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1295456 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1272689 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2568145 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 788237 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 797661 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1585898 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 761490 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 485280 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1246770 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 126843 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 127060 # 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number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 911023 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 672036 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1583059 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2266223 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2293879 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 4560102 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2265304 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2292997 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 4558301 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 170586146 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 170112337 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 340698483 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 171586753 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 171121163 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 342707916 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.034067 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033683 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033875 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016059 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015694 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015877 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.790456 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.787546 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788995 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.840434 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.715084 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.787221 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055303 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056264 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055786 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000000 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # 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miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 8917390 # number of writebacks -system.cpu0.dcache.writebacks::total 8917390 # number of writebacks -system.cpu0.icache.tags.replacements 14265253 # number of replacements +system.cpu0.dcache.writebacks::writebacks 8920157 # number of writebacks +system.cpu0.dcache.writebacks::total 8920157 # number of writebacks +system.cpu0.icache.tags.replacements 14275419 # number of replacements system.cpu0.icache.tags.tagsinuse 511.984599 # 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Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 268.598488 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 243.386111 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.524606 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.475363 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 997060750 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 997060750 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 485302740 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 483226470 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 968529210 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 485302740 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 483226470 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 968529210 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 485302740 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 483226470 # number of overall hits -system.cpu0.icache.overall_hits::total 968529210 # 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number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 492441419 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 490353561 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 982794980 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 492441419 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 490353561 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 982794980 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014497 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014535 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014497 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014535 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014497 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014535 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 997995764 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 997995764 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 486058611 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 483385281 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 969443892 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 486058611 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 483385281 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 969443892 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 486058611 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 483385281 # number of overall hits +system.cpu0.icache.overall_hits::total 969443892 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 7166406 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 7109530 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 14275936 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 7166406 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 7109530 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 14275936 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 7166406 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 7109530 # number of overall misses +system.cpu0.icache.overall_misses::total 14275936 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 493225017 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 490494811 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 983719828 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 493225017 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 490494811 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 983719828 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 493225017 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 490494811 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 983719828 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014530 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014495 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014512 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014530 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014495 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014512 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014530 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014495 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014512 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 14265253 # number of writebacks -system.cpu0.icache.writebacks::total 14265253 # number of writebacks +system.cpu0.icache.writebacks::writebacks 14275419 # number of writebacks +system.cpu0.icache.writebacks::total 14275419 # number of writebacks system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -501,45 +501,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 143142 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 143142 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 143142 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 143142 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 143142 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 143940 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 143940 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 143940 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 143940 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 143940 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples 1000001000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000001000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000001000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 106698 85.48% 85.48% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 18131 14.52% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 124829 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143142 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 107031 85.37% 85.37% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 18349 14.63% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 125380 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143940 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143142 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124829 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143940 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125380 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124829 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 267971 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125380 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 269320 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 91711522 # DTB read hits -system.cpu1.dtb.read_misses 106128 # DTB read misses -system.cpu1.dtb.write_hits 83752453 # DTB write hits -system.cpu1.dtb.write_misses 37014 # DTB write misses +system.cpu1.dtb.read_hits 91791346 # DTB read hits +system.cpu1.dtb.read_misses 106897 # DTB read misses +system.cpu1.dtb.write_hits 83829592 # DTB write hits +system.cpu1.dtb.write_misses 37043 # DTB write misses system.cpu1.dtb.flush_tlb 51111 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 24348 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 565 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 56325 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 24586 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 569 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 56691 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4754 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4731 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 10699 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91817650 # DTB read accesses -system.cpu1.dtb.write_accesses 83789467 # DTB write accesses +system.cpu1.dtb.read_accesses 91898243 # DTB read accesses +system.cpu1.dtb.write_accesses 83866635 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 175463975 # DTB hits -system.cpu1.dtb.misses 143142 # DTB misses -system.cpu1.dtb.accesses 175607117 # DTB accesses +system.cpu1.dtb.hits 175620938 # DTB hits +system.cpu1.dtb.misses 143940 # DTB misses +system.cpu1.dtb.accesses 175764878 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -569,109 +569,109 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 69345 # Table walker walks requested -system.cpu1.itb.walker.walksLong 69345 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 69345 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 69345 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 69345 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 69853 # Table walker walks requested +system.cpu1.itb.walker.walksLong 69853 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 69853 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 69853 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69853 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 60894 96.02% 96.02% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 2524 3.98% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 63418 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 61351 96.02% 96.02% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2542 3.98% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 63893 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69345 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69345 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69853 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69853 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63418 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63418 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 132763 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 490290143 # ITB inst hits -system.cpu1.itb.inst_misses 69345 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63893 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63893 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 133746 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 490430918 # ITB inst hits +system.cpu1.itb.inst_misses 69853 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 51111 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 24348 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 565 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40528 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 24586 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 569 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 41078 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 490359488 # ITB inst accesses -system.cpu1.itb.hits 490290143 # DTB hits -system.cpu1.itb.misses 69345 # DTB misses -system.cpu1.itb.accesses 490359488 # DTB accesses -system.cpu1.numCycles 97462077146 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 490500771 # ITB inst accesses +system.cpu1.itb.hits 490430918 # DTB hits +system.cpu1.itb.misses 69853 # DTB misses +system.cpu1.itb.accesses 490500771 # DTB accesses +system.cpu1.numCycles 97462088232 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 490045271 # Number of instructions committed -system.cpu1.committedOps 576189555 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 528249503 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 430532 # Number of float alu accesses -system.cpu1.num_func_calls 28340665 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 75582970 # number of instructions that are conditional controls -system.cpu1.num_int_insts 528249503 # number of integer instructions -system.cpu1.num_fp_insts 430532 # number of float instructions -system.cpu1.num_int_register_reads 777873169 # number of times the integer registers were read -system.cpu1.num_int_register_writes 419771432 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 687265 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 378920 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 131316168 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 131060074 # number of times the CC registers were written -system.cpu1.num_mem_refs 175582205 # number of memory refs -system.cpu1.num_load_insts 91803684 # Number of load instructions -system.cpu1.num_store_insts 83778521 # Number of store instructions -system.cpu1.num_idle_cycles 96357522330.236954 # Number of idle cycles -system.cpu1.num_busy_cycles 1104554815.763041 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011333 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988667 # Percentage of idle cycles -system.cpu1.Branches 109435377 # Number of branches fetched +system.cpu1.committedInsts 490185614 # Number of instructions committed +system.cpu1.committedOps 576425305 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 528528005 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 428357 # Number of float alu accesses +system.cpu1.num_func_calls 28391089 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 75589435 # number of instructions that are conditional controls +system.cpu1.num_int_insts 528528005 # number of integer instructions +system.cpu1.num_fp_insts 428357 # number of float instructions +system.cpu1.num_int_register_reads 777707533 # number of times the integer registers were read +system.cpu1.num_int_register_writes 419943205 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 679275 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 386980 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 131115369 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 130866277 # number of times the CC registers were written +system.cpu1.num_mem_refs 175739961 # number of memory refs +system.cpu1.num_load_insts 91884045 # Number of load instructions +system.cpu1.num_store_insts 83855916 # Number of store instructions +system.cpu1.num_idle_cycles 96357307601.045395 # Number of idle cycles +system.cpu1.num_busy_cycles 1104780630.954602 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011335 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988665 # Percentage of idle cycles +system.cpu1.Branches 109487364 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 399630588 69.32% 69.32% # Class of executed instruction -system.cpu1.op_class::IntMult 1180116 0.20% 69.53% # Class of executed instruction -system.cpu1.op_class::IntDiv 50607 0.01% 69.53% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 54286 0.01% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::MemRead 91803684 15.92% 85.47% # Class of executed instruction -system.cpu1.op_class::MemWrite 83778521 14.53% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 399711275 69.31% 69.31% # Class of executed instruction +system.cpu1.op_class::IntMult 1178043 0.20% 69.51% # Class of executed instruction +system.cpu1.op_class::IntDiv 49858 0.01% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 55322 0.01% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::MemRead 91884045 15.93% 85.46% # Class of executed instruction +system.cpu1.op_class::MemWrite 83855916 14.54% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 576497845 # Class of executed instruction -system.iobus.trans_dist::ReadReq 40242 # Transaction distribution -system.iobus.trans_dist::ReadResp 40242 # Transaction distribution +system.cpu1.op_class::total 576734502 # Class of executed instruction +system.iobus.trans_dist::ReadReq 40249 # Transaction distribution +system.iobus.trans_dist::ReadResp 40249 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution system.iobus.trans_dist::WriteResp 136515 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) @@ -688,11 +688,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230968 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353514 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353528 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -707,53 +707,53 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334304 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.replacements 115459 # number of replacements +system.iobus.pkt_size::total 7492000 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115466 # number of replacements system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115482 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13082113303009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.852512 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039650 # Number of tag accesses -system.iocache.tags.data_accesses 1039650 # Number of data accesses +system.iocache.tags.tag_accesses 1039713 # Number of tag accesses +system.iocache.tags.data_accesses 1039713 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115477 # number of demand (read+write) misses -system.iocache.demand_misses::total 115517 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115484 # number of demand (read+write) misses +system.iocache.demand_misses::total 115524 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115477 # number of overall misses -system.iocache.overall_misses::total 115517 # number of overall misses +system.iocache.overall_misses::realview.ide 115484 # number of overall misses +system.iocache.overall_misses::total 115524 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8820 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8857 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115477 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115517 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115484 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115524 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115477 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115517 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115484 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115524 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -775,259 +775,265 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.l2c.tags.replacements 1725796 # number of replacements -system.l2c.tags.tagsinuse 65319.576265 # Cycle average of tags in use -system.l2c.tags.total_refs 46978291 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1788815 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 26.262241 # Average number of references to valid blocks. +system.l2c.tags.replacements 1725552 # number of replacements +system.l2c.tags.tagsinuse 65318.589868 # Cycle average of tags in use +system.l2c.tags.total_refs 46997821 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1788325 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 26.280358 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37199.693838 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 157.541812 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 243.130433 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3426.948929 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9570.300685 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 153.000068 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 205.689904 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2648.963417 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11714.307180 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.567622 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002404 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003710 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.052291 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.146031 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002335 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003139 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.040420 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.178746 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 318 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62701 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 318 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54255 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004852 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.956741 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 426283079 # Number of tag accesses -system.l2c.tags.data_accesses 426283079 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 280721 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 145865 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 277388 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 142208 # number of ReadReq hits -system.l2c.ReadReq_hits::total 846182 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 8917390 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 8917390 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 14263676 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 14263676 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 5749 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5456 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 11205 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 852276 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 837137 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1689413 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 7090154 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 7092610 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 14182764 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 3754052 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 3745235 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 7499287 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 340224 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 354322 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 694546 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 280721 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 145865 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7090154 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4606328 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 277388 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 142208 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7092610 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4582372 # number of demand (read+write) hits -system.l2c.demand_hits::total 24217646 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 280721 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 145865 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7090154 # number of overall hits -system.l2c.overall_hits::cpu0.data 4606328 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 277388 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 142208 # number of overall hits -system.l2c.overall_hits::cpu1.inst 7092610 # number of overall hits -system.l2c.overall_hits::cpu1.data 4582372 # number of overall hits -system.l2c.overall_hits::total 24217646 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3224 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2940 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3244 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2894 # number of ReadReq misses -system.l2c.ReadReq_misses::total 12302 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 20285 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 19642 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 39927 # number of UpgradeReq misses +system.l2c.tags.occ_blocks::writebacks 37152.914726 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 156.952834 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 243.226181 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3473.573916 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9619.511696 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 153.800333 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 210.267974 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2624.848804 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11683.493403 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.566908 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002395 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003711 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.053003 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.146782 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002347 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003208 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040052 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.178276 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996683 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 268 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62505 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 268 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 604 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2729 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4885 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54176 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.953751 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 426507397 # Number of tag accesses +system.l2c.tags.data_accesses 426507397 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 281107 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 145752 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 278085 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 143361 # number of ReadReq hits +system.l2c.ReadReq_hits::total 848305 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 8920157 # 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miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.269861 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.442924 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011354 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.019757 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.006797 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.114341 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011560 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.019945 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004838 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.111836 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.049716 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011354 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.019757 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.006797 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.114341 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011560 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.019945 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004838 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.111836 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.049716 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.327133 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.329959 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.328529 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006815 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004809 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.005816 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045173 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042484 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.043834 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.551670 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.270795 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.443360 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011325 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.019641 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.006815 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.114092 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011478 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.019901 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004809 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.111904 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.049665 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011325 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.019641 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.006815 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.114092 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011478 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.019901 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004809 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.111904 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.049665 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1507081 # number of writebacks -system.l2c.writebacks::total 1507081 # number of writebacks +system.l2c.writebacks::writebacks 1507035 # number of writebacks +system.l2c.writebacks::total 1507035 # number of writebacks +system.membus.snoop_filter.tot_requests 3814231 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1911351 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2893 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 524934 # Transaction distribution +system.membus.trans_dist::ReadResp 524759 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1613712 # Transaction distribution -system.membus.trans_dist::CleanEvict 226309 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40494 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1613666 # Transaction distribution +system.membus.trans_dist::CleanEvict 226120 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40498 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40495 # Transaction distribution -system.membus.trans_dist::ReadExReq 827043 # Transaction distribution -system.membus.trans_dist::ReadExResp 827043 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 448255 # Transaction distribution -system.membus.trans_dist::InvalidateReq 658881 # Transaction distribution -system.membus.trans_dist::InvalidateResp 658881 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40499 # Transaction distribution +system.membus.trans_dist::ReadExReq 826686 # Transaction distribution +system.membus.trans_dist::ReadExResp 826686 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 448080 # Transaction distribution +system.membus.trans_dist::InvalidateReq 659180 # Transaction distribution +system.membus.trans_dist::InvalidateResp 659180 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5534254 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5663446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6009939 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5533540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5662732 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346514 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346514 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6009246 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 177698976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 177868026 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 185258810 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 177661536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 177830586 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7391232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 185221818 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3924980 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 3924516 # Request fanout histogram +system.membus.snoop_fanout::mean 0.009389 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.096443 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3924980 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3887667 99.06% 99.06% # Request fanout histogram +system.membus.snoop_fanout::1 36849 0.94% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3924980 # Request fanout histogram +system.membus.snoop_fanout::total 3924516 # Request fanout histogram system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks @@ -1080,49 +1086,49 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 52405672 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 26532742 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 52432480 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 26546586 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1741 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2697 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2697 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 1320342 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23429496 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 1321968 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23443629 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 8917390 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 14265253 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2689252 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 51132 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 8920157 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 14275419 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2689286 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 51144 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51133 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2517013 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2517013 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 14265770 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7843384 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1246770 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1246770 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 42883043 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35057562 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 830208 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1657118 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 80427931 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1826157972 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1233968038 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3320832 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6628472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3070075314 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1957567 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 55106685 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.011176 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105126 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 51145 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2518022 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2518022 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 14275936 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7845725 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1246217 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1246217 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 42913541 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35065981 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 831270 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1659308 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 80470100 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1827459220 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1234359526 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3325080 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6637232 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3071781058 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1762525 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 54939201 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.011226 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105357 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 54490790 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 615895 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 54322443 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 616758 1.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 55106685 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 54939201 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index 1b1aa2e1b..d8c58ee0c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,194 +1,194 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.278333 # Number of seconds simulated -sim_ticks 51278333141000 # Number of ticks simulated -final_tick 51278333141000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.316243 # Number of seconds simulated +sim_ticks 51316242679000 # Number of ticks simulated +final_tick 51316242679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 300545 # Simulator instruction rate (inst/s) -host_op_rate 353177 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18121485754 # Simulator tick rate (ticks/s) -host_mem_usage 688280 # Number of bytes of host memory used -host_seconds 2829.70 # Real time elapsed on the host -sim_insts 850450745 # Number of instructions simulated -sim_ops 999383448 # Number of ops (including micro ops) simulated +host_inst_rate 361668 # Simulator instruction rate (inst/s) +host_op_rate 424976 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21619129427 # Simulator tick rate (ticks/s) +host_mem_usage 686216 # Number of bytes of host memory used +host_seconds 2373.65 # Real time elapsed on the host +sim_insts 858473131 # Number of instructions simulated +sim_ops 1008744567 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 82048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 86080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2553908 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 18749896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 26560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 25408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 451200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4994624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 34432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 29952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 1461952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 6681856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 70784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.itb.walker 53120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 1684864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 11657408 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 398592 # Number of bytes read from this memory -system.physmem.bytes_read::total 49042684 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2553908 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 451200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 1461952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 1684864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6151924 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 68500992 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 84032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 93120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2529588 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19493128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 22656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 23808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 606400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5209600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 35264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 30848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 1545600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 6997952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 75392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.itb.walker 63744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 1527168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 11329792 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 446016 # Number of bytes read from this memory +system.physmem.bytes_read::total 50114108 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2529588 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 606400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 1545600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 1527168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6208756 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69736384 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 68521572 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1282 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1345 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 80312 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 292980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 415 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 397 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 78041 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 538 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 468 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 22843 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 104404 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 1106 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.itb.walker 830 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 26326 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 182147 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6228 # Number of read requests responded to by this memory -system.physmem.num_reads::total 806712 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1070328 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69756964 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1313 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1455 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 79932 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 304593 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 354 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 372 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9475 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81400 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 551 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 482 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 24150 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 109343 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 1178 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.itb.walker 996 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 23862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 177028 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6969 # Number of read requests responded to by this memory +system.physmem.num_reads::total 823453 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1089631 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1072901 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 49805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 365649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 8799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 97402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 28510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 130306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.itb.walker 1036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 32857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 227336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 956402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 49805 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 8799 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 28510 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 32857 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 119971 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1335866 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1092204 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 49294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 379863 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 11817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 101520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 30119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 136369 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.itb.walker 1242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 29760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 220784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 976574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 49294 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 11817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 30119 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 29760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 120990 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1358953 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1336268 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1335866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 49805 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 366051 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 8799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 97402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 28510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 130306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.itb.walker 1036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 32857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 227336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2292669 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 428538 # Number of read requests accepted -system.physmem.writeReqs 456847 # Number of write requests accepted -system.physmem.readBursts 428538 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 456847 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 27408320 # Total number of bytes read from DRAM +system.physmem.bw_write::total 1359354 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1358953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 49294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 380264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 11817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 101520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 30119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 136369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.itb.walker 1242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 29760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 220784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2335928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 433905 # Number of read requests accepted +system.physmem.writeReqs 477158 # Number of write requests accepted +system.physmem.readBursts 433905 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 477158 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27751808 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 18112 # Total number of bytes read from write queue -system.physmem.bytesWritten 29236416 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27426432 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 29238208 # Total written bytes from the system interface side +system.physmem.bytesWritten 30536384 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27769920 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 30538112 # Total written bytes from the system interface side system.physmem.servicedByWrQ 283 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26649 # Per bank write bursts -system.physmem.perBankRdBursts::1 30049 # Per bank write bursts -system.physmem.perBankRdBursts::2 26532 # Per bank write bursts -system.physmem.perBankRdBursts::3 25500 # Per bank write bursts -system.physmem.perBankRdBursts::4 26079 # Per bank write bursts -system.physmem.perBankRdBursts::5 32966 # Per bank write bursts -system.physmem.perBankRdBursts::6 25199 # Per bank write bursts -system.physmem.perBankRdBursts::7 25237 # Per bank write bursts -system.physmem.perBankRdBursts::8 24838 # Per bank write bursts -system.physmem.perBankRdBursts::9 28373 # Per bank write bursts -system.physmem.perBankRdBursts::10 26870 # Per bank write bursts -system.physmem.perBankRdBursts::11 27983 # Per bank write bursts -system.physmem.perBankRdBursts::12 26309 # Per bank write bursts -system.physmem.perBankRdBursts::13 25787 # Per bank write bursts -system.physmem.perBankRdBursts::14 24479 # Per bank write bursts -system.physmem.perBankRdBursts::15 25405 # Per bank write bursts -system.physmem.perBankWrBursts::0 27847 # Per bank write bursts -system.physmem.perBankWrBursts::1 29934 # Per bank write bursts -system.physmem.perBankWrBursts::2 27360 # Per bank write bursts -system.physmem.perBankWrBursts::3 28363 # Per bank write bursts -system.physmem.perBankWrBursts::4 28817 # Per bank write bursts -system.physmem.perBankWrBursts::5 32577 # Per bank write bursts -system.physmem.perBankWrBursts::6 27869 # Per bank write bursts -system.physmem.perBankWrBursts::7 28879 # Per bank write bursts -system.physmem.perBankWrBursts::8 27745 # Per bank write bursts -system.physmem.perBankWrBursts::9 30902 # Per bank write bursts -system.physmem.perBankWrBursts::10 28100 # Per bank write bursts -system.physmem.perBankWrBursts::11 29746 # Per bank write bursts -system.physmem.perBankWrBursts::12 27536 # Per bank write bursts -system.physmem.perBankWrBursts::13 27471 # Per bank write bursts -system.physmem.perBankWrBursts::14 26272 # Per bank write bursts -system.physmem.perBankWrBursts::15 27401 # Per bank write bursts +system.physmem.perBankRdBursts::0 27002 # Per bank write bursts +system.physmem.perBankRdBursts::1 28908 # Per bank write bursts +system.physmem.perBankRdBursts::2 27684 # Per bank write bursts +system.physmem.perBankRdBursts::3 26367 # Per bank write bursts +system.physmem.perBankRdBursts::4 27601 # Per bank write bursts +system.physmem.perBankRdBursts::5 30822 # Per bank write bursts +system.physmem.perBankRdBursts::6 24976 # Per bank write bursts +system.physmem.perBankRdBursts::7 26194 # Per bank write bursts +system.physmem.perBankRdBursts::8 25034 # Per bank write bursts +system.physmem.perBankRdBursts::9 29693 # Per bank write bursts +system.physmem.perBankRdBursts::10 29082 # Per bank write bursts +system.physmem.perBankRdBursts::11 28850 # Per bank write bursts +system.physmem.perBankRdBursts::12 25459 # Per bank write bursts +system.physmem.perBankRdBursts::13 26397 # Per bank write bursts +system.physmem.perBankRdBursts::14 23675 # Per bank write bursts +system.physmem.perBankRdBursts::15 25878 # Per bank write bursts +system.physmem.perBankWrBursts::0 28116 # Per bank write bursts +system.physmem.perBankWrBursts::1 30181 # Per bank write bursts +system.physmem.perBankWrBursts::2 29513 # Per bank write bursts +system.physmem.perBankWrBursts::3 29673 # Per bank write bursts +system.physmem.perBankWrBursts::4 30639 # Per bank write bursts +system.physmem.perBankWrBursts::5 33377 # Per bank write bursts +system.physmem.perBankWrBursts::6 28958 # Per bank write bursts +system.physmem.perBankWrBursts::7 30258 # Per bank write bursts +system.physmem.perBankWrBursts::8 28970 # Per bank write bursts +system.physmem.perBankWrBursts::9 32487 # Per bank write bursts +system.physmem.perBankWrBursts::10 30224 # Per bank write bursts +system.physmem.perBankWrBursts::11 30351 # Per bank write bursts +system.physmem.perBankWrBursts::12 28039 # Per bank write bursts +system.physmem.perBankWrBursts::13 29604 # Per bank write bursts +system.physmem.perBankWrBursts::14 27578 # Per bank write bursts +system.physmem.perBankWrBursts::15 29163 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 20 # Number of times write queue was full causing retry -system.physmem.totGap 51277332920000 # Total gap between requests +system.physmem.numWrRetry 15 # Number of times write queue was full causing retry +system.physmem.totGap 51315242398500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 428538 # Read request sizes (log2) +system.physmem.readPktSize::6 433905 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 456847 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 325583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20024 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 316 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 477158 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 336122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 409 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1036 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -198,219 +198,205 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 10375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12229 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 29858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 26497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 26161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 25503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 60 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 267354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 211.869985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.094359 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 252.014491 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 129551 48.46% 48.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 69661 26.06% 74.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 23971 8.97% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11874 4.44% 87.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 7889 2.95% 90.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4786 1.79% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3806 1.42% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2811 1.05% 95.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 13005 4.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 267354 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 24743 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.307279 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 12.628838 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-31 23085 93.30% 93.30% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32-63 1534 6.20% 99.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-95 94 0.38% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::96-127 12 0.05% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-159 6 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::160-191 2 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::192-223 2 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::224-255 1 0.00% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-287 2 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::288-319 1 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::320-351 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-415 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-543 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::640-671 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 24743 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 24743 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.462555 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.679981 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.466510 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 17 0.07% 0.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 18 0.07% 0.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 7 0.03% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 50 0.20% 0.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 22406 90.55% 90.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1021 4.13% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 245 0.99% 96.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 205 0.83% 96.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 59 0.24% 97.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 45 0.18% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 91 0.37% 97.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 19 0.08% 97.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 158 0.64% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 47 0.19% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 11 0.04% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 29 0.12% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 119 0.48% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 17 0.07% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 15 0.06% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 48 0.19% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 83 0.34% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 4 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 24743 # Writes before turning the bus around for reads -system.physmem.totQLat 8299247161 # Total ticks spent queuing -system.physmem.totMemAccLat 16329028411 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2141275000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19379.22 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 10672 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 28851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 29534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 26977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 26434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 25831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 226 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 48 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 269447 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 216.323596 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 135.007957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.795343 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 129144 47.93% 47.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 70137 26.03% 73.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 24147 8.96% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12093 4.49% 87.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8137 3.02% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4947 1.84% 92.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4006 1.49% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2935 1.09% 94.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 13901 5.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 269447 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 25551 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.968847 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 13.943536 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-31 23836 93.29% 93.29% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-63 1606 6.29% 99.57% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-95 93 0.36% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-127 3 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-159 4 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::192-223 1 0.00% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-287 1 0.00% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::352-383 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-415 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::416-447 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::448-479 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::704-735 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::928-959 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 25551 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 25551 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.673672 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.805610 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.967409 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 31 0.12% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 43 0.17% 0.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 23775 93.05% 93.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 652 2.55% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 518 2.03% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 117 0.46% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 66 0.26% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 48 0.19% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 173 0.68% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 30 0.12% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 11 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 7 0.03% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 14 0.05% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 8 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 9 0.04% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 10 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 4 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 6 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 4 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 3 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-359 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 25551 # Writes before turning the bus around for reads +system.physmem.totQLat 8250184127 # Total ticks spent queuing +system.physmem.totMemAccLat 16380596627 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2168110000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19026.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38129.22 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.53 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.53 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.57 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37776.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.54 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 5.79 # Average write queue length when enqueuing -system.physmem.readRowHits 313353 # Number of row buffer hits during reads -system.physmem.writeRowHits 304365 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.62 # Row buffer hit rate for writes -system.physmem.avgGap 57915294.39 # Average gap between requests -system.physmem.pageHitRate 69.79 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1033164720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 562076625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1701999000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1501066080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3310356385440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1179927426690 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30447593029500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34942675148055 # Total energy per rank (pJ) -system.physmem_0.averagePower 665.942257 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48866965519857 # Time in different power states -system.physmem_0.memoryStateTime::REF 1692411240000 # Time in different power states +system.physmem.avgWrQLen 7.94 # Average write queue length when enqueuing +system.physmem.readRowHits 319229 # Number of row buffer hits during reads +system.physmem.writeRowHits 322075 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.50 # Row buffer hit rate for writes +system.physmem.avgGap 56324581.72 # Average gap between requests +system.physmem.pageHitRate 70.41 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1046092320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 569142750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1712513400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1559833200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3312965298240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1175245195320 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29690777078250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34183875153480 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.616999 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48913778839190 # Time in different power states +system.physmem_0.memoryStateTime::REF 1693745040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 123966214393 # Time in different power states +system.physmem_0.memoryStateTime::ACT 115773933810 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 988031520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 537520500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1638335400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1459121040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3310356385440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1177251222825 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29686423716000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34178654332725 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.571395 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 48870902891583 # Time in different power states -system.physmem_1.memoryStateTime::REF 1692411240000 # Time in different power states +system.physmem_1.actEnergy 990927000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 539141625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1669683600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1531975680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3312965298240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1172482833105 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29689600432500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34179780291750 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.615252 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48917806002648 # Time in different power states +system.physmem_1.memoryStateTime::REF 1693745040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 120022768167 # Time in different power states +system.physmem_1.memoryStateTime::ACT 111730336352 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu2.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 196 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu2.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu2.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu2.inst 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu2.inst 1 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu2.inst 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -447,47 +433,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 90231 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 90231 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 90231 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 90231 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 90231 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 388941119992 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.527073 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -205000507008 -52.71% -52.71% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 593941627000 152.71% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 388941119992 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 65649 84.67% 84.67% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11889 15.33% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 77538 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90231 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 91119 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 91119 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 91119 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 91119 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 91119 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 392500671624 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.508107 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -199432260126 -50.81% -50.81% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 591932931750 150.81% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 392500671624 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 66569 84.97% 84.97% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11779 15.03% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 78348 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 91119 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90231 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77538 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 91119 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78348 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77538 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 167769 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78348 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 169467 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 64940650 # DTB read hits -system.cpu0.dtb.read_misses 68234 # DTB read misses -system.cpu0.dtb.write_hits 59349095 # DTB write hits -system.cpu0.dtb.write_misses 21997 # DTB write misses -system.cpu0.dtb.flush_tlb 1197 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 64520896 # DTB read hits +system.cpu0.dtb.read_misses 69076 # DTB read misses +system.cpu0.dtb.write_hits 58341415 # DTB write hits +system.cpu0.dtb.write_misses 22043 # DTB write misses +system.cpu0.dtb.flush_tlb 1192 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 16324 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 389 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 40980 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 16238 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 399 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 41149 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2794 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 2806 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 7599 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 65008884 # DTB read accesses -system.cpu0.dtb.write_accesses 59371092 # DTB write accesses +system.cpu0.dtb.perms_faults 7502 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 64589972 # DTB read accesses +system.cpu0.dtb.write_accesses 58363458 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 124289745 # DTB hits -system.cpu0.dtb.misses 90231 # DTB misses -system.cpu0.dtb.accesses 124379976 # DTB accesses +system.cpu0.dtb.hits 122862311 # DTB hits +system.cpu0.dtb.misses 91119 # DTB misses +system.cpu0.dtb.accesses 122953430 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -517,686 +503,684 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 52885 # Table walker walks requested -system.cpu0.itb.walker.walksLong 52885 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 52885 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 52885 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 52885 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 388941119992 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.527164 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -205035740008 -52.72% -52.72% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 593976860000 152.72% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 388941119992 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 45865 94.85% 94.85% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2491 5.15% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 48356 # Table walker page sizes translated +system.cpu0.itb.walker.walks 53727 # Table walker walks requested +system.cpu0.itb.walker.walksLong 53727 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 53727 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 53727 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 53727 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 392500671624 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.508219 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -199476179626 -50.82% -50.82% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 591976851250 150.82% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 392500671624 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 46661 94.95% 94.95% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2481 5.05% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 49142 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 52885 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 52885 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53727 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53727 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48356 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48356 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 101241 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 347148099 # ITB inst hits -system.cpu0.itb.inst_misses 52885 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49142 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49142 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 102869 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 342517055 # ITB inst hits +system.cpu0.itb.inst_misses 53727 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1197 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1192 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 16324 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 389 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 28527 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 16238 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 399 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 28999 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 347200984 # ITB inst accesses -system.cpu0.itb.hits 347148099 # DTB hits -system.cpu0.itb.misses 52885 # DTB misses -system.cpu0.itb.accesses 347200984 # DTB accesses -system.cpu0.numCycles 418851699 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 342570782 # ITB inst accesses +system.cpu0.itb.hits 342517055 # DTB hits +system.cpu0.itb.misses 53727 # DTB misses +system.cpu0.itb.accesses 342570782 # DTB accesses +system.cpu0.numCycles 413468946 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16522 # number of quiesce instructions executed -system.cpu0.committedInsts 347002044 # Number of instructions committed -system.cpu0.committedOps 408295196 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 375110913 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 357489 # Number of float alu accesses -system.cpu0.num_func_calls 20952666 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 52632755 # number of instructions that are conditional controls -system.cpu0.num_int_insts 375110913 # number of integer instructions -system.cpu0.num_fp_insts 357489 # number of float instructions -system.cpu0.num_int_register_reads 548276980 # number of times the integer registers were read -system.cpu0.num_int_register_writes 297820090 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 571479 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 314936 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 90391371 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 90175878 # number of times the CC registers were written -system.cpu0.num_mem_refs 124362861 # number of memory refs -system.cpu0.num_load_insts 64997668 # Number of load instructions -system.cpu0.num_store_insts 59365193 # Number of store instructions -system.cpu0.num_idle_cycles 408653989.262248 # Number of idle cycles -system.cpu0.num_busy_cycles 10197709.737752 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024347 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975653 # Percentage of idle cycles -system.cpu0.Branches 77385391 # Number of branches fetched +system.cpu0.kern.inst.quiesce 16570 # number of quiesce instructions executed +system.cpu0.committedInsts 342362794 # Number of instructions committed +system.cpu0.committedOps 402636690 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 369953687 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 353210 # Number of float alu accesses +system.cpu0.num_func_calls 20646613 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 51970284 # number of instructions that are conditional controls +system.cpu0.num_int_insts 369953687 # number of integer instructions +system.cpu0.num_fp_insts 353210 # number of float instructions +system.cpu0.num_int_register_reads 539846960 # number of times the integer registers were read +system.cpu0.num_int_register_writes 293703337 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 568892 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 300360 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 89273277 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 89056803 # number of times the CC registers were written +system.cpu0.num_mem_refs 122937235 # number of memory refs +system.cpu0.num_load_insts 64579480 # Number of load instructions +system.cpu0.num_store_insts 58357755 # Number of store instructions +system.cpu0.num_idle_cycles 403595961.081611 # Number of idle cycles +system.cpu0.num_busy_cycles 9872984.918389 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023878 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976122 # Percentage of idle cycles +system.cpu0.Branches 76352356 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 283178336 69.32% 69.32% # Class of executed instruction -system.cpu0.op_class::IntMult 901174 0.22% 69.54% # Class of executed instruction -system.cpu0.op_class::IntDiv 41440 0.01% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 48921 0.01% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::MemRead 64997668 15.91% 85.47% # Class of executed instruction -system.cpu0.op_class::MemWrite 59365193 14.53% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 278960942 69.24% 69.24% # Class of executed instruction +system.cpu0.op_class::IntMult 898467 0.22% 69.46% # Class of executed instruction +system.cpu0.op_class::IntDiv 41470 0.01% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 45104 0.01% 69.49% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu0.op_class::MemRead 64579480 16.03% 85.51% # Class of executed instruction +system.cpu0.op_class::MemWrite 58357755 14.49% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 408532732 # Class of executed instruction -system.cpu0.dcache.tags.replacements 9687552 # number of replacements +system.cpu0.op_class::total 402883218 # Class of executed instruction +system.cpu0.dcache.tags.replacements 9811129 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999716 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 293952506 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9688064 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.341718 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 296592840 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9811641 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.228668 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.138446 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 5.125391 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.691064 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 5.044815 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970974 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.010011 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009162 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.009853 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.870770 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.381737 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.192700 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 6.554509 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968498 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.008558 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010142 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.012802 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1245495121 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1245495121 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 60779853 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 18961352 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 26111596 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 45441324 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 151294125 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 56143457 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 17475743 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 23187165 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 37961445 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 134767810 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 158913 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47173 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 75137 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 114608 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395831 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 129155 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 44895 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu2.data 57683 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu3.data 97740 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 329473 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1454318 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 433667 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 579314 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 933829 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3401128 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1544855 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 472149 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 627026 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1076109 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3720139 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 117052465 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 36481990 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 49356444 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 83500509 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 286391408 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 117211378 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 36529163 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 49431581 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 83615117 # number of overall hits -system.cpu0.dcache.overall_hits::total 286787239 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2029256 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 653198 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 985570 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 3497352 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7165376 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 851964 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 257580 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 600165 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 3409601 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 5119310 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 471821 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 150396 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 207281 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 345345 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1174843 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 677444 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 112505 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu2.data 152358 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu3.data 284476 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1226783 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 91274 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 38716 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 47958 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 178987 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 356935 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu3.data 3 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3558664 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1023283 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1738093 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu3.data 7191429 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 13511469 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4030485 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1173679 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1945374 # number of overall misses -system.cpu0.dcache.overall_misses::cpu3.data 7536774 # number of overall misses -system.cpu0.dcache.overall_misses::total 14686312 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 10960907500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 17114957500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 61176597000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 89252462000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9674205500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 22728130500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 118919985516 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 151322321516 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 2777991000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 3811495000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 7834790952 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 14424276952 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 568655000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 714283000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2393915500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3676853500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 109000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 109000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 23413104000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 43654583000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu3.data 187931373468 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 254999060468 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 23413104000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 43654583000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu3.data 187931373468 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 254999060468 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 62809109 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 19614550 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 27097166 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu3.data 48938676 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 158459501 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 56995421 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 17733323 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 23787330 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu3.data 41371046 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 139887120 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 630734 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 197569 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 282418 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 459953 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1570674 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 806599 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 157400 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 210041 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 382216 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1556256 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1545592 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 472383 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 627272 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1112816 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 3758063 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1544857 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 472149 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 627026 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1076112 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 3720144 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 120611129 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 37505273 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 51094537 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu3.data 90691938 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 299902877 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 121241863 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 37702842 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 51376955 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu3.data 91151891 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 301473551 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032308 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033302 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.036372 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.071464 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.045219 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014948 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014525 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.025230 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.082415 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.036596 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.748051 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.761233 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.733951 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.750827 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.747987 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.839877 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.714771 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.725373 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.744281 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788291 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059054 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081959 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.076455 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.160842 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094978 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029505 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.027284 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.034017 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu3.data 0.079295 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.045053 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.033243 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.031130 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.037865 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu3.data 0.082684 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.048715 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16780.375170 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17365.542275 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17492.261860 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12456.075159 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37558.061573 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37869.803304 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 34877.977076 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 29559.124475 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24692.155904 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 25016.704079 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 27541.131596 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 11757.806354 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14687.855150 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14893.928020 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13374.800963 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10301.185090 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 36333.333333 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21800 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22880.380110 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25116.367766 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 26132.688436 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18872.785814 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19948.473134 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22440.200702 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24935.253925 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17363.042571 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 13201195 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 42765 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 880108 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 406 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.999517 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 105.332512 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 7502187 # number of writebacks -system.cpu0.dcache.writebacks::total 7502187 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3304 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 129070 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1937801 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 2070175 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 4910 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 266090 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2829152 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3100152 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 34 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2050 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 2084 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8564 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 10548 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 110240 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 129352 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 8214 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 395194 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu3.data 4769003 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 5172411 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 8214 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 395194 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu3.data 4769003 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 5172411 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 649894 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 856500 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1559551 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3065945 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 252670 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 334075 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 580449 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1167194 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 150015 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 204632 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 338269 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 692916 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 112505 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 152324 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 282426 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 547255 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 30152 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 37410 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 68747 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 136309 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 1015069 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 1342899 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu3.data 2422426 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4780394 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 1165084 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 1547531 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu3.data 2760695 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5473310 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 6276 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 6461 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 6522 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19259 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 5881 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5970 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6236 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18087 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 12157 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 12431 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 12758 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 37346 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 10091751000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 13620756000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 26803792500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50516299500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9207058000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 12098027000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 21802435152 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 43107520152 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 3089558000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 4271039000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 6719235000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14079832000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 2665486000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 3657832500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 7405729452 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 13729047952 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 402292000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 498531000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 981967500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1882790500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 106000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 106000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 21964295000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 29376615500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 56011957104 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 107352867604 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 25053853000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 33647654500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 62731192104 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 121432699604 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1244510500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1253007000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1222915500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3720433000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1244510500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1253007000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1222915500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3720433000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033133 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031608 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031867 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019348 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014248 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014044 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014030 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008344 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.759304 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.724571 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.735443 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.441158 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.714771 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.725211 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.738917 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.351648 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063830 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.059639 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.061778 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036271 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.027065 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.026283 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.026710 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015940 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.030902 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.030121 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.030287 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018155 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15528.303077 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15902.809107 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17186.865002 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16476.583729 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36439.062809 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 36213.505949 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 37561.327786 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36932.609448 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20594.993834 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20871.804019 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19863.584898 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20319.680885 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23692.155904 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 24013.500827 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 26221.840241 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 25087.112867 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13342.133192 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13326.142743 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14283.786929 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13812.664608 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 35333.333333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 35333.333333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21638.228534 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21875.521167 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 23122.257235 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22456.907862 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21503.902723 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21742.798367 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22722.970884 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22186.336897 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198296.765456 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 193933.911159 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 187506.209752 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193178.929332 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 102369.869211 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 100796.959215 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 95854.796990 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 99620.655492 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 15833780 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.971388 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 559992507 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 15834292 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.365807 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 11768020500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 478.662838 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 4.739189 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 21.951060 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 6.618302 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.934888 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.009256 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.042873 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.012926 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999944 # Average percentage of cache occupancy +system.cpu0.dcache.tags.tag_accesses 1256795104 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1256795104 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 60226997 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 19487622 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 26552483 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 46438516 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 152705618 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 55178222 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 17776476 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 23635965 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 39304314 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 135894977 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 162747 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47920 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 80030 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu3.data 112762 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 403459 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 128939 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 43352 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu2.data 57616 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu3.data 100015 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 329922 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1452193 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 455982 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 583951 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 952022 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3444148 # 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number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 50326094 # number of overall hits +system.cpu0.dcache.overall_hits::cpu3.data 85955607 # number of overall hits +system.cpu0.dcache.overall_hits::total 289333976 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2119141 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 646622 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 956573 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu3.data 3413419 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7135755 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 824381 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 254255 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 649910 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu3.data 3547380 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 5275926 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 507242 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 136623 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 211405 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu3.data 339128 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1194398 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 658327 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 110099 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu2.data 158553 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu3.data 301342 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1228321 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 93463 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 38738 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 47683 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 182809 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 362693 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu3.data 9 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3601849 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1010976 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1765036 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu3.data 7262141 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 13640002 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4109091 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1147599 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1976441 # number of overall misses +system.cpu0.dcache.overall_misses::cpu3.data 7601269 # number of overall misses +system.cpu0.dcache.overall_misses::total 14834400 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 9793359500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15230666500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 50513918000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 75537944000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 7272358500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18053796000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 96990581909 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 122316736409 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 1773607500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 2664287500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 5725219049 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 10163114049 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 551392000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 676206000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2266593000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3494191000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 213500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 213500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 18839325500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 35948750000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu3.data 153229718958 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 208017794458 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 18839325500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 35948750000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu3.data 153229718958 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 208017794458 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 62346138 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 20134244 # 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mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.740332 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.725040 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.739766 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.426958 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.717486 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.733398 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.745688 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.364464 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060111 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.058350 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.061859 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.035934 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026331 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.026408 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.026330 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015976 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.029754 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.030301 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.029776 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018135 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14149.501200 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14859.213011 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15054.253226 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14808.200214 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27599.884359 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26307.233550 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 28898.686200 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27855.825153 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16510.638765 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14009.992807 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 14840.696634 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14917.831983 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 15109.206260 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 15802.779144 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 17870.418859 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 16757.935127 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12994.501984 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12937.649229 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13238.596866 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13104.449026 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 22722.222222 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22722.222222 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17643.333862 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18001.512899 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 18802.539962 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18332.975699 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17508.250240 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17469.330033 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18327.110741 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17910.603138 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183435.682098 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 178816.382396 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 182433.171815 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181591.024410 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 96262.818446 # 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Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 592023830 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 592023830 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 341615603 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 106621003 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 64011899 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu3.inst 47744002 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 559992507 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 341615603 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 106621003 # 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average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13529.567356 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13737.403425 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13472.301513 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8899.534215 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 58905 # number of cycles access was blocked +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015508 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.055250 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu3.inst 0.095511 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.028173 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13417.476778 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13469.061371 # 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number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 3585 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 2970 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.430962 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.169697 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 15833780 # number of writebacks -system.cpu0.icache.writebacks::total 15833780 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 362545 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 362545 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu3.inst 362545 # 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average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 15904025 # number of writebacks +system.cpu0.icache.writebacks::total 15904025 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 364218 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 364218 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu3.inst 364218 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 364218 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu3.inst 364218 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 364218 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1711494 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 3903001 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 4783801 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 10398296 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 1711494 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 3903001 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu3.inst 4783801 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 10398296 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 1711494 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 3903001 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu3.inst 4783801 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 10398296 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 21252437000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 48666759000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 59754516896 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 129673712896 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 21252437000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 48666759000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 59754516896 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 129673712896 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 21252437000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 48666759000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 59754516896 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 129673712896 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015508 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.055250 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.088754 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.018007 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015508 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.055250 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.088754 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.018007 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015508 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.055250 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.088754 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.018007 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12417.476778 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12469.061371 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12491.012251 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12470.669511 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12417.476778 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12469.061371 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12491.012251 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12470.669511 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12417.476778 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12469.061371 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12491.012251 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12470.669511 # average overall mshr miss latency system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1226,70 +1210,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 32812 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 32812 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4690 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 24112 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 32807 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 1.066845 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 193.234552 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 32806 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 32807 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 28807 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 25324.695387 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21900.388938 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15981.091084 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 18461 64.09% 64.09% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 10165 35.29% 99.37% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 148 0.51% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 13 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 1 0.00% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 1 0.00% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 7 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 3 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 5 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 28807 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 2784865428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.637616 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.480689 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1009190500 36.24% 36.24% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 1775674928 63.76% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 2784865428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 24112 83.72% 83.72% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 4690 16.28% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 28802 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 32812 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 32054 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 32054 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4620 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23591 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 2 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 32052 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 32052 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 32052 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 28213 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24818.452486 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21684.712498 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13220.953832 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 18569 65.82% 65.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9436 33.45% 99.26% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 123 0.44% 99.70% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 57 0.20% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 4 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 13 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 2 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 28213 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2332813120 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.567212 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.495462 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1009613500 43.28% 43.28% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1323199620 56.72% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2332813120 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 23591 83.62% 83.62% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 4620 16.38% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 28211 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 32054 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 32812 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 28802 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 32054 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 28211 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 28802 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 61614 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 28211 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 60265 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 20290778 # DTB read hits -system.cpu1.dtb.read_misses 25288 # DTB read misses -system.cpu1.dtb.write_hits 18371397 # DTB write hits -system.cpu1.dtb.write_misses 7524 # DTB write misses -system.cpu1.dtb.flush_tlb 1188 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 20818389 # DTB read hits +system.cpu1.dtb.read_misses 24417 # DTB read misses +system.cpu1.dtb.write_hits 18685767 # DTB write hits +system.cpu1.dtb.write_misses 7637 # DTB write misses +system.cpu1.dtb.flush_tlb 1184 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 5447 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 137 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 18352 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 5343 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 135 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 18131 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 929 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 972 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 2632 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 20316066 # DTB read accesses -system.cpu1.dtb.write_accesses 18378921 # DTB write accesses +system.cpu1.dtb.perms_faults 2619 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 20842806 # DTB read accesses +system.cpu1.dtb.write_accesses 18693404 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 38662175 # DTB hits -system.cpu1.dtb.misses 32812 # DTB misses -system.cpu1.dtb.accesses 38694987 # DTB accesses +system.cpu1.dtb.hits 39504156 # DTB hits +system.cpu1.dtb.misses 32054 # DTB misses +system.cpu1.dtb.accesses 39536210 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1319,139 +1300,138 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 20715 # Table walker walks requested -system.cpu1.itb.walker.walksLong 20715 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 943 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 18376 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 20715 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 20715 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 20715 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 19319 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28783.140949 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25411.076231 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19382.499659 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 9731 50.37% 50.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 9374 48.52% 98.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 1 0.01% 98.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 168 0.87% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 22 0.11% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 9 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 7 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 3 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 19319 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 20183 # Table walker walks requested +system.cpu1.itb.walker.walksLong 20183 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 931 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17873 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 20183 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 20183 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 20183 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 18804 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 27697.085726 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24882.952231 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 14267.961573 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 10321 54.89% 54.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 8257 43.91% 98.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 85 0.45% 99.25% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 115 0.61% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 9 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 4 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 8 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 18804 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 18376 95.12% 95.12% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 943 4.88% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 19319 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 17873 95.05% 95.05% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 931 4.95% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 18804 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20715 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20715 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20183 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20183 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 19319 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 19319 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 40034 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 108288078 # ITB inst hits -system.cpu1.itb.inst_misses 20715 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18804 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18804 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 38987 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 110361810 # ITB inst hits +system.cpu1.itb.inst_misses 20183 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1188 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1184 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 5447 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 137 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 13933 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 5343 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 135 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 13509 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 108308793 # ITB inst accesses -system.cpu1.itb.hits 108288078 # DTB hits -system.cpu1.itb.misses 20715 # DTB misses -system.cpu1.itb.accesses 108308793 # DTB accesses -system.cpu1.numCycles 1188105502 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 110381993 # ITB inst accesses +system.cpu1.itb.hits 110361810 # DTB hits +system.cpu1.itb.misses 20183 # DTB misses +system.cpu1.itb.accesses 110381993 # DTB accesses +system.cpu1.numCycles 1184092485 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 108209898 # Number of instructions committed -system.cpu1.committedOps 126974949 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 116708707 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 113927 # Number of float alu accesses -system.cpu1.num_func_calls 6429899 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 16402371 # number of instructions that are conditional controls -system.cpu1.num_int_insts 116708707 # number of integer instructions -system.cpu1.num_fp_insts 113927 # number of float instructions -system.cpu1.num_int_register_reads 168563743 # number of times the integer registers were read -system.cpu1.num_int_register_writes 92548799 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 187994 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 86044 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 27990654 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27915757 # number of times the CC registers were written -system.cpu1.num_mem_refs 38659204 # number of memory refs -system.cpu1.num_load_insts 20289811 # Number of load instructions -system.cpu1.num_store_insts 18369393 # Number of store instructions -system.cpu1.num_idle_cycles 1163060687.092743 # Number of idle cycles -system.cpu1.num_busy_cycles 25044814.907257 # Number of busy cycles -system.cpu1.not_idle_fraction 0.021080 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.978920 # Percentage of idle cycles -system.cpu1.Branches 24096387 # Number of branches fetched +system.cpu1.committedInsts 110287651 # Number of instructions committed +system.cpu1.committedOps 129462738 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 119015901 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 118522 # Number of float alu accesses +system.cpu1.num_func_calls 6563146 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 16773404 # number of instructions that are conditional controls +system.cpu1.num_int_insts 119015901 # number of integer instructions +system.cpu1.num_fp_insts 118522 # number of float instructions +system.cpu1.num_int_register_reads 171436551 # number of times the integer registers were read +system.cpu1.num_int_register_writes 94361756 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 191512 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 99140 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 28456563 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 28368844 # number of times the CC registers were written +system.cpu1.num_mem_refs 39501087 # number of memory refs +system.cpu1.num_load_insts 20816799 # Number of load instructions +system.cpu1.num_store_insts 18684288 # Number of store instructions +system.cpu1.num_idle_cycles 1157765533.383607 # Number of idle cycles +system.cpu1.num_busy_cycles 26326951.616393 # Number of busy cycles +system.cpu1.not_idle_fraction 0.022234 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.977766 # Percentage of idle cycles +system.cpu1.Branches 24650673 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 88104313 69.34% 69.34% # Class of executed instruction -system.cpu1.op_class::IntMult 267805 0.21% 69.56% # Class of executed instruction -system.cpu1.op_class::IntDiv 10742 0.01% 69.56% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 11023 0.01% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::MemRead 20289811 15.97% 85.54% # Class of executed instruction -system.cpu1.op_class::MemWrite 18369393 14.46% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 89732955 69.27% 69.27% # Class of executed instruction +system.cpu1.op_class::IntMult 279120 0.22% 69.49% # Class of executed instruction +system.cpu1.op_class::IntDiv 11472 0.01% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 12221 0.01% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::MemRead 20816799 16.07% 85.58% # Class of executed instruction +system.cpu1.op_class::MemWrite 18684288 14.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 127053129 # Class of executed instruction -system.cpu2.branchPred.lookups 39776917 # Number of BP lookups -system.cpu2.branchPred.condPredicted 27483460 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 2037436 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 28756518 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 19292729 # Number of BTB hits +system.cpu1.op_class::total 129536897 # Class of executed instruction +system.cpu2.branchPred.lookups 40914061 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28392312 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2019755 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 29835012 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 20286508 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 67.089934 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4859404 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 317380 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 1168446 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 802318 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 366128 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 149530 # Number of mispredicted indirect branches. +system.cpu2.branchPred.BTBHitPct 67.995642 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4999749 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 330951 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 1158254 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 808792 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 349462 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 143811 # Number of mispredicted indirect branches. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1481,66 +1461,59 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 93967 # Table walker walks requested -system.cpu2.dtb.walker.walksLong 93967 # Table walker walks initiated with long descriptors -system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6944 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29768 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 93967 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 93967 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 93967 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 36712 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 25539.442144 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 22201.127196 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 16823.219049 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-32767 24012 65.41% 65.41% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::32768-65535 12449 33.91% 99.32% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-163839 190 0.52% 99.83% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::163840-196607 24 0.07% 99.90% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::196608-229375 5 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::229376-262143 3 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-294911 13 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::360448-393215 4 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::393216-425983 6 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::425984-458751 2 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 36712 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 2000224000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0 2000224000 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 2000224000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 29768 81.09% 81.09% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::2M 6944 18.91% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 36712 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93967 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walks 93613 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 93613 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7056 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 30134 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 93613 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 93613 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 93613 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 37190 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 24826.364614 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 21866.546445 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 12685.900174 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-65535 36979 99.43% 99.43% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::65536-131071 182 0.49% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-196607 14 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-262143 8 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::327680-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 37190 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 2000359500 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0 2000359500 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 2000359500 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 30134 81.03% 81.03% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 7056 18.97% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 37190 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93613 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93967 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36712 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93613 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 37190 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36712 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 130679 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 37190 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 130803 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 28283757 # DTB read hits -system.cpu2.dtb.read_misses 78317 # DTB read misses -system.cpu2.dtb.write_hits 24727017 # DTB write hits -system.cpu2.dtb.write_misses 15650 # DTB write misses -system.cpu2.dtb.flush_tlb 1188 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 28720728 # DTB read hits +system.cpu2.dtb.read_misses 78135 # DTB read misses +system.cpu2.dtb.write_hits 25235469 # DTB write hits +system.cpu2.dtb.write_misses 15478 # DTB write misses +system.cpu2.dtb.flush_tlb 1184 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 6736 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 178 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 22142 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 90 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 2053 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 6949 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 188 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 22306 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 80 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 2280 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 3761 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 28362074 # DTB read accesses -system.cpu2.dtb.write_accesses 24742667 # DTB write accesses +system.cpu2.dtb.perms_faults 3881 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 28798863 # DTB read accesses +system.cpu2.dtb.write_accesses 25250947 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 53010774 # DTB hits -system.cpu2.dtb.misses 93967 # DTB misses -system.cpu2.dtb.accesses 53104741 # DTB accesses +system.cpu2.dtb.hits 53956197 # DTB hits +system.cpu2.dtb.misses 93613 # DTB misses +system.cpu2.dtb.accesses 54049810 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1570,125 +1543,126 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 27720 # Table walker walks requested -system.cpu2.itb.walker.walksLong 27720 # Table walker walks initiated with long descriptors -system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1832 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksLongTerminationLevel::Level3 23079 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 27720 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 27720 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 27720 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 24911 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 29141.122396 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 25972.278022 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 17945.677356 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-32767 12737 51.13% 51.13% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-65535 11873 47.66% 98.79% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.80% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::131072-163839 235 0.94% 99.74% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::163840-196607 44 0.18% 99.92% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::196608-229375 4 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::229376-262143 2 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::262144-294911 11 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walks 26529 # Table walker walks requested +system.cpu2.itb.walker.walksLong 26529 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1840 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22126 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 26529 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 26529 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 26529 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 23966 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 28028.290078 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 25290.360104 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 14051.232329 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 12906 53.85% 53.85% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 10781 44.98% 98.84% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::65536-98303 94 0.39% 99.23% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::98304-131071 160 0.67% 99.90% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 3 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::163840-196607 9 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::196608-229375 3 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::229376-262143 3 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::262144-294911 2 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.98% # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 24911 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 2000197500 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 2000197500 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 2000197500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 23079 92.65% 92.65% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::2M 1832 7.35% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 24911 # Table walker page sizes translated +system.cpu2.itb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 23966 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 2000327500 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 2000327500 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 2000327500 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 22126 92.32% 92.32% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 1840 7.68% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 23966 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27720 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27720 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 26529 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 26529 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24911 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24911 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 52631 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 67934299 # ITB inst hits -system.cpu2.itb.inst_misses 27720 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 23966 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 23966 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 50495 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 70694439 # ITB inst hits +system.cpu2.itb.inst_misses 26529 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1188 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1184 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 6736 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 178 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 16373 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 6949 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 188 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 16608 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 46985 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 49134 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 67962019 # ITB inst accesses -system.cpu2.itb.hits 67934299 # DTB hits -system.cpu2.itb.misses 27720 # DTB misses -system.cpu2.itb.accesses 67962019 # DTB accesses -system.cpu2.numCycles 6665035719 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 70720968 # ITB inst accesses +system.cpu2.itb.hits 70694439 # DTB hits +system.cpu2.itb.misses 26529 # DTB misses +system.cpu2.itb.accesses 70720968 # DTB accesses +system.cpu2.numCycles 1178523145 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 145016271 # Number of instructions committed -system.cpu2.committedOps 170167286 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 13691437 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 1431 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 95890552078 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 45.960606 # CPI: cycles per instruction -system.cpu2.ipc 0.021758 # IPC: instructions per cycle +system.cpu2.committedInsts 148428479 # Number of instructions committed +system.cpu2.committedOps 174146855 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 14845041 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 1527 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 5665146 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 7.940007 # CPI: cycles per instruction +system.cpu2.ipc 0.125944 # IPC: instructions per cycle system.cpu2.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.op_class_0::IntAlu 117737819 69.19% 69.19% # Class of committed instruction -system.cpu2.op_class_0::IntMult 373156 0.22% 69.41% # Class of committed instruction -system.cpu2.op_class_0::IntDiv 14991 0.01% 69.42% # Class of committed instruction -system.cpu2.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMisc 14732 0.01% 69.43% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu2.op_class_0::MemRead 27395173 16.10% 85.53% # Class of committed instruction -system.cpu2.op_class_0::MemWrite 24631415 14.47% 100.00% # Class of committed instruction +system.cpu2.op_class_0::IntAlu 120785530 69.36% 69.36% # Class of committed instruction +system.cpu2.op_class_0::IntMult 363959 0.21% 69.57% # Class of committed instruction +system.cpu2.op_class_0::IntDiv 15220 0.01% 69.58% # Class of committed instruction +system.cpu2.op_class_0::FloatAdd 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::FloatCmp 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::FloatCvt 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::FloatMult 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::FloatDiv 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::FloatSqrt 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdAdd 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdAddAcc 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdAlu 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdCmp 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdCvt 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdMisc 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdMult 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdMultAcc 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdShift 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdSqrt 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMisc 16120 0.01% 69.59% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMult 0 0.00% 69.59% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 69.59% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 69.59% # Class of committed instruction +system.cpu2.op_class_0::MemRead 27827190 15.98% 85.56% # Class of committed instruction +system.cpu2.op_class_0::MemWrite 25138836 14.44% 100.00% # Class of committed instruction system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.op_class_0::total 170167286 # Class of committed instruction +system.cpu2.op_class_0::total 174146855 # Class of committed instruction system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 269996715 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 6395039004 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 74192352 # Number of BP lookups -system.cpu3.branchPred.condPredicted 49437452 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 3347278 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 50136785 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 33881997 # Number of BTB hits +system.cpu2.tickCycles 278422703 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 900100442 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 75872804 # Number of BP lookups +system.cpu3.branchPred.condPredicted 50609506 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 3388105 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 51366888 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 34595075 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 67.579118 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 9625210 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 106045 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 2919697 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 1497835 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 1421862 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 235981 # Number of mispredicted indirect branches. +system.cpu3.branchPred.BTBHitPct 67.348980 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 9780520 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 107006 # Number of incorrect RAS predictions. +system.cpu3.branchPred.indirectLookups 3035481 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 1551109 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 1484372 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 245540 # Number of mispredicted indirect branches. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1718,88 +1692,97 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 504531 # Table walker walks requested -system.cpu3.dtb.walker.walksLong 504531 # Table walker walks initiated with long descriptors -system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8579 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 49642 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 315573 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 188958 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 2466.701595 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 15451.703294 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-65535 187621 99.29% 99.29% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-131071 761 0.40% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::131072-196607 388 0.21% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::196608-262143 66 0.03% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::262144-327679 68 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::327680-393215 12 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::393216-458751 16 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::458752-524287 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::720896-786431 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 188958 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 235670 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 22726.150974 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 18499.548679 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 17978.117081 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-65535 231036 98.03% 98.03% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3674 1.56% 99.59% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-196607 687 0.29% 99.88% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::196608-262143 78 0.03% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::262144-327679 114 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::327680-393215 27 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::393216-458751 37 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::524288-589823 12 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 235670 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -29346850516 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.109432 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-3 -29931174016 101.99% 101.99% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-7 321600000 -1.10% 100.90% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-11 109899000 -0.37% 100.52% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-15 66660000 -0.23% 100.29% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-19 26916000 -0.09% 100.20% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-23 15037500 -0.05% 100.15% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-27 15685000 -0.05% 100.10% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-31 23345000 -0.08% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::32-35 4979000 -0.02% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::36-39 163000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::40-43 37500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::44-47 1500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -29346850516 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 49642 85.26% 85.26% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::2M 8579 14.74% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 58221 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 504531 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walks 515601 # Table walker walks requested +system.cpu3.dtb.walker.walksLong 515601 # Table walker walks initiated with long descriptors +system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8515 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 50947 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 323770 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 191831 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 2186.536587 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 12259.515456 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-32767 187758 97.88% 97.88% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-65535 2920 1.52% 99.40% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-98303 506 0.26% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::98304-131071 334 0.17% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::131072-163839 139 0.07% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::163840-196607 61 0.03% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::196608-229375 40 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::229376-262143 20 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::262144-294911 20 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::294912-327679 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::327680-360447 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::360448-393215 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::393216-425983 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::425984-458751 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 191831 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 241555 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 22389.801494 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 18267.883118 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 16107.200178 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-32767 187656 77.69% 77.69% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-65535 48957 20.27% 97.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-98303 3861 1.60% 99.55% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::98304-131071 637 0.26% 99.82% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-163839 131 0.05% 99.87% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::163840-196607 99 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::196608-229375 72 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::229376-262143 72 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::262144-294911 24 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::294912-327679 10 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::327680-360447 14 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::425984-458751 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 241555 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -21501827588 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean -0.278457 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-3 -22090252588 102.74% 102.74% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-7 330768000 -1.54% 101.20% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-11 106533500 -0.50% 100.70% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-15 66241000 -0.31% 100.39% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-19 26933500 -0.13% 100.27% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-23 15179500 -0.07% 100.20% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-27 14407500 -0.07% 100.13% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-31 23051000 -0.11% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::32-35 5101000 -0.02% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::36-39 177500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::40-43 28500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::44-47 4000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -21501827588 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 50947 85.68% 85.68% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::2M 8515 14.32% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 59462 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 515601 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 504531 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 58221 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 515601 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 59462 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 58221 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 562752 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 59462 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 575063 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 58858607 # DTB read hits -system.cpu3.dtb.read_misses 345619 # DTB read misses -system.cpu3.dtb.write_hits 45337458 # DTB write hits -system.cpu3.dtb.write_misses 158912 # DTB write misses -system.cpu3.dtb.flush_tlb 1187 # Number of times complete TLB was flushed +system.cpu3.dtb.read_hits 59668425 # DTB read hits +system.cpu3.dtb.read_misses 351201 # DTB read misses +system.cpu3.dtb.write_hits 46869082 # DTB write hits +system.cpu3.dtb.write_misses 164400 # DTB write misses +system.cpu3.dtb.flush_tlb 1184 # Number of times complete TLB was flushed system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.dtb.flush_tlb_mva_asid 11014 # Number of times TLB was flushed by MVA & ASID -system.cpu3.dtb.flush_tlb_asid 317 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 30161 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 96 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 4984 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_tlb_mva_asid 11562 # Number of times TLB was flushed by MVA & ASID +system.cpu3.dtb.flush_tlb_asid 307 # Number of times TLB was flushed by ASID +system.cpu3.dtb.flush_entries 29776 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 81 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 5087 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 31824 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 59204226 # DTB read accesses -system.cpu3.dtb.write_accesses 45496370 # DTB write accesses +system.cpu3.dtb.perms_faults 32866 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 60019626 # DTB read accesses +system.cpu3.dtb.write_accesses 47033482 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 104196065 # DTB hits -system.cpu3.dtb.misses 504531 # DTB misses -system.cpu3.dtb.accesses 104700596 # DTB accesses +system.cpu3.dtb.hits 106537507 # DTB hits +system.cpu3.dtb.misses 515601 # DTB misses +system.cpu3.dtb.accesses 107053108 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1829,388 +1812,386 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 57749 # Table walker walks requested -system.cpu3.itb.walker.walksLong 57749 # Table walker walks initiated with long descriptors -system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1869 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksLongTerminationLevel::Level3 39849 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 8061 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 49688 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1392.157060 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 9705.040089 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-32767 49238 99.09% 99.09% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-65535 280 0.56% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-98303 20 0.04% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-131071 53 0.11% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::131072-163839 71 0.14% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::163840-196607 11 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::196608-229375 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::229376-262143 8 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 49688 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 49779 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 28899.797103 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 24686.192128 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 20239.281965 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-32767 26767 53.77% 53.77% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-65535 22147 44.49% 98.26% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::65536-98303 258 0.52% 98.78% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::98304-131071 22 0.04% 98.82% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::131072-163839 390 0.78% 99.61% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::163840-196607 115 0.23% 99.84% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::196608-229375 17 0.03% 99.87% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.89% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::262144-294911 35 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::393216-425983 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::425984-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 49779 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -29349528016 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.914056 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.275786 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -2489826708 8.48% 8.48% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -26888510808 91.61% 100.10% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 25356500 -0.09% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 3132000 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 321000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -29349528016 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 39849 95.52% 95.52% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::2M 1869 4.48% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 41718 # Table walker page sizes translated +system.cpu3.itb.walker.walks 59193 # Table walker walks requested +system.cpu3.itb.walker.walksLong 59193 # Table walker walks initiated with long descriptors +system.cpu3.itb.walker.walksLongTerminationLevel::Level2 2031 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksLongTerminationLevel::Level3 40773 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 8103 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 51090 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1228.772754 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 7780.748037 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-32767 50655 99.15% 99.15% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-65535 286 0.56% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-98303 82 0.16% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::98304-131071 46 0.09% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::131072-163839 10 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 51090 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 50907 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 28166.146110 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 24191.673448 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 17123.817204 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-32767 28249 55.49% 55.49% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-65535 21614 42.46% 97.95% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::65536-98303 468 0.92% 98.87% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::98304-131071 440 0.86% 99.73% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::131072-163839 42 0.08% 99.82% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::163840-196607 46 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::196608-229375 22 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::229376-262143 5 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::262144-294911 4 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::327680-360447 8 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 50907 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -25799318884 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.966437 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.171998 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -833253492 3.23% 3.23% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -24994847892 96.88% 100.11% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 25196000 -0.10% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 3318000 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 257000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 11500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -25799318884 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 40773 95.26% 95.26% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::2M 2031 4.74% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 42804 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 57749 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 57749 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 59193 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 59193 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 41718 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 41718 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 99467 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 52942414 # ITB inst hits -system.cpu3.itb.inst_misses 57749 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 42804 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 42804 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 101997 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 54025408 # ITB inst hits +system.cpu3.itb.inst_misses 59193 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.flush_tlb 1187 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb 1184 # Number of times complete TLB was flushed system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.itb.flush_tlb_mva_asid 11014 # Number of times TLB was flushed by MVA & ASID -system.cpu3.itb.flush_tlb_asid 317 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 23395 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_tlb_mva_asid 11562 # Number of times TLB was flushed by MVA & ASID +system.cpu3.itb.flush_tlb_asid 307 # Number of times TLB was flushed by ASID +system.cpu3.itb.flush_entries 22881 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 105407 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 108557 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 53000163 # ITB inst accesses -system.cpu3.itb.hits 52942414 # DTB hits -system.cpu3.itb.misses 57749 # DTB misses -system.cpu3.itb.accesses 53000163 # DTB accesses -system.cpu3.numCycles 367393110 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 54084601 # ITB inst accesses +system.cpu3.itb.hits 54025408 # DTB hits +system.cpu3.itb.misses 59193 # DTB misses +system.cpu3.itb.accesses 54084601 # DTB accesses +system.cpu3.numCycles 361836520 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 140035473 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 329019087 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 74192352 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 45005042 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 204823343 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 7558478 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 1392210 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 11060 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 2040 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 2559054 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 98792 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 5855 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 52820449 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 2085044 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 22116 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 352706869 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.090104 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.342261 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 142346168 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 336897254 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 75872804 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 45926704 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 198396992 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 7651750 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 1405577 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 5653 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 1383 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 2613876 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 96442 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 3584 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 53899852 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 2112674 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 22747 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 348695424 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.129497 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.376512 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 272076000 77.14% 77.14% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 10117728 2.87% 80.01% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 10161980 2.88% 82.89% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 7427862 2.11% 85.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 15229127 4.32% 89.31% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 5034181 1.43% 90.74% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 5424859 1.54% 92.28% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 4755580 1.35% 93.63% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 22479552 6.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 266239908 76.35% 76.35% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 10306563 2.96% 79.31% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 10284239 2.95% 82.26% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 7691718 2.21% 84.46% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 15615273 4.48% 88.94% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 5057857 1.45% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 5501918 1.58% 91.97% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 4845338 1.39% 93.36% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 23152610 6.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 352706869 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.201943 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.895551 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 114206040 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 168667111 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 59684206 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7159093 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2988451 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 11027683 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 801920 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 358900429 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 2465138 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 2988451 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 118341583 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 14120881 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 134077735 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 62618980 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 20557172 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 350288919 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 64776 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1233598 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 933453 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 10294556 # Number of times rename has blocked due to SQ full -system.cpu3.rename.FullRegisterEvents 2108 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 333834444 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 533414830 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 412704173 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 534789 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 279088781 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 54745658 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 7872437 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 6763416 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 39440187 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 56882383 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 47659648 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 7390317 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 8048428 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 332440192 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7866599 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 331640119 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 487315 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 46360769 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 29124307 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 191271 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 352706869 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.940271 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.666990 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 348695424 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.209688 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.931076 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 116362710 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 160827903 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 61169614 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7306733 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 3026861 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 11256055 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 810097 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 368055040 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 2493002 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 3026861 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 120564311 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 11200780 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 131699731 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 64193761 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 18008282 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 359339338 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 52499 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 958756 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 756701 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 7766170 # Number of times rename has blocked due to SQ full +system.cpu3.rename.FullRegisterEvents 2268 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 342255199 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 547447054 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 423264500 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 516863 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 287051688 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 55203506 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 8135865 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 7007620 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 40276067 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 57867192 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 49204017 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 7450996 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 7967631 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 341094082 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 8138044 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 340373041 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 493634 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 46733837 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 29214718 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 196934 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 348695424 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.976133 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.690131 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 224298657 63.59% 63.59% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 52689618 14.94% 78.53% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 24223023 6.87% 85.40% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 17391351 4.93% 90.33% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 12809979 3.63% 93.96% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 9108183 2.58% 96.54% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 6180606 1.75% 98.30% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 3577681 1.01% 99.31% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 2427771 0.69% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 216968703 62.22% 62.22% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 54146545 15.53% 77.75% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 24769246 7.10% 84.85% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 17826986 5.11% 89.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 13092392 3.75% 93.72% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 9312814 2.67% 96.39% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 6328109 1.81% 98.21% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 3700278 1.06% 99.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 2550351 0.73% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 352706869 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 348695424 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 1672825 25.77% 25.77% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 16469 0.25% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 1475 0.02% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 2639879 40.67% 66.72% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 2160482 33.28% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 1713777 25.74% 25.74% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 17699 0.27% 26.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 1135 0.02% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 2657686 39.92% 65.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 2267999 34.06% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 27 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 224723694 67.76% 67.76% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 782210 0.24% 68.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 40081 0.01% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 289 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 42689 0.01% 68.02% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.02% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.02% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.02% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 60119649 18.13% 86.15% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 45931480 13.85% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 4 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 231084475 67.89% 67.89% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 790161 0.23% 68.12% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 39649 0.01% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 230 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 2 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 1 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 44022 0.01% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 60938583 17.90% 86.05% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 47475914 13.95% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 331640119 # Type of FU issued -system.cpu3.iq.rate 0.902685 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 6491130 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.019573 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 1022298212 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 386704326 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 319186755 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 667340 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 341320 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 298656 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 337775175 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 356047 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 2654997 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 340373041 # Type of FU issued +system.cpu3.iq.rate 0.940682 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 6658296 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.019562 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 1035940060 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 396014860 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 328005954 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 653376 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 333988 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 291600 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 346682688 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 348645 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 2712348 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 9481961 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 11664 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 384451 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 4830568 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 9520955 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 12048 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 389231 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 4853610 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 2150262 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 4167936 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 2139160 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 4030631 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2988451 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 8896535 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 3943315 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 340388861 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 1005407 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 56882383 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 47659648 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 6617026 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 121260 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 3776054 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 384451 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 1420846 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1561965 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 2982811 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 327664673 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 58849807 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 3477335 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 3026861 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 7711218 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 2621141 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 349315178 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 1020364 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 57867192 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 49204017 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 6861602 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 115452 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 2462398 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 389231 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 1435072 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1591104 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 3026176 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 336329886 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 59659129 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 3533928 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 82070 # number of nop insts executed -system.cpu3.iew.exec_refs 104185879 # number of memory reference insts executed -system.cpu3.iew.exec_branches 60732264 # Number of branches executed -system.cpu3.iew.exec_stores 45336072 # Number of stores executed -system.cpu3.iew.exec_rate 0.891864 # Inst execution rate -system.cpu3.iew.wb_sent 320275931 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 319485411 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 157730975 # num instructions producing a value -system.cpu3.iew.wb_consumers 273958307 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.869601 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.575748 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 46394137 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7675328 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2556293 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 344852948 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.852381 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.849144 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 83052 # number of nop insts executed +system.cpu3.iew.exec_refs 106526406 # number of memory reference insts executed +system.cpu3.iew.exec_branches 62299744 # Number of branches executed +system.cpu3.iew.exec_stores 46867277 # Number of stores executed +system.cpu3.iew.exec_rate 0.929508 # Inst execution rate +system.cpu3.iew.wb_sent 329094434 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 328297554 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 161959018 # num instructions producing a value +system.cpu3.iew.wb_consumers 281119845 # num instructions consuming a value +system.cpu3.iew.wb_rate 0.907309 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.576121 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 46762853 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7941110 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2588965 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 340775286 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.887677 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.879536 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 238109143 69.05% 69.05% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 51559449 14.95% 84.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 18667514 5.41% 89.41% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8519895 2.47% 91.88% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 6096374 1.77% 93.65% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 3704494 1.07% 94.72% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 3440464 1.00% 95.72% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 2103815 0.61% 96.33% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 12651800 3.67% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 231011602 67.79% 67.79% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 53095779 15.58% 83.37% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 18991936 5.57% 88.94% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8794245 2.58% 91.52% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 6362030 1.87% 93.39% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 3754940 1.10% 94.49% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 3557662 1.04% 95.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 2189630 0.64% 96.18% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 13017462 3.82% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 344852948 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 250222532 # Number of instructions committed -system.cpu3.commit.committedOps 293946017 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 340775286 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 257394207 # Number of instructions committed +system.cpu3.commit.committedOps 302498284 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 90229501 # Number of memory references committed -system.cpu3.commit.loads 47400421 # Number of loads committed -system.cpu3.commit.membars 1979442 # Number of memory barriers committed -system.cpu3.commit.branches 55926403 # Number of branches committed -system.cpu3.commit.fp_insts 287180 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 270155076 # Number of committed integer instructions. -system.cpu3.commit.function_calls 7460078 # Number of function calls committed. +system.cpu3.commit.refs 92696643 # Number of memory references committed +system.cpu3.commit.loads 48346236 # Number of loads committed +system.cpu3.commit.membars 2024611 # Number of memory barriers committed +system.cpu3.commit.branches 57446863 # Number of branches committed +system.cpu3.commit.fp_insts 280508 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 277937546 # Number of committed integer instructions. +system.cpu3.commit.function_calls 7603985 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 203036725 69.07% 69.07% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 612324 0.21% 69.28% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 30368 0.01% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 37099 0.01% 69.30% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 47400421 16.13% 85.43% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 42829080 14.57% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 209109353 69.13% 69.13% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 624464 0.21% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 29794 0.01% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 38030 0.01% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 48346236 15.98% 85.34% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 44350407 14.66% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 293946017 # Class of committed instruction -system.cpu3.commit.bw_lim_events 12651800 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 670506126 # The number of ROB reads -system.cpu3.rob.rob_writes 688548433 # The number of ROB writes -system.cpu3.timesIdled 2399435 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 14686241 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 98624955783 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 250222532 # Number of Instructions Simulated -system.cpu3.committedOps 293946017 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.468265 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.468265 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.681076 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.681076 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 385596565 # number of integer regfile reads -system.cpu3.int_regfile_writes 228796101 # number of integer regfile writes -system.cpu3.fp_regfile_reads 580685 # number of floating regfile reads -system.cpu3.fp_regfile_writes 358952 # number of floating regfile writes -system.cpu3.cc_regfile_reads 69302556 # number of cc regfile reads -system.cpu3.cc_regfile_writes 69940425 # number of cc regfile writes -system.cpu3.misc_regfile_reads 654940348 # number of misc regfile reads -system.cpu3.misc_regfile_writes 7733963 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40259 # Transaction distribution -system.iobus.trans_dist::ReadResp 40259 # Transaction distribution +system.cpu3.commit.op_class_0::total 302498284 # Class of committed instruction +system.cpu3.commit.bw_lim_events 13017462 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 674966133 # The number of ROB reads +system.cpu3.rob.rob_writes 706454494 # The number of ROB writes +system.cpu3.timesIdled 2436524 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 13141096 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 98718347024 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 257394207 # Number of Instructions Simulated +system.cpu3.committedOps 302498284 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.405768 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.405768 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.711355 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.711355 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 395796018 # number of integer regfile reads +system.cpu3.int_regfile_writes 234887439 # number of integer regfile writes +system.cpu3.fp_regfile_reads 565351 # number of floating regfile reads +system.cpu3.fp_regfile_writes 361110 # number of floating regfile writes +system.cpu3.cc_regfile_reads 71210349 # number of cc regfile reads +system.cpu3.cc_regfile_writes 71874336 # number of cc regfile writes +system.cpu3.misc_regfile_reads 658260097 # number of misc regfile reads +system.cpu3.misc_regfile_writes 8003769 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40273 # Transaction distribution +system.iobus.trans_dist::ReadResp 40273 # Transaction distribution system.iobus.trans_dist::WriteReq 136539 # Transaction distribution system.iobus.trans_dist::WriteResp 136539 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes) @@ -2227,11 +2208,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230940 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230968 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353596 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353624 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -2246,91 +2227,93 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155706 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334192 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334192 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334304 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7491984 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 28447500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13621500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 5500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 82500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 18500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 5000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 12315500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 11667500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 21455000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 21479000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 262449133 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 236022564 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 54866000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 41037000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 76206000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 70810000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115457 # number of replacements -system.iocache.tags.tagsinuse 10.420631 # Cycle average of tags in use +system.iocache.tags.replacements 115466 # number of replacements +system.iocache.tags.tagsinuse 10.425431 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115482 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13089104998009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 5.909087 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 4.511544 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.369318 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.281971 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651289 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13087288267509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544657 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.880774 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221541 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430048 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651589 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039587 # Number of tag accesses -system.iocache.tags.data_accesses 1039587 # Number of data accesses +system.iocache.tags.tag_accesses 1039713 # Number of tag accesses +system.iocache.tags.data_accesses 1039713 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8806 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8843 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115470 # number of demand (read+write) misses -system.iocache.demand_misses::total 115510 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115484 # number of demand (read+write) misses +system.iocache.demand_misses::total 115524 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115470 # number of overall misses -system.iocache.overall_misses::total 115510 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 1073978422 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1073978422 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 6143621711 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 6143621711 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 7217600133 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7217600133 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 7217600133 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7217600133 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 115484 # number of overall misses +system.iocache.overall_misses::total 115524 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 1088192723 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1088192723 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 5155830841 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5155830841 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 6244023564 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6244023564 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 6244023564 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6244023564 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8806 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8843 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8820 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8857 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115470 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115510 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115484 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115524 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115470 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115510 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115484 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115524 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2344,830 +2327,838 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 121959.848058 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 121449.555807 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 57597.893488 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 57597.893488 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 62506.279839 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 62484.634516 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 62506.279839 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 62484.634516 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 21262 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123377.859751 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122862.450378 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 48337.122562 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 48337.122562 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 54068.300059 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 54049.578997 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 54068.300059 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 54049.578997 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22542 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2148 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2372 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.898510 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.503373 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 5707 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 5707 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 48856 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 48856 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 54563 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 54563 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 54563 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 54563 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 788628422 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 788628422 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3698645601 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3698645601 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 4487274023 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4487274023 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 4487274023 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4487274023 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.648081 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.645369 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.458036 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.458036 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.472530 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.472366 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.472530 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.472366 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138186.161206 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 138186.161206 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75705.043413 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75705.043413 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 82240.236479 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82240.236479 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 82240.236479 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82240.236479 # average overall mshr miss latency -system.l2c.tags.replacements 1158394 # number of replacements -system.l2c.tags.tagsinuse 65318.411237 # Cycle average of tags in use -system.l2c.tags.total_refs 47534578 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1221500 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 38.914923 # Average number of references to valid blocks. +system.iocache.ReadReq_mshr_misses::realview.ide 5693 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 5693 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 43488 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 43488 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 49181 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 49181 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 49181 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 49181 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 803542723 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 803542723 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2978631735 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2978631735 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 3782174458 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3782174458 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 3782174458 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3782174458 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.645465 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.642768 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.407710 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.407710 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.425869 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.425721 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.425869 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.425721 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141145.744423 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 141145.744423 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68493.187431 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68493.187431 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76903.162969 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76903.162969 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76903.162969 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76903.162969 # average overall mshr miss latency +system.l2c.tags.replacements 1175380 # number of replacements +system.l2c.tags.tagsinuse 65273.508044 # Cycle average of tags in use +system.l2c.tags.total_refs 47870421 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1238537 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 38.650780 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36632.144769 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 146.246189 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 202.168712 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4157.667973 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8742.110148 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 28.831722 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 47.900932 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 347.749800 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2205.430231 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 32.408854 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 51.307546 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1406.712197 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3461.981272 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 83.334747 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.itb.walker 114.561611 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2502.338392 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 5155.516141 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.558962 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002232 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003085 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063441 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.133394 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000440 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000731 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.005306 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.033652 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000495 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000783 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.021465 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.052826 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001272 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.itb.walker 0.001748 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.038183 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.078667 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996680 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 263 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62843 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 36522.594911 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 124.677817 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 187.809125 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3696.971873 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 11236.224149 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 38.223238 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 48.365437 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 755.794708 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1969.239780 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 46.667563 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 65.236270 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2038.056565 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2946.228048 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 100.667016 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.itb.walker 147.723446 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 1700.524086 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 3648.504014 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.557291 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001902 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002866 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.056411 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.171451 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000583 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000738 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.011533 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.030048 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000712 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000995 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.031098 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.044956 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001536 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.itb.walker 0.002254 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.025948 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.055672 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995995 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 287 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62870 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 261 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 560 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2808 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5049 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54318 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004013 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.958908 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 420535401 # Number of tag accesses -system.l2c.tags.data_accesses 420535401 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 157367 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 107004 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 58638 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 43521 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 153028 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 59170 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 293557 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 105792 # number of ReadReq hits -system.l2c.ReadReq_hits::total 978077 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 7502187 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 7502187 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 15831215 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 15831215 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3881 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1299 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 1589 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 2641 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9410 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu3.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 649967 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 198078 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 263559 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3.data 467871 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1579475 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 5543628 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 1660025 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 3849796 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 4687305 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 15740754 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 2482832 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 800663 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 1056956 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 1884656 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 6225107 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 284770 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 92927 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu2.data 125862 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu3.data 228099 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 731658 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 157367 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 107004 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 5543628 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3132799 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 58638 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 43521 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 1660025 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 998741 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 153028 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 59170 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 3849796 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 1320515 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.dtb.walker 293557 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.itb.walker 105792 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 4687305 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 2352527 # number of demand (read+write) hits -system.l2c.demand_hits::total 24523413 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 157367 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 107004 # number of overall hits -system.l2c.overall_hits::cpu0.inst 5543628 # number of overall hits -system.l2c.overall_hits::cpu0.data 3132799 # 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number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 415 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 397 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 538 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 468 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.dtb.walker 1108 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.itb.walker 841 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6394 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 14017 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4542 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 5830 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 9491 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 33880 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu3.data 1 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 2465924000 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 834447000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 789828000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3.data 841649000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 2465924000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.006211 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.008928 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003644 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.008707 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003993 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.009296 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.004019 # mshr miss rate for ReadReq accesses +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.790023 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.779716 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.780928 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.461165 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.222222 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.222222 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.217550 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.199771 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.185759 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.117461 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005536 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006188 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.004988 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.003615 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.033886 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.034832 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.034369 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.020182 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.170574 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.189576 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.241330 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.098725 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.006211 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.008928 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005536 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.076961 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003644 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.008707 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006188 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.075228 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003993 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.009296 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.004988 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.069659 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.016871 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.006211 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.008928 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005536 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.076961 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003644 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.008707 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006188 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.075228 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003993 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.009296 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.004988 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.069659 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.016871 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74557.909605 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 73963.709677 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 76368.421053 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 78675.311203 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 79455.433786 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 78664.659639 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 77766.845156 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18911.221122 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19008.516862 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18993.052738 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18979.101746 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 45750 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 45750 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72201.028544 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 72024.542634 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 89442.929077 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80214.990210 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72252.189974 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74754.927536 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 76239.272232 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74958.556091 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74062.168365 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 74773.572716 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 79572.242152 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77048.923506 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18727.928647 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 19459.291299 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 20267.105791 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19827.788654 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74557.909605 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73963.709677 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72252.189974 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72828.309288 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 76368.421053 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 78675.311203 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74754.927536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 72985.645061 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 79455.433786 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 78664.659639 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 76239.272232 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 85708.127253 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 78510.647630 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74557.909605 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73963.709677 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72252.189974 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72828.309288 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 76368.421053 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 78675.311203 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74754.927536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 72985.645061 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 79455.433786 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 78664.659639 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 76239.272232 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 85708.127253 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 78510.647630 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170923.187218 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 166314.592546 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 169927.114880 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169084.201865 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 89696.549500 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 87787.929310 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 85489.994921 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 87614.993782 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 2708332 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1355057 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2739 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.trans_dist::ReadReq 76738 # Transaction distribution -system.membus.trans_dist::ReadResp 445217 # Transaction distribution +system.membus.trans_dist::ReadResp 443894 # Transaction distribution system.membus.trans_dist::WriteReq 33648 # Transaction distribution system.membus.trans_dist::WriteResp 33648 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1070328 # Transaction distribution -system.membus.trans_dist::CleanEvict 202542 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34555 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1089631 # Transaction distribution +system.membus.trans_dist::CleanEvict 200219 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35037 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14337 # Transaction distribution -system.membus.trans_dist::ReadExReq 398389 # Transaction distribution -system.membus.trans_dist::ReadExResp 398389 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 368479 # Transaction distribution -system.membus.trans_dist::InvalidateReq 599634 # Transaction distribution -system.membus.trans_dist::InvalidateResp 450461 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14486 # Transaction distribution +system.membus.trans_dist::ReadExReq 415725 # Transaction distribution +system.membus.trans_dist::ReadExResp 415725 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 367156 # Transaction distribution +system.membus.trans_dist::InvalidateReq 600547 # Transaction distribution +system.membus.trans_dist::InvalidateResp 436040 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6760 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3699064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3828461 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 295887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 295887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4124348 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3729876 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3859270 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 302047 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 302047 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4161317 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155706 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 110365024 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 110534446 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7279360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7279360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 117813806 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2019 # Total snoops (count) -system.membus.snoop_fanout::samples 2784335 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 112629920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 112799278 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7328576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7328576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 120127854 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1179 # Total snoops (count) +system.membus.snoop_fanout::samples 2232317 # Request fanout histogram +system.membus.snoop_fanout::mean 0.015391 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.123101 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2784335 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2197960 98.46% 98.46% # Request fanout histogram +system.membus.snoop_fanout::1 34357 1.54% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2784335 # Request fanout histogram -system.membus.reqLayer0.occupancy 62370000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2232317 # Request fanout histogram +system.membus.reqLayer0.occupancy 46873500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1751500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1706000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 3098674718 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 3219472355 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2309468641 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2319703830 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 28779324 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 28713899 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3221,61 +3212,61 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 51706899 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 26184435 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 3148 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2316 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2316 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 52099554 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 26383185 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3169 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2082 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2082 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 1482882 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23802645 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 1490866 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23977004 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33648 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33648 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 7959053 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 15833779 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2295611 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 43290 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43295 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1978465 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1978465 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 15834389 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6490632 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1273555 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1224699 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47588616 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29285291 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 809621 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1728313 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 79411841 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2026923028 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1022015642 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2929800 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6124520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3057992990 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1664727 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 38155391 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.016407 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.127033 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 8032732 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 15904025 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2315696 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 43839 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43848 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2004412 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2004412 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 15904657 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6582020 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1233125 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1226250 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47799339 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29657154 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 806902 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1734280 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 79997675 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2035912148 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1036024666 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2901928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6114504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3080953246 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1497196 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 38183781 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.016504 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.127404 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 37529389 98.36% 98.36% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 626002 1.64% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 37553594 98.35% 98.35% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 630187 1.65% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 38155391 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 30930822494 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 38183781 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 31295495912 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 835176 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 884168 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 15386050433 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 15602902016 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 7871932216 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 7909503562 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 287489224 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 285711732 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 705270825 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 709709811 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index ad76c447e..d85138b4f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,158 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.284902 # Number of seconds simulated -sim_ticks 51284901790000 # Number of ticks simulated -final_tick 51284901790000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.317219 # Number of seconds simulated +sim_ticks 51317219225000 # Number of ticks simulated +final_tick 51317219225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166610 # Simulator instruction rate (inst/s) -host_op_rate 195762 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9559915430 # Simulator tick rate (ticks/s) -host_mem_usage 696216 # Number of bytes of host memory used -host_seconds 5364.58 # Real time elapsed on the host -sim_insts 893791087 # Number of instructions simulated -sim_ops 1050181412 # Number of ops (including micro ops) simulated +host_inst_rate 190793 # Simulator instruction rate (inst/s) +host_op_rate 224183 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10734613908 # Simulator tick rate (ticks/s) +host_mem_usage 694152 # Number of bytes of host memory used +host_seconds 4780.54 # Real time elapsed on the host +sim_insts 912094204 # Number of instructions simulated +sim_ops 1071714405 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 151616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 131392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3547392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 26803872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 164672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 152640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3783872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 26210856 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 417152 # Number of bytes read from this memory -system.physmem.bytes_read::total 61363464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3547392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3783872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7331264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 79575360 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory -system.physmem.bytes_written::total 79595940 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2369 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2053 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 55428 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 418819 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2573 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2385 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 59123 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 409549 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6518 # Number of read requests responded to by this memory -system.physmem.num_reads::total 958817 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1243365 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1245938 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 69170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 522646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 73781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 511083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1196521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 73781 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 142952 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1551633 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1552035 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1551633 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 522647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 73781 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 511484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2748556 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 958817 # Number of read requests accepted -system.physmem.writeReqs 1245938 # Number of write requests accepted -system.physmem.readBursts 958817 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1245938 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61319744 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 44544 # Total number of bytes read from write queue -system.physmem.bytesWritten 79596352 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61363464 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 79595940 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 696 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2241 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu0.dtb.walker 178240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 158592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3667840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 28126168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 173888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 153280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3614336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 28857840 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory +system.physmem.bytes_read::total 65359176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3667840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3614336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7282176 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 83655232 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory +system.physmem.bytes_written::total 83675812 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2785 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 57310 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 439479 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2717 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56474 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 450909 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1021250 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1307113 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1309686 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3473 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 71474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 548084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 70431 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 562342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1273631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 71474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 70431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 141905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1630159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1630560 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1630159 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3473 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 71474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 548485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 70431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 562342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2904191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1021250 # Number of read requests accepted +system.physmem.writeReqs 1309686 # Number of write requests accepted +system.physmem.readBursts 1021250 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1309686 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 65325376 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 34624 # Total number of bytes read from write queue +system.physmem.bytesWritten 83676352 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 65359176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 83675812 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 541 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2238 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 56014 # Per bank write bursts -system.physmem.perBankRdBursts::1 61765 # Per bank write bursts -system.physmem.perBankRdBursts::2 56852 # Per bank write bursts -system.physmem.perBankRdBursts::3 54266 # Per bank write bursts -system.physmem.perBankRdBursts::4 57300 # Per bank write bursts -system.physmem.perBankRdBursts::5 65586 # Per bank write bursts -system.physmem.perBankRdBursts::6 58254 # Per bank write bursts -system.physmem.perBankRdBursts::7 56988 # Per bank write bursts -system.physmem.perBankRdBursts::8 55394 # Per bank write bursts -system.physmem.perBankRdBursts::9 83577 # Per bank write bursts -system.physmem.perBankRdBursts::10 57993 # Per bank write bursts -system.physmem.perBankRdBursts::11 64464 # Per bank write bursts -system.physmem.perBankRdBursts::12 57098 # Per bank write bursts -system.physmem.perBankRdBursts::13 62288 # Per bank write bursts -system.physmem.perBankRdBursts::14 55335 # Per bank write bursts -system.physmem.perBankRdBursts::15 54947 # Per bank write bursts -system.physmem.perBankWrBursts::0 75753 # Per bank write bursts -system.physmem.perBankWrBursts::1 78600 # Per bank write bursts -system.physmem.perBankWrBursts::2 75987 # Per bank write bursts -system.physmem.perBankWrBursts::3 76409 # Per bank write bursts -system.physmem.perBankWrBursts::4 77268 # Per bank write bursts -system.physmem.perBankWrBursts::5 81844 # Per bank write bursts -system.physmem.perBankWrBursts::6 76609 # Per bank write bursts -system.physmem.perBankWrBursts::7 77405 # Per bank write bursts -system.physmem.perBankWrBursts::8 75535 # Per bank write bursts -system.physmem.perBankWrBursts::9 81820 # Per bank write bursts -system.physmem.perBankWrBursts::10 76863 # Per bank write bursts -system.physmem.perBankWrBursts::11 81595 # Per bank write bursts -system.physmem.perBankWrBursts::12 75866 # Per bank write bursts -system.physmem.perBankWrBursts::13 80975 # Per bank write bursts -system.physmem.perBankWrBursts::14 75599 # Per bank write bursts -system.physmem.perBankWrBursts::15 75565 # Per bank write bursts +system.physmem.perBankRdBursts::0 59538 # Per bank write bursts +system.physmem.perBankRdBursts::1 65186 # Per bank write bursts +system.physmem.perBankRdBursts::2 59192 # Per bank write bursts +system.physmem.perBankRdBursts::3 61503 # Per bank write bursts +system.physmem.perBankRdBursts::4 61968 # Per bank write bursts +system.physmem.perBankRdBursts::5 71297 # Per bank write bursts +system.physmem.perBankRdBursts::6 63621 # Per bank write bursts +system.physmem.perBankRdBursts::7 62505 # Per bank write bursts +system.physmem.perBankRdBursts::8 57971 # Per bank write bursts +system.physmem.perBankRdBursts::9 85989 # Per bank write bursts +system.physmem.perBankRdBursts::10 63150 # Per bank write bursts +system.physmem.perBankRdBursts::11 64998 # Per bank write bursts +system.physmem.perBankRdBursts::12 58754 # Per bank write bursts +system.physmem.perBankRdBursts::13 64690 # Per bank write bursts +system.physmem.perBankRdBursts::14 59967 # Per bank write bursts +system.physmem.perBankRdBursts::15 60380 # Per bank write bursts +system.physmem.perBankWrBursts::0 78521 # Per bank write bursts +system.physmem.perBankWrBursts::1 82873 # Per bank write bursts +system.physmem.perBankWrBursts::2 79926 # Per bank write bursts +system.physmem.perBankWrBursts::3 82832 # Per bank write bursts +system.physmem.perBankWrBursts::4 82609 # Per bank write bursts +system.physmem.perBankWrBursts::5 88110 # Per bank write bursts +system.physmem.perBankWrBursts::6 81518 # Per bank write bursts +system.physmem.perBankWrBursts::7 82656 # Per bank write bursts +system.physmem.perBankWrBursts::8 78895 # Per bank write bursts +system.physmem.perBankWrBursts::9 84228 # Per bank write bursts +system.physmem.perBankWrBursts::10 80757 # Per bank write bursts +system.physmem.perBankWrBursts::11 83094 # Per bank write bursts +system.physmem.perBankWrBursts::12 78112 # Per bank write bursts +system.physmem.perBankWrBursts::13 83897 # Per bank write bursts +system.physmem.perBankWrBursts::14 79365 # Per bank write bursts +system.physmem.perBankWrBursts::15 80050 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 53 # Number of times write queue was full causing retry -system.physmem.totGap 51284900546000 # Total gap between requests +system.physmem.numWrRetry 115 # Number of times write queue was full causing retry +system.physmem.totGap 51317218019000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 958802 # Read request sizes (log2) +system.physmem.readPktSize::6 1021235 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1243365 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 542154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 273293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 94311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 42898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1098 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 325 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1307113 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 561294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 302542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 104557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 481 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -165,216 +162,216 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 53530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 66664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 70454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 71905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 72565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 73989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 82526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 76278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 89703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 76639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 77053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 82881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 72033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 70668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 68023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 139 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 555731 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 253.568320 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 151.645025 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 292.798773 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 244526 44.00% 44.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 138101 24.85% 68.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53162 9.57% 78.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26648 4.80% 83.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 19957 3.59% 86.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11140 2.00% 88.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10224 1.84% 90.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6833 1.23% 91.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 45140 8.12% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 555731 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 64596 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.832281 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 53.413760 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 64590 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7680-8191 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8704-9215 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 64596 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 64596 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.253406 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.362319 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.482686 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 110 0.17% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 65 0.10% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 55177 85.42% 85.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 6740 10.43% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 705 1.09% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 447 0.69% 97.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 541 0.84% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 101 0.16% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 328 0.51% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 148 0.23% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 164 0.25% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 3 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 7 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 4 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 17 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 16 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::328-335 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 64596 # Writes before turning the bus around for reads -system.physmem.totQLat 25254361125 # Total ticks spent queuing -system.physmem.totMemAccLat 43219129875 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4790605000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26358.22 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 21632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 29719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 41729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 50195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 67312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 74771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 78166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 83727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 87147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 84488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 87764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 90437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 82620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 80818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 81373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 72156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 70724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 67158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 296 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 578062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 257.760143 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.645909 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 296.380743 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 251223 43.46% 43.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 144003 24.91% 68.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 55356 9.58% 77.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27668 4.79% 82.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20975 3.63% 86.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11890 2.06% 88.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10828 1.87% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7399 1.28% 91.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 48720 8.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 578062 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61477 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.602941 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 65.801588 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 61469 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 61477 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61477 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.267189 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.511196 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.879627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 57149 92.96% 92.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 2185 3.55% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 1043 1.70% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 635 1.03% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 196 0.32% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 105 0.17% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 30 0.05% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 57 0.09% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 29 0.05% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 5 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 5 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 11 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 7 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-447 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-607 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-639 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-671 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-767 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-895 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-927 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1504-1535 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61477 # Writes before turning the bus around for reads +system.physmem.totQLat 27580144715 # Total ticks spent queuing +system.physmem.totMemAccLat 46718438465 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5103545000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27020.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45108.22 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.20 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 45770.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.63 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.83 # Average write queue length when enqueuing -system.physmem.readRowHits 736278 # Number of row buffer hits during reads -system.physmem.writeRowHits 909804 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.85 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes -system.physmem.avgGap 23261042.86 # Average gap between requests -system.physmem.pageHitRate 74.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2087694000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1139118750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3642795000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4016790000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3349680278880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1234735113780 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29687838385500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34283140175910 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.484113 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49388248138285 # Time in different power states -system.physmem_0.memoryStateTime::REF 1712515480000 # Time in different power states +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.54 # Average write queue length when enqueuing +system.physmem.readRowHits 791160 # Number of row buffer hits during reads +system.physmem.writeRowHits 958928 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.34 # Row buffer hit rate for writes +system.physmem.avgGap 22015713.01 # Average gap between requests +system.physmem.pageHitRate 75.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2219328720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1210943250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3937471200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4270611600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3351790802880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1232390071935 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29709283194000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34305102423585 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.491159 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49423935419086 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713594480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 184135332965 # Time in different power states +system.physmem_0.memoryStateTime::ACT 179688951414 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2113632360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1153271625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3830509800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4042340640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3349680278880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1240634967750 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29682663075000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34284118076055 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.503181 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49379589334828 # Time in different power states -system.physmem_1.memoryStateTime::REF 1712515480000 # Time in different power states +system.physmem_1.actEnergy 2150820000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1173562500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4024012200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4201619040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3351790802880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1230344610120 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29711077467000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34304762893740 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.484542 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49426892036602 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713594480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 192796355672 # Time in different power states +system.physmem_1.memoryStateTime::ACT 176725372148 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 1088 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 1024 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 2148 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 1088 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 1024 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 2112 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 17 # Number of read requests responded to by this memory +system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 2212 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 1408 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 2176 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 21 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.num_reads::cpu1.inst 22 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 20 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 42 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 21 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 20 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 41 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 21 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 27 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 43 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 27 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 42 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 20 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 42 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 27 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 43 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 131701737 # Number of BP lookups -system.cpu0.branchPred.condPredicted 88290011 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5749928 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 88871773 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 60662484 # Number of BTB hits +system.cpu0.branchPred.lookups 133997601 # Number of BP lookups +system.cpu0.branchPred.condPredicted 89911686 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5854244 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 89985465 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 61739918 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 68.258438 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 16943081 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 189225 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4992924 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2589273 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 2403651 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 412581 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 68.610990 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17379215 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 192773 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4943112 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2622279 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 2320833 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 406549 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -405,91 +402,93 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 895264 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 895264 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17123 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90441 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 554296 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 340968 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2750.470719 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 16351.798354 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 338087 99.16% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1498 0.44% 99.59% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 976 0.29% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 136 0.04% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 169 0.05% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 22 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 39 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 36 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 931838 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 931838 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17645 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 95375 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 582006 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 349832 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2584.187553 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 14750.130751 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 347090 99.22% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1907 0.55% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 488 0.14% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 130 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 123 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 40 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 48 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 340968 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 416487 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22961.536615 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18398.217426 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 19575.689133 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 407358 97.81% 97.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6820 1.64% 99.45% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1636 0.39% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 111 0.03% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 329 0.08% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 154 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 63 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 416487 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 342294024144 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.109470 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.721232 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 341240531644 99.69% 99.69% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 582822500 0.17% 99.86% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 199579000 0.06% 99.92% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 117924500 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 46760000 0.01% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 24862000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 28899000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 44321000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 7892500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 388000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 22500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::44-47 11000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::48-51 10500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 342294024144 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 90442 84.08% 84.08% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 17123 15.92% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 107565 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 895264 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 349832 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 445532 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23200.793658 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 19017.924437 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16422.337995 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 338631 76.01% 76.01% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 97435 21.87% 97.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 7291 1.64% 99.51% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 1212 0.27% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 239 0.05% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 222 0.05% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 191 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 178 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 71 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 21 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 12 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 14 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 445532 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 361726794756 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.119484 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.718354 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 360638415756 99.70% 99.70% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 594419500 0.16% 99.86% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 206814500 0.06% 99.92% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 128366500 0.04% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 51460000 0.01% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 27618000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 28344500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 44148500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 6546000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 549000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 65000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::44-47 32000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::48-51 15500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 361726794756 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 95376 84.39% 84.39% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 17645 15.61% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 113021 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 931838 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 895264 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107565 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 931838 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 113021 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107565 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 1002829 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 113021 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 1044859 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 104837372 # DTB read hits -system.cpu0.dtb.read_misses 616098 # DTB read misses -system.cpu0.dtb.write_hits 80671443 # DTB write hits -system.cpu0.dtb.write_misses 279166 # DTB write misses -system.cpu0.dtb.flush_tlb 1102 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 105631864 # DTB read hits +system.cpu0.dtb.read_misses 640489 # DTB read misses +system.cpu0.dtb.write_hits 81680668 # DTB write hits +system.cpu0.dtb.write_misses 291349 # DTB write misses +system.cpu0.dtb.flush_tlb 1081 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21868 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 546 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 55634 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 233 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9003 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 22090 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 55450 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 172 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9899 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 56722 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 105453470 # DTB read accesses -system.cpu0.dtb.write_accesses 80950609 # DTB write accesses +system.cpu0.dtb.perms_faults 56099 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 106272353 # DTB read accesses +system.cpu0.dtb.write_accesses 81972017 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 185508815 # DTB hits -system.cpu0.dtb.misses 895264 # DTB misses -system.cpu0.dtb.accesses 186404079 # DTB accesses +system.cpu0.dtb.hits 187312532 # DTB hits +system.cpu0.dtb.misses 931838 # DTB misses +system.cpu0.dtb.accesses 188244370 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -519,838 +518,837 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 102402 # Table walker walks requested -system.cpu0.itb.walker.walksLong 102402 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3079 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69849 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 14173 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 88229 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1559.917941 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 11109.318329 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 87313 98.96% 98.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 469 0.53% 99.49% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 83 0.09% 99.59% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 147 0.17% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 141 0.16% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 43 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 17 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 88229 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 87101 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 28953.462073 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24215.206372 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 22576.849397 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 85266 97.89% 97.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 483 0.55% 98.45% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1148 1.32% 99.77% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 69 0.08% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 97 0.11% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 24 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 11 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 102509 # Table walker walks requested +system.cpu0.itb.walker.walksLong 102509 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2958 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69563 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 14385 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 88124 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1419.845899 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 9093.034945 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 87142 98.89% 98.89% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 616 0.70% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 206 0.23% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 105 0.12% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 24 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 11 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 88124 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 86906 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 28693.715048 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24359.274514 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 18506.887432 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 84671 97.43% 97.43% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1946 2.24% 99.67% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 187 0.22% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 65 0.07% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 20 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 87101 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 630054255476 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.901585 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.298241 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 62069607016 9.85% 9.85% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 567926877960 90.14% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 53229500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 3926000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 600500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 14500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 630054255476 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 69849 95.78% 95.78% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 3079 4.22% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 72928 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 86906 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 610832410424 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.899859 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.300566 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 61230050100 10.02% 10.02% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 549548390324 89.97% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 48170500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 4945000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 599000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 205000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 50500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 610832410424 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 69563 95.92% 95.92% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2958 4.08% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 72521 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102402 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102402 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102509 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102509 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72928 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72928 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 175330 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 93547159 # ITB inst hits -system.cpu0.itb.inst_misses 102402 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72521 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72521 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 175030 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 94735666 # ITB inst hits +system.cpu0.itb.inst_misses 102509 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1102 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1081 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21868 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 546 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 41100 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 22090 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 40899 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 189115 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 193621 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 93649561 # ITB inst accesses -system.cpu0.itb.hits 93547159 # DTB hits -system.cpu0.itb.misses 102402 # DTB misses -system.cpu0.itb.accesses 93649561 # DTB accesses -system.cpu0.numCycles 688011025 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 94838175 # ITB inst accesses +system.cpu0.itb.hits 94735666 # DTB hits +system.cpu0.itb.misses 102509 # DTB misses +system.cpu0.itb.accesses 94838175 # DTB accesses +system.cpu0.numCycles 677363519 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 243601869 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 585571838 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 131701737 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 80194838 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 401370000 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13146214 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2578790 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 20091 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 3656 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 4829637 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 164032 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 3268 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 93342305 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3584098 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 39018 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 659144176 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.038197 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.295091 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 248081332 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 593905796 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 133997601 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81741412 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 389608891 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13373506 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2523552 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 22024 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 2940 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 4870394 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 168493 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 2299 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 94525599 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3651769 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 39552 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 651966408 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.065387 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.317537 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 515420904 78.20% 78.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 17940395 2.72% 80.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 18023461 2.73% 83.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13220348 2.01% 85.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 27959766 4.24% 89.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 8806264 1.34% 91.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9588960 1.45% 92.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8203319 1.24% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 39980759 6.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 506080688 77.62% 77.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18214646 2.79% 80.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18100947 2.78% 83.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13291875 2.04% 85.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 28751599 4.41% 89.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 8986592 1.38% 91.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9770458 1.50% 92.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8414345 1.29% 93.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 40355258 6.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 659144176 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.191424 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.851108 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 197499187 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 338466010 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 104398182 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13546805 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5231982 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19379138 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1360316 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 638255296 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4185441 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5231982 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 205063449 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 27153307 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 262923483 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 110249317 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 48520379 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 622996110 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 132355 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2247994 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1861879 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 28960972 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 3803 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 595426650 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 956549851 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 734166245 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 794435 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 500270864 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 95155781 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15187791 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13237681 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 75403173 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 100496845 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 84720468 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13599194 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14388955 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 590484103 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15298411 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 591681421 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 857551 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 80930976 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 50447616 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 351888 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 659144176 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.897651 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.636567 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 651966408 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.197822 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.876790 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 201025214 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 326077447 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 105614620 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13934386 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5312657 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19632987 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1393622 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 647334053 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4303710 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5312657 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 208746840 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 23221789 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 263564774 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 111697152 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 39420825 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 631864038 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 81982 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1845422 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1714455 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 19477575 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 3876 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 604366839 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 973584661 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 745191594 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 824988 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 507520310 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 96846524 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15772416 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13809695 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 77902092 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 101804436 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 85844339 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13951597 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14791131 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 598600479 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15906116 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 599443694 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 871420 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 82277994 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 51785989 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 367722 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 651966408 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.919440 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.646692 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 427475761 64.85% 64.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 97836885 14.84% 79.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 42770645 6.49% 86.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 30584958 4.64% 90.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 22743510 3.45% 94.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 15987914 2.43% 96.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 10968411 1.66% 98.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6384440 0.97% 99.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4391652 0.67% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 416000229 63.81% 63.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 100627614 15.43% 79.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43369864 6.65% 85.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 31012057 4.76% 90.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 22935032 3.52% 94.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 16054599 2.46% 96.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 11112799 1.70% 98.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6483448 0.99% 99.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4370766 0.67% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 659144176 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 651966408 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 2986555 25.26% 25.26% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 23747 0.20% 25.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 2157 0.02% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4879643 41.27% 66.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3932744 33.26% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 3017859 25.71% 25.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 24275 0.21% 25.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 3125 0.03% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4815194 41.03% 66.98% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3875781 33.02% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 139 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 401347935 67.83% 67.83% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1444621 0.24% 68.08% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 64829 0.01% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 116 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 56174 0.01% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 107054227 18.09% 86.19% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 81713380 13.81% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 50 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 407248355 67.94% 67.94% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1425936 0.24% 68.18% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 67925 0.01% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 173 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 60970 0.01% 68.20% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.20% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.20% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.20% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 107889592 18.00% 86.20% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82750693 13.80% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 591681421 # Type of FU issued -system.cpu0.iq.rate 0.859988 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11824846 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019985 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1854198838 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 686917057 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 569115204 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 990577 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 508872 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 439153 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 602977632 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 528496 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4632250 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 599443694 # Type of FU issued +system.cpu0.iq.rate 0.884966 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11736234 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019579 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1862428500 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 696963642 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 577071065 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1032950 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 531195 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 457217 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 610628639 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 551239 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4761086 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 16643333 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 19794 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 724475 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 8465055 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 16972106 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 20586 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 721660 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 8682994 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 3918685 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 8300346 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 4003221 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 7891299 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5231982 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15925349 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 9030114 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 605926435 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1719706 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 100496845 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 84720468 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 12946615 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 222991 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 8727203 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 724475 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2456659 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2686981 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5143640 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 584799722 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 104827609 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 5998636 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5312657 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14923194 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 6733387 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 614655210 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1737208 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 101804436 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 85844339 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13513919 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 247440 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6392978 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 721660 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2504975 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2708374 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5213349 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 592463883 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 105622287 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 6061529 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 143921 # number of nop insts executed -system.cpu0.iew.exec_refs 185499348 # number of memory reference insts executed -system.cpu0.iew.exec_branches 108059724 # Number of branches executed -system.cpu0.iew.exec_stores 80671739 # Number of stores executed -system.cpu0.iew.exec_rate 0.849986 # Inst execution rate -system.cpu0.iew.wb_sent 570956210 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 569554357 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 281415896 # num instructions producing a value -system.cpu0.iew.wb_consumers 488383708 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.827827 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.576219 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 80977867 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 14946523 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4408529 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 645374166 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.813252 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.811592 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 148615 # number of nop insts executed +system.cpu0.iew.exec_refs 187306165 # number of memory reference insts executed +system.cpu0.iew.exec_branches 109885900 # Number of branches executed +system.cpu0.iew.exec_stores 81683878 # Number of stores executed +system.cpu0.iew.exec_rate 0.874662 # Inst execution rate +system.cpu0.iew.wb_sent 578962486 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 577528282 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 284712169 # num instructions producing a value +system.cpu0.iew.wb_consumers 495210168 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.852612 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.574932 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 82335465 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15538394 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4479878 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 637982242 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.834237 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.825466 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 452622252 70.13% 70.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 95504432 14.80% 84.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 32341034 5.01% 89.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 15221107 2.36% 92.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10764054 1.67% 93.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6526900 1.01% 94.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6016149 0.93% 95.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3811802 0.59% 96.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22566436 3.50% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 441101470 69.14% 69.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 98311443 15.41% 84.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 33085662 5.19% 89.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15424273 2.42% 92.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10896564 1.71% 93.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6486229 1.02% 94.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6026213 0.94% 95.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3904773 0.61% 96.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 22745615 3.57% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 645374166 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 446835848 # Number of instructions committed -system.cpu0.commit.committedOps 524851533 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 637982242 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 452758888 # Number of instructions committed +system.cpu0.commit.committedOps 532228596 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 160108924 # Number of memory references committed -system.cpu0.commit.loads 83853511 # Number of loads committed -system.cpu0.commit.membars 3685792 # Number of memory barriers committed -system.cpu0.commit.branches 99662639 # Number of branches committed -system.cpu0.commit.fp_insts 420768 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 481718978 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13112301 # Number of function calls committed. +system.cpu0.commit.refs 161993674 # Number of memory references committed +system.cpu0.commit.loads 84832329 # Number of loads committed +system.cpu0.commit.membars 3784982 # Number of memory barriers committed +system.cpu0.commit.branches 101373358 # Number of branches committed +system.cpu0.commit.fp_insts 437523 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 488401874 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13443378 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 363528180 69.26% 69.26% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1118140 0.21% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 48609 0.01% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 47680 0.01% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 83853511 15.98% 85.47% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 76255413 14.53% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 369014830 69.33% 69.33% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1117216 0.21% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 51029 0.01% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 51847 0.01% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 84832329 15.94% 85.50% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 77161345 14.50% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 524851533 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22566436 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1224636916 # The number of ROB reads -system.cpu0.rob.rob_writes 1225450764 # The number of ROB writes -system.cpu0.timesIdled 4112135 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 28866849 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 54222947414 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 446835848 # Number of Instructions Simulated -system.cpu0.committedOps 524851533 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.539740 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.539740 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.649460 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.649460 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 688252111 # number of integer regfile reads -system.cpu0.int_regfile_writes 407094655 # number of integer regfile writes -system.cpu0.fp_regfile_reads 800302 # number of floating regfile reads -system.cpu0.fp_regfile_writes 473448 # number of floating regfile writes -system.cpu0.cc_regfile_reads 125192637 # number of cc regfile reads -system.cpu0.cc_regfile_writes 126303504 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1203085849 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15043668 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 10538852 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.973177 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 302937432 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10539364 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.743426 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 2695088500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 218.644895 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 293.328283 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.427041 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.572907 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999948 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 532228596 # Class of committed instruction +system.cpu0.commit.bw_lim_events 22745615 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1225734406 # The number of ROB reads +system.cpu0.rob.rob_writes 1243135976 # The number of ROB writes +system.cpu0.timesIdled 4186507 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25397111 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 54288384692 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 452758888 # Number of Instructions Simulated +system.cpu0.committedOps 532228596 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.496080 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.496080 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.668413 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.668413 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 697890382 # number of integer regfile reads +system.cpu0.int_regfile_writes 412518994 # number of integer regfile writes +system.cpu0.fp_regfile_reads 828341 # number of floating regfile reads +system.cpu0.fp_regfile_writes 487008 # number of floating regfile writes +system.cpu0.cc_regfile_reads 127089396 # number of cc regfile reads +system.cpu0.cc_regfile_writes 128258211 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1206144502 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15679564 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 10794532 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.983410 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 308661870 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10795044 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.592924 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1667914500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 302.186929 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 209.796481 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.590209 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.409759 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1336210971 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1336210971 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 79968247 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 80371614 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 160339861 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67069375 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 67205589 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 134274964 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199346 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 203477 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 402823 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 140986 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 183532 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 324518 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1741209 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1760714 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3501923 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2021774 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2019563 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4041337 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 147178608 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 147760735 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 294939343 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 147377954 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 147964212 # number of overall hits -system.cpu0.dcache.overall_hits::total 295342166 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6393063 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 6235592 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 12628655 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6405631 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 6317446 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 12723077 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 674803 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 616721 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1291524 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 612571 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 626179 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1238750 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 334024 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 316429 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 650453 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 1362392595 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1362392595 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 80965730 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 82351460 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 163317190 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67604275 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 69208699 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 136812974 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 205804 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202560 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 408364 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 173367 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 153044 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 326411 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1817125 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1785316 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3602441 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2093741 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2052340 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 4146081 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 148743372 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 151713203 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 300456575 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 148949176 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 151915763 # number of overall hits +system.cpu0.dcache.overall_hits::total 300864939 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6366558 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 6514512 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 12881070 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 6631964 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 6534144 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 13166108 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 653449 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 684365 # 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average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25431.474915 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25407.887793 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24224.498480 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24216.500328 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24220.496163 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 50251301 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 54501 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3623821 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 1019 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.866938 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 53.484789 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 8249196 # number of writebacks +system.cpu0.dcache.writebacks::total 8249196 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3454316 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3599973 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 7054289 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5516594 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5434587 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 10951181 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 3628 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data 3364 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 6992 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 204992 # 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number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 252737 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 7 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4541427 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 4529226 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 9070653 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5200720 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 5137345 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 10338065 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16852 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 139976221754 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 138284454293 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 278260676047 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3092079500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3139092000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6231171500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3092079500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3139092000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6231171500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033016 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032774 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032895 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014709 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014531 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014620 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.754211 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.741430 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.748024 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.808618 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.768735 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787960 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060879 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058477 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059678 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4673731 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 4602629 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 9276360 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5318127 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 5271545 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 10589672 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17867 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15813 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33680 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18974 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14723 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 36841 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 30536 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67377 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45309693000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 45038920000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 90348613000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 40408833272 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 40500038516 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 80908871788 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10386373000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12065937500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 22452310500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 14266559663 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 12400788300 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26667347963 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1747255500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1706730500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3453986000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 76000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 231000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 307000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99985085935 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 97939746816 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 197924832751 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 110371458935 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 110005684316 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 220377143251 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3393465500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2870779500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6264245000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3393465500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2870779500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6264245000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033347 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032797 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033069 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015025 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014517 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014768 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.749949 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.754197 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752107 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.784969 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.790040 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787378 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059303 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059305 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059304 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000003 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028280 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028142 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028211 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032210 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.031759 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031984 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17440.928372 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17553.568824 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17497.120977 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47241.114431 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47759.959237 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47499.037457 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21214.691344 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18477.571002 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19901.389209 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 41362.237585 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 42090.985634 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 41730.490538 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14340.927979 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14896.880609 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14613.437986 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 51642.857143 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12714.285714 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 32178.571429 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27742.276658 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 28050.685104 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27896.273460 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26914.777522 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26917.494210 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26916.127539 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183484.423214 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186561.987400 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185022.017341 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95056.088413 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 90087.300904 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92486.292932 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 16323462 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.933155 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 169414196 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 16323974 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.378245 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 19400599500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 237.111231 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 274.821924 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.463108 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.536762 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028781 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.027835 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028304 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032576 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.031710 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032139 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15558.354354 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15453.188309 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15505.750602 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36229.083866 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36833.050507 # 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Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 203303412 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 203303412 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 84627850 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 84786346 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 169414196 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 84627850 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 84786346 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 169414196 # 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number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 93329321 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 93649766 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 186979087 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 93329321 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 93649766 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 186979087 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.093234 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.094644 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.093940 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.093234 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.094644 # 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average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13578.588777 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13507.007541 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 128531 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 206602499 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 206602499 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 85625549 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 86769133 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 172394682 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 85625549 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 86769133 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 172394682 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 85625549 # 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miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.094035 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.092475 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.093251 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13129.107611 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13168.829969 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13148.917263 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13129.107611 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13168.829969 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13148.917263 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13129.107611 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13168.829969 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13148.917263 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 88437 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 8539 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 7555 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.052231 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11.705758 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 16323462 # number of writebacks -system.cpu0.icache.writebacks::total 16323462 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 613191 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 627375 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 1240566 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 613191 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 627375 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 1240566 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 613191 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 627375 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 1240566 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8088280 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8236045 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 16324325 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 8088280 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 8236045 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 16324325 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 8088280 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 8236045 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 16324325 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 12957 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 7688 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 20645 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 12957 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 7688 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 20645 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103270633406 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 106205385876 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 209476019282 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103270633406 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 106205385876 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 209476019282 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103270633406 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 106205385876 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 209476019282 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1654613000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 981709000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2636322000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1654613000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 981709000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 2636322000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086664 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.087945 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087306 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086664 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.087945 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.087306 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086664 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.087945 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.087306 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12767.935013 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12895.192520 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12832.139723 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12767.935013 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12895.192520 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12832.139723 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12767.935013 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12895.192520 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12832.139723 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127700.316431 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127693.678460 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127697.844514 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127700.316431 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127693.678460 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127697.844514 # average overall mshr uncacheable latency -system.cpu1.branchPred.lookups 132207984 # Number of BP lookups -system.cpu1.branchPred.condPredicted 88587172 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5826495 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 89257950 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 60608223 # Number of BTB hits +system.cpu0.icache.writebacks::writebacks 16477862 # number of writebacks +system.cpu0.icache.writebacks::total 16477862 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 628355 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 622192 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 1250547 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 628355 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 622192 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 1250547 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 628355 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 622192 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 1250547 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8259234 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8219401 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 16478635 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 8259234 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 8219401 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 16478635 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 8259234 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 8219401 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 16478635 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 12438 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 8200 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 20638 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 12438 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 8200 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 20638 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103445364915 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 103197184413 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 206642549328 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103445364915 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 103197184413 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 206642549328 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103445364915 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 103197184413 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 206642549328 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 974276500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 641521000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1615797500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 974276500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 641521000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1615797500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087387 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085967 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086673 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087387 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085967 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.086673 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087387 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085967 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.086673 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12524.813429 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12555.316916 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12540.028305 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12524.813429 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12555.316916 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12540.028305 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12524.813429 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12555.316916 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12540.028305 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 78292.349065 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 78292.349065 # average overall mshr uncacheable latency +system.cpu1.branchPred.lookups 135004521 # Number of BP lookups +system.cpu1.branchPred.condPredicted 90686520 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5841333 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 91602372 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 61971036 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 67.902325 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17136106 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 189382 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 4973679 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2647071 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 2326608 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 405619 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 67.652218 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17264827 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 189835 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 5144550 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2721808 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 2422742 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 415682 # Number of mispredicted indirect branches. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1380,94 +1378,98 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 905143 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 905143 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17108 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91252 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 560527 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 344616 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2714.976960 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 16407.674532 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 341711 99.16% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1475 0.43% 99.59% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 1008 0.29% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 155 0.04% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 168 0.05% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 28 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 24 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 38 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::655360-720895 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 344616 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 422123 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23405.519244 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18788.136881 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 20434.088485 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 412646 97.75% 97.75% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 6891 1.63% 99.39% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1818 0.43% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 156 0.04% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 358 0.08% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 124 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 77 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 40 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::786432-851967 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 422123 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 367737970920 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.152186 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.727251 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 366665366920 99.71% 99.71% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 581252000 0.16% 99.87% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 209708000 0.06% 99.92% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 124789500 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 48258000 0.01% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 27968500 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 30956000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 41073500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 7796500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 589000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 122000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::44-47 17500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::48-51 21000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::52-55 3000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::56-59 5000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::60-63 44500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 367737970920 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 91252 84.21% 84.21% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17108 15.79% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 108360 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 905143 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 920636 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 920636 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17624 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92524 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 572462 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 348174 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2542.994307 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 15098.255497 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 345444 99.22% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1949 0.56% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 425 0.12% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 137 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 118 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 24 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 58 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::720896-786431 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 348174 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 432733 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23053.791830 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18897.650182 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16323.118118 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 333564 77.08% 77.08% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 89713 20.73% 97.81% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 7384 1.71% 99.52% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 1176 0.27% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 238 0.05% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 198 0.05% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 173 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 170 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 52 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 12 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 27 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 432733 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 314249886000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.018496 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.687233 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 313186458000 99.66% 99.66% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 582171000 0.19% 99.85% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 205657500 0.07% 99.91% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 123171000 0.04% 99.95% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 50673000 0.02% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 26248000 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 27458500 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 40663500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 6954500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 344500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 34000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 16000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 30000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::52-55 4000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::56-59 2500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 314249886000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 92524 84.00% 84.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17624 16.00% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 110148 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 920636 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 905143 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 108360 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 920636 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 110148 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 108360 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 1013503 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 110148 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 1030784 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 104254499 # DTB read hits -system.cpu1.dtb.read_misses 630275 # DTB read misses -system.cpu1.dtb.write_hits 80849259 # DTB write hits -system.cpu1.dtb.write_misses 274868 # DTB write misses -system.cpu1.dtb.flush_tlb 1096 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 107706385 # DTB read hits +system.cpu1.dtb.read_misses 633869 # DTB read misses +system.cpu1.dtb.write_hits 83022369 # DTB write hits +system.cpu1.dtb.write_misses 286767 # DTB write misses +system.cpu1.dtb.flush_tlb 1089 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 20902 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 515 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 53828 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 197 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 9278 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 21973 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 55426 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 199 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 9714 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 53866 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 104884774 # DTB read accesses -system.cpu1.dtb.write_accesses 81124127 # DTB write accesses +system.cpu1.dtb.perms_faults 57000 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 108340254 # DTB read accesses +system.cpu1.dtb.write_accesses 83309136 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 185103758 # DTB hits -system.cpu1.dtb.misses 905143 # DTB misses -system.cpu1.dtb.accesses 186008901 # DTB accesses +system.cpu1.dtb.hits 190728754 # DTB hits +system.cpu1.dtb.misses 920636 # DTB misses +system.cpu1.dtb.accesses 191649390 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1497,387 +1499,389 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 101154 # Table walker walks requested -system.cpu1.itb.walker.walksLong 101154 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3005 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 68686 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 14200 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 86954 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1608.292890 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 11331.097997 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 85986 98.89% 98.89% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 520 0.60% 99.48% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 66 0.08% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 164 0.19% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 145 0.17% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 40 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 11 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 101988 # Table walker walks requested +system.cpu1.itb.walker.walksLong 101988 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3087 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 69367 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14377 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 87611 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1414.069010 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8744.624659 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 86637 98.89% 98.89% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 608 0.69% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 209 0.24% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 111 0.13% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 21 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 11 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 86954 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 85891 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 29748.012015 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24412.003991 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 25999.467191 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 83578 97.31% 97.31% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 495 0.58% 97.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1521 1.77% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 97 0.11% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 134 0.16% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 37 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 24 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 85891 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 612540191292 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.893340 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.309134 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 65404482540 10.68% 10.68% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 547076306252 89.31% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 50127000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 7455500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 1506000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 91500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::6 196000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::7 26500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 612540191292 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 68686 95.81% 95.81% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 3005 4.19% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 71691 # Table walker page sizes translated +system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 87611 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 86831 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28749.490389 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24437.163786 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18363.738628 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 45615 52.53% 52.53% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 39084 45.01% 97.54% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 938 1.08% 98.62% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 923 1.06% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 93 0.11% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 90 0.10% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 33 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 11 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 11 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 86831 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 606307709128 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.900370 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.299888 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 60468146000 9.97% 9.97% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 545785217128 90.02% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 47888000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 5793500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 658000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 6500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 606307709128 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 69367 95.74% 95.74% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 3087 4.26% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 72454 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101154 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101154 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101988 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101988 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71691 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71691 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 172845 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 93866720 # ITB inst hits -system.cpu1.itb.inst_misses 101154 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72454 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72454 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 174442 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 95828100 # ITB inst hits +system.cpu1.itb.inst_misses 101988 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1096 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1089 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 20902 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 515 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 39904 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21973 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 40809 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 187991 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 188352 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 93967874 # ITB inst accesses -system.cpu1.itb.hits 93866720 # DTB hits -system.cpu1.itb.misses 101154 # DTB misses -system.cpu1.itb.accesses 93967874 # DTB accesses -system.cpu1.numCycles 688149644 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 95930088 # ITB inst accesses +system.cpu1.itb.hits 95828100 # DTB hits +system.cpu1.itb.misses 101988 # DTB misses +system.cpu1.itb.accesses 95930088 # DTB accesses +system.cpu1.numCycles 668684774 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 246774526 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 586387121 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 132207984 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 80391400 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 398002232 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13247809 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2526813 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 23208 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 3339 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 4746787 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 172822 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 4142 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 93657492 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3619612 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 39280 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 658877500 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.040777 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.297556 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 248375133 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 600185967 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 135004521 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 81957671 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 381222161 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13317970 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2536848 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 21164 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2785 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 4727264 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 160612 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 2602 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 95618947 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3633834 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 39185 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 643707284 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.089618 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.340143 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 514943270 78.15% 78.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 17992448 2.73% 80.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 17938734 2.72% 83.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13188969 2.00% 85.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 27941093 4.24% 89.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 8949077 1.36% 91.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9653002 1.47% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8287474 1.26% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 39983433 6.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 496523035 77.13% 77.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 18305041 2.84% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 18509005 2.88% 82.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13552167 2.11% 84.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 28450532 4.42% 89.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 9097899 1.41% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9820940 1.53% 92.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8391092 1.30% 93.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 41057573 6.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 658877500 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.192121 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.852122 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 200321379 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 334897766 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 105062974 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 13347316 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5245962 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19411078 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1397694 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 639286066 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4311897 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5245962 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 207822387 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 28109229 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 259552504 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 110777742 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 47367249 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 624073748 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 113090 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1957012 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1963484 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 28046902 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 3748 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 596057640 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 957465344 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 735885626 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 888832 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 500042308 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 96015332 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 14940728 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 12988345 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 74317967 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 100818071 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 84975729 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13584844 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14513721 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 591824868 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15016632 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 591532545 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 864332 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 81511621 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 51286616 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 358770 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 658877500 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.897788 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.636922 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 643707284 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.201896 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.897562 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 201561818 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 315815468 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 107257676 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13770315 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5299898 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 19801436 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1379430 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 654914208 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4252969 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5299898 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 209252042 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 22880216 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 253975050 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 113199216 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 39098550 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 639470628 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 86957 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 2174171 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1609351 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 19507965 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3945 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 611072160 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 980685418 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 753664877 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 843607 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 514110066 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 96962094 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15327241 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13321250 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 76568402 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 103346770 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 87233341 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13784187 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14730689 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 606543686 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15379714 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 607376538 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 875474 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 82437591 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 51624950 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 357944 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 643707284 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.943560 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.668311 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 427630752 64.90% 64.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 97159571 14.75% 79.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 42910564 6.51% 86.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 30776221 4.67% 90.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 22686133 3.44% 94.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 15935700 2.42% 96.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 10990898 1.67% 98.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6446525 0.98% 99.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4341136 0.66% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 406849245 63.20% 63.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 99415625 15.44% 78.65% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 43745607 6.80% 85.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 31472621 4.89% 90.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 23315391 3.62% 93.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 16399031 2.55% 96.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 11324350 1.76% 98.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6634295 1.03% 99.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4551119 0.71% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 658877500 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 643707284 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2999770 25.98% 25.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 25009 0.22% 26.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 3249 0.03% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4684166 40.56% 66.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3835188 33.21% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3079713 25.38% 25.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 23466 0.19% 25.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 2047 0.02% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4953216 40.82% 66.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 4075474 33.59% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 401605558 67.89% 67.89% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1412010 0.24% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 67658 0.01% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 191 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 72305 0.01% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 106483903 18.00% 86.16% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 81890872 13.84% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 65 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 411722588 67.79% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1463458 0.24% 68.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 65529 0.01% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 206 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 66963 0.01% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 109966089 18.11% 86.15% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 84091577 13.85% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 591532545 # Type of FU issued -system.cpu1.iq.rate 0.859599 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 11547382 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019521 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1853248239 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 688458824 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 569767413 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1106065 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 569050 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 490960 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 602490208 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 589717 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4719123 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 607376538 # Type of FU issued +system.cpu1.iq.rate 0.908315 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 12133916 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019978 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1870398622 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 704521244 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 584421121 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1071128 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 544645 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 476254 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 618939378 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 571011 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4788717 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 16759885 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 20137 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 685641 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 8616382 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 16961682 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 19758 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 716289 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 8689454 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3886436 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 7425204 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 3983377 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 8390309 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5245962 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 16637308 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 9398313 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 606988228 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1717377 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 100818071 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 84975729 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12705052 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 239734 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 9069380 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 685641 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2485685 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2694157 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 5179842 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 584642052 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 104243442 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 5998727 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5299898 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14473954 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 6659801 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 622069689 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1729386 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 103346770 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 87233341 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13033934 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 237234 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6338314 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 716289 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2501247 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2722291 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 5223538 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 600362187 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 107695161 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6106837 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 146728 # number of nop insts executed -system.cpu1.iew.exec_refs 185095226 # number of memory reference insts executed -system.cpu1.iew.exec_branches 108396618 # Number of branches executed -system.cpu1.iew.exec_stores 80851784 # Number of stores executed -system.cpu1.iew.exec_rate 0.849586 # Inst execution rate -system.cpu1.iew.wb_sent 571674985 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 570258373 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 281283764 # num instructions producing a value -system.cpu1.iew.wb_consumers 489058083 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.828684 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.575154 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 81573069 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14657862 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4448279 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 645042111 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.814412 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.812297 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 146289 # number of nop insts executed +system.cpu1.iew.exec_refs 190717674 # number of memory reference insts executed +system.cpu1.iew.exec_branches 110987821 # Number of branches executed +system.cpu1.iew.exec_stores 83022513 # Number of stores executed +system.cpu1.iew.exec_rate 0.897825 # Inst execution rate +system.cpu1.iew.wb_sent 586317808 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 584897375 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 289057464 # num instructions producing a value +system.cpu1.iew.wb_consumers 502211172 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.874698 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.575570 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 82490328 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15021770 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4481976 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 629716363 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.856712 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.853018 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 452426770 70.14% 70.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 94787874 14.69% 84.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 32819397 5.09% 89.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15329214 2.38% 92.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10832611 1.68% 93.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6451723 1.00% 94.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5988175 0.93% 95.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3853316 0.60% 96.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 22553031 3.50% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 432763054 68.72% 68.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 96847267 15.38% 84.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 33152549 5.26% 89.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15677479 2.49% 91.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11079326 1.76% 93.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6740057 1.07% 94.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 6209892 0.99% 95.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3949846 0.63% 96.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 23296893 3.70% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 645042111 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 446955239 # Number of instructions committed -system.cpu1.commit.committedOps 525329879 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 629716363 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 459335316 # Number of instructions committed +system.cpu1.commit.committedOps 539485809 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 160417533 # Number of memory references committed -system.cpu1.commit.loads 84058186 # Number of loads committed -system.cpu1.commit.membars 3661350 # Number of memory barriers committed -system.cpu1.commit.branches 99963573 # Number of branches committed -system.cpu1.commit.fp_insts 470740 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 482339888 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13268232 # Number of function calls committed. +system.cpu1.commit.refs 164928975 # Number of memory references committed +system.cpu1.commit.loads 86385088 # Number of loads committed +system.cpu1.commit.membars 3716704 # Number of memory barriers committed +system.cpu1.commit.branches 102438773 # Number of branches committed +system.cpu1.commit.fp_insts 458507 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 495134645 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13388221 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 363697714 69.23% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1101230 0.21% 69.44% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 50710 0.01% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 62650 0.01% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 84058186 16.00% 85.46% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 76359347 14.54% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 373316618 69.20% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1132929 0.21% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 49236 0.01% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 58009 0.01% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 86385088 16.01% 85.44% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 78543887 14.56% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 525329879 # Class of committed instruction -system.cpu1.commit.bw_lim_events 22553031 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1225507013 # The number of ROB reads -system.cpu1.rob.rob_writes 1227667180 # The number of ROB writes -system.cpu1.timesIdled 4198522 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 29272144 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 46970319294 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 446955239 # Number of Instructions Simulated -system.cpu1.committedOps 525329879 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.539639 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.539639 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.649503 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.649503 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 688608688 # number of integer regfile reads -system.cpu1.int_regfile_writes 407764370 # number of integer regfile writes -system.cpu1.fp_regfile_reads 881042 # number of floating regfile reads -system.cpu1.fp_regfile_writes 529972 # number of floating regfile writes -system.cpu1.cc_regfile_reads 124702473 # number of cc regfile reads -system.cpu1.cc_regfile_writes 125859602 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1202737772 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14790646 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40305 # Transaction distribution -system.iobus.trans_dist::ReadResp 40305 # Transaction distribution +system.cpu1.commit.op_class_0::total 539485809 # Class of committed instruction +system.cpu1.commit.bw_lim_events 23296893 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1224452307 # The number of ROB reads +system.cpu1.rob.rob_writes 1257969342 # The number of ROB writes +system.cpu1.timesIdled 4181395 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 24977490 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 46999639814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 459335316 # Number of Instructions Simulated +system.cpu1.committedOps 539485809 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.455766 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.455766 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.686924 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.686924 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 706650375 # number of integer regfile reads +system.cpu1.int_regfile_writes 418043743 # number of integer regfile writes +system.cpu1.fp_regfile_reads 853513 # number of floating regfile reads +system.cpu1.fp_regfile_writes 519324 # number of floating regfile writes +system.cpu1.cc_regfile_reads 128705619 # number of cc regfile reads +system.cpu1.cc_regfile_writes 129852515 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1200738028 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15156718 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40297 # Transaction distribution +system.iobus.trans_dist::ReadResp 40297 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1894,11 +1898,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230968 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353752 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1913,16 +1917,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 47810500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 47815500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 348000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 346000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1932,7 +1936,7 @@ system.iobus.reqLayer10.occupancy 10000 # La system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) @@ -1940,73 +1944,73 @@ system.iobus.reqLayer16.occupancy 14500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25726500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25701500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 40136500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 40146500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 566999378 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568673363 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147728000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147712000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115465 # number of replacements -system.iocache.tags.tagsinuse 10.419655 # Cycle average of tags in use +system.iocache.tags.replacements 115457 # number of replacements +system.iocache.tags.tagsinuse 10.425589 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13096612113000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.546608 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.873047 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221663 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429565 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651228 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13089213782000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544365 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.881224 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221523 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430077 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651599 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039713 # Number of tag accesses -system.iocache.tags.data_accesses 1039713 # Number of data accesses +system.iocache.tags.tag_accesses 1039641 # Number of tag accesses +system.iocache.tags.data_accesses 1039641 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115484 # number of demand (read+write) misses -system.iocache.demand_misses::total 115524 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115476 # number of demand (read+write) misses +system.iocache.demand_misses::total 115516 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115484 # number of overall misses -system.iocache.overall_misses::total 115524 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1649759369 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1654845369 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115476 # number of overall misses +system.iocache.overall_misses::total 115516 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5146000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1631213114 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1636359114 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13415597009 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13415597009 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15065356378 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15070793378 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15065356378 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15070793378 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12815787249 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12815787249 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5497000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14447000363 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14452497363 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5497000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14447000363 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14452497363 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8820 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8857 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115484 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115524 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115476 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115516 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115484 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115524 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115476 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115516 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2020,53 +2024,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 187047.547506 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 186840.393926 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 139081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 185112.700182 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 184920.229856 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125774.366319 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125774.366319 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130454.057514 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130455.951820 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130454.057514 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130455.951820 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33085 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120151.009235 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120151.009235 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 137425 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125108.250745 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125112.515695 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 137425 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125108.250745 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125112.515695 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31781 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3398 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3407 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.736610 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.328148 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8820 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8857 # 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mshr miss rate for ReadReq accesses @@ -2080,589 +2084,594 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137047.547506 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 136840.393926 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 89081.081081 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135112.700182 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 134920.229856 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75726.927089 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75726.927089 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80410.241419 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80412.150895 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80410.241419 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80412.150895 # average overall mshr miss latency -system.l2c.tags.replacements 1347841 # number of replacements -system.l2c.tags.tagsinuse 65324.740261 # Cycle average of tags in use -system.l2c.tags.total_refs 50311393 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1410817 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 35.661176 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 4298396500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35245.257795 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 161.370291 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 265.309574 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3415.837838 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 12035.721839 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 188.618634 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 273.886836 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3763.840034 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 9974.897420 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.537800 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002462 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004048 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.052122 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.183651 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002878 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004179 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.057432 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.152205 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996776 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 377 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62599 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 377 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 537 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2787 # Occupied blocks per task id +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70086.224143 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70086.224143 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87425 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75048.409418 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75052.695090 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87425 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75048.409418 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75052.695090 # average overall mshr miss latency +system.l2c.tags.replacements 1414907 # number of replacements +system.l2c.tags.tagsinuse 65322.046709 # Cycle average of tags in use +system.l2c.tags.total_refs 51048957 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1478359 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 34.530826 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2400888500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 35689.019526 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 163.312182 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 256.355195 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4109.760843 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 10213.253541 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 166.614140 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 239.422394 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3052.672621 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11431.636266 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.544571 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002492 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003912 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062710 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.155842 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002542 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003653 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.046580 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.174433 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996735 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 311 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 63141 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 309 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 509 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2809 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::3 5038 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54135 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.005753 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.955185 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 445845701 # Number of tag accesses -system.l2c.tags.data_accesses 445845701 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 522213 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 182395 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 532310 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 179240 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1416158 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 8064911 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 8064911 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 16319354 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 16319354 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 5211 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4888 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10099 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 801611 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 788325 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1589936 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 8045447 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78688.256659 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78738.866765 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 78768.893946 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 78893.350072 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19004.014441 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19028.007793 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19015.984879 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 72000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92332.559725 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92674.455243 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 92504.000491 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 76351.662797 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75856.313952 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 76094.883362 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80750.347127 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82691.860604 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 81751.288869 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20825.027872 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20919.196314 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20867.046041 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79333.574506 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78688.256659 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76351.662797 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 88307.257192 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78738.866765 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78768.893946 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75856.313952 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89076.252130 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 87414.462692 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79333.574506 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78688.256659 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76351.662797 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88307.257192 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78738.866765 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78768.893946 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75856.313952 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89076.252130 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 87414.462692 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177423.826048 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169041.073800 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131429.203929 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86046.293532 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87537.545848 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 81110.850412 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3192252 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1599225 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2999 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 54318 # Transaction distribution +system.membus.trans_dist::ReadResp 482453 # Transaction distribution +system.membus.trans_dist::WriteReq 33697 # Transaction distribution +system.membus.trans_dist::WriteResp 33697 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1307113 # Transaction distribution +system.membus.trans_dist::CleanEvict 222137 # Transaction distribution +system.membus.trans_dist::UpgradeReq 37798 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 524316 # Transaction distribution -system.membus.trans_dist::ReadExResp 524316 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 416875 # Transaction distribution -system.membus.trans_dist::InvalidateReq 614824 # Transaction distribution +system.membus.trans_dist::ReadExReq 575301 # Transaction distribution +system.membus.trans_dist::ReadExResp 575301 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 428135 # Transaction distribution +system.membus.trans_dist::InvalidateReq 621651 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3802484 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3932122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237507 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237507 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4169629 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6864 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4001476 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4131122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237676 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237676 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4368798 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 133717932 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 133889630 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7241472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7241472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 141131102 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3009 # Total snoops (count) -system.membus.snoop_fanout::samples 3143476 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 141781676 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 141953450 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7253312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 149206762 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2813 # Total snoops (count) +system.membus.snoop_fanout::samples 1750905 # Request fanout histogram +system.membus.snoop_fanout::mean 0.020034 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.140117 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3143476 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1715827 98.00% 98.00% # Request fanout histogram +system.membus.snoop_fanout::1 35078 2.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3143476 # Request fanout histogram -system.membus.reqLayer0.occupancy 114116000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1750905 # Request fanout histogram +system.membus.reqLayer0.occupancy 114103000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 50156 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5372500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5413500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8328651016 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8735804910 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5128575160 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5454823379 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44638442 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44601796 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2716,64 +2725,64 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 54578445 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 27714706 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 5543 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2124 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2124 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 55407066 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 28133350 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 5182 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1867 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1867 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 2026220 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25543991 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 9308329 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 16323462 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2693882 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 46501 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 14 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 46515 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2114895 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2114895 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 16324325 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7201544 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1338457 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1231793 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49012603 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31846136 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 876413 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2521080 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 84256232 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2090728512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1112078430 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2928944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8475824 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3214211710 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2126745 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 30549096 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.026641 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.161031 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2058891 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25917963 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 9449679 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 16477862 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2759760 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 47359 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 47372 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2180704 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2180704 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 16478635 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7382055 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1266688 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1234652 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49475900 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32614875 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 885296 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2587313 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 85563384 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2110504128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1140051882 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2983576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8760712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3262300298 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1987088 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 30865453 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.026594 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.160894 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 29735242 97.34% 97.34% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 813854 2.66% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 30044617 97.34% 97.34% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 820836 2.66% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 30549096 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 52321567856 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 30865453 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 53089488175 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1445388 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1406902 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 24533352992 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24765766555 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 14657364738 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 15040405076 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 510704141 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 512773114 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1464609307 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1495395971 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16351 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 16437 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index ab74bea7e..0789be798 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -1,160 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.799232 # Number of seconds simulated -sim_ticks 51799232151500 # Number of ticks simulated -final_tick 51799232151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.821000 # Number of seconds simulated +sim_ticks 51820999867500 # Number of ticks simulated +final_tick 51820999867500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 780767 # Simulator instruction rate (inst/s) -host_op_rate 917508 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48392163425 # Simulator tick rate (ticks/s) -host_mem_usage 677024 # Number of bytes of host memory used -host_seconds 1070.41 # Real time elapsed on the host -sim_insts 835736802 # Number of instructions simulated -sim_ops 982105580 # Number of ops (including micro ops) simulated +host_inst_rate 784285 # Simulator instruction rate (inst/s) +host_op_rate 921634 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45455267989 # Simulator tick rate (ticks/s) +host_mem_usage 675212 # Number of bytes of host memory used +host_seconds 1140.04 # Real time elapsed on the host +sim_insts 894119248 # Number of instructions simulated +sim_ops 1050702892 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 74880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 80448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2375384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 17755184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 76352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 77888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2376540 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 17975768 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 395840 # Number of bytes read from this memory -system.physmem.bytes_read::total 41188284 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2375384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2376540 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4751924 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 62641792 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 15860 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 4720 # Number of bytes written to this memory -system.physmem.bytes_written::total 62662372 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1257 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 57776 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 277428 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1193 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1217 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56880 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 280881 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6185 # Number of read requests responded to by this memory -system.physmem.num_reads::total 683987 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 978778 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 1983 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 590 # Number of write requests responded to by this memory -system.physmem.num_writes::total 981351 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 45858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 342769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 347028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 795152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 45858 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45880 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 91737 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1209319 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 306 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 91 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1209716 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1209319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1446 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 45858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 343075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45880 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 347119 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2004869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 683987 # Number of read requests accepted -system.physmem.writeReqs 981351 # Number of write requests accepted -system.physmem.readBursts 683987 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 981351 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 43730304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 44864 # Total number of bytes read from write queue -system.physmem.bytesWritten 62662336 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 41188284 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 62662372 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 701 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu0.dtb.walker 122816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 126336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2599472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 26029680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 150208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 131904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2604676 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 25292888 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 407488 # Number of bytes read from this memory +system.physmem.bytes_read::total 57465468 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2599472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2604676 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5204148 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78618432 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory +system.physmem.bytes_written::total 78639012 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1919 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1974 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 64898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 406717 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2347 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2061 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56824 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 395211 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6367 # Number of read requests responded to by this memory +system.physmem.num_reads::total 938318 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1228413 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1230986 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 50163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 502300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 50263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 488082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7863 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1108922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 50163 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 50263 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 100425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1517115 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1517512 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1517115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 50163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 502300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 50263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 488479 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7863 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2626435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 938318 # Number of read requests accepted +system.physmem.writeReqs 1230986 # Number of write requests accepted +system.physmem.readBursts 938318 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1230986 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 60016640 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35712 # Total number of bytes read from write queue +system.physmem.bytesWritten 78638272 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 57465468 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 78639012 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 558 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2260 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 41322 # Per bank write bursts -system.physmem.perBankRdBursts::1 41177 # Per bank write bursts -system.physmem.perBankRdBursts::2 39218 # Per bank write bursts -system.physmem.perBankRdBursts::3 39952 # Per bank write bursts -system.physmem.perBankRdBursts::4 41092 # Per bank write bursts -system.physmem.perBankRdBursts::5 49504 # Per bank write bursts -system.physmem.perBankRdBursts::6 36877 # Per bank write bursts -system.physmem.perBankRdBursts::7 36988 # Per bank write bursts -system.physmem.perBankRdBursts::8 38459 # Per bank write bursts -system.physmem.perBankRdBursts::9 81977 # Per bank write bursts -system.physmem.perBankRdBursts::10 39138 # Per bank write bursts -system.physmem.perBankRdBursts::11 41925 # Per bank write bursts -system.physmem.perBankRdBursts::12 38445 # Per bank write bursts -system.physmem.perBankRdBursts::13 41518 # Per bank write bursts -system.physmem.perBankRdBursts::14 36799 # Per bank write bursts -system.physmem.perBankRdBursts::15 38895 # Per bank write bursts -system.physmem.perBankWrBursts::0 61042 # Per bank write bursts -system.physmem.perBankWrBursts::1 63110 # Per bank write bursts -system.physmem.perBankWrBursts::2 61459 # Per bank write bursts -system.physmem.perBankWrBursts::3 62355 # Per bank write bursts -system.physmem.perBankWrBursts::4 60847 # Per bank write bursts -system.physmem.perBankWrBursts::5 67831 # Per bank write bursts -system.physmem.perBankWrBursts::6 59687 # Per bank write bursts -system.physmem.perBankWrBursts::7 59677 # Per bank write bursts -system.physmem.perBankWrBursts::8 60696 # Per bank write bursts -system.physmem.perBankWrBursts::9 62695 # Per bank write bursts -system.physmem.perBankWrBursts::10 60108 # Per bank write bursts -system.physmem.perBankWrBursts::11 60915 # Per bank write bursts -system.physmem.perBankWrBursts::12 59030 # Per bank write bursts -system.physmem.perBankWrBursts::13 62102 # Per bank write bursts -system.physmem.perBankWrBursts::14 56975 # Per bank write bursts -system.physmem.perBankWrBursts::15 60570 # Per bank write bursts +system.physmem.perBankRdBursts::0 57802 # Per bank write bursts +system.physmem.perBankRdBursts::1 61444 # Per bank write bursts +system.physmem.perBankRdBursts::2 58618 # Per bank write bursts +system.physmem.perBankRdBursts::3 56911 # Per bank write bursts +system.physmem.perBankRdBursts::4 53280 # Per bank write bursts +system.physmem.perBankRdBursts::5 57178 # Per bank write bursts +system.physmem.perBankRdBursts::6 52016 # Per bank write bursts +system.physmem.perBankRdBursts::7 52831 # Per bank write bursts +system.physmem.perBankRdBursts::8 55081 # Per bank write bursts +system.physmem.perBankRdBursts::9 100686 # Per bank write bursts +system.physmem.perBankRdBursts::10 57898 # Per bank write bursts +system.physmem.perBankRdBursts::11 58894 # Per bank write bursts +system.physmem.perBankRdBursts::12 52465 # Per bank write bursts +system.physmem.perBankRdBursts::13 56002 # Per bank write bursts +system.physmem.perBankRdBursts::14 52925 # Per bank write bursts +system.physmem.perBankRdBursts::15 53729 # Per bank write bursts +system.physmem.perBankWrBursts::0 76591 # Per bank write bursts +system.physmem.perBankWrBursts::1 80097 # Per bank write bursts +system.physmem.perBankWrBursts::2 79619 # Per bank write bursts +system.physmem.perBankWrBursts::3 80251 # Per bank write bursts +system.physmem.perBankWrBursts::4 74804 # Per bank write bursts +system.physmem.perBankWrBursts::5 78970 # Per bank write bursts +system.physmem.perBankWrBursts::6 72699 # Per bank write bursts +system.physmem.perBankWrBursts::7 74032 # Per bank write bursts +system.physmem.perBankWrBursts::8 75192 # Per bank write bursts +system.physmem.perBankWrBursts::9 79224 # Per bank write bursts +system.physmem.perBankWrBursts::10 76715 # Per bank write bursts +system.physmem.perBankWrBursts::11 78463 # Per bank write bursts +system.physmem.perBankWrBursts::12 72476 # Per bank write bursts +system.physmem.perBankWrBursts::13 78380 # Per bank write bursts +system.physmem.perBankWrBursts::14 75126 # Per bank write bursts +system.physmem.perBankWrBursts::15 76084 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 35 # Number of times write queue was full causing retry -system.physmem.totGap 51799229214500 # Total gap between requests +system.physmem.numWrRetry 41 # Number of times write queue was full causing retry +system.physmem.totGap 51820996946500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 640871 # Read request sizes (log2) +system.physmem.readPktSize::6 895202 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 978778 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 654776 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 22950 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 529 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1228413 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 903707 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 501 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 483 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -165,188 +165,191 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 37595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 53715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 53386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 56244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 54082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 56988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 54298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 54807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 54383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 55346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 57492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 55406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 55164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 56641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 53923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 52610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 52233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 390 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 89 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 437346 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 243.268076 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.507272 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 286.058540 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 195461 44.69% 44.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 115696 26.45% 71.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 38501 8.80% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20148 4.61% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13086 2.99% 87.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8742 2.00% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7314 1.67% 91.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5744 1.31% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 32654 7.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 437346 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 51642 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 13.230801 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 107.035752 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 51638 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 1654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1417 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 136 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 563401 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 246.102850 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 148.051526 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 287.279361 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 250361 44.44% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 146586 26.02% 70.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 50209 8.91% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27045 4.80% 84.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18004 3.20% 87.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12090 2.15% 89.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8995 1.60% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7664 1.36% 92.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 42447 7.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 563401 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 65697 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.273848 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 106.818256 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 65693 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::7168-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::17408-18431 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 51642 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 51642 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.959355 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.129785 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.514310 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 120 0.23% 0.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 58 0.11% 0.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 71 0.14% 0.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 110 0.21% 0.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 46610 90.26% 90.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2201 4.26% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 409 0.79% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 381 0.74% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 125 0.24% 96.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 97 0.19% 97.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 249 0.48% 97.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 37 0.07% 97.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 313 0.61% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 78 0.15% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 24 0.05% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 64 0.12% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 317 0.61% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 20 0.04% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 23 0.04% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 120 0.23% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 150 0.29% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 12 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 17 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 65697 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 65697 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.702878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.053855 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.999985 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 137 0.21% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 78 0.12% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 60 0.09% 0.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 99 0.15% 0.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 51857 78.93% 79.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 9705 14.77% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 1082 1.65% 95.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 596 0.91% 96.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 852 1.30% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 335 0.51% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 83 0.13% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 33 0.05% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 55 0.08% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 34 0.05% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 40 0.06% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 30 0.05% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 421 0.64% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 37 0.06% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 32 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 35 0.05% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 21 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 5 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 14 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 8 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 51642 # Writes before turning the bus around for reads -system.physmem.totQLat 9080957107 # Total ticks spent queuing -system.physmem.totMemAccLat 21892569607 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3416430000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13290.13 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 65697 # Writes before turning the bus around for reads +system.physmem.totQLat 12237400086 # Total ticks spent queuing +system.physmem.totMemAccLat 29820400086 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4688800000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13049.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32040.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.21 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.21 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31799.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.30 # Average write queue length when enqueuing -system.physmem.readRowHits 503634 # Number of row buffer hits during reads -system.physmem.writeRowHits 721404 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.68 # Row buffer hit rate for writes -system.physmem.avgGap 31104333.90 # Average gap between requests -system.physmem.pageHitRate 73.69 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1696456440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 925645875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2543814000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3214131840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3383273718240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1286151175755 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29951333686500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34629138628650 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.526160 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49826371298908 # Time in different power states -system.physmem_0.memoryStateTime::REF 1729690040000 # Time in different power states +system.physmem.avgWrQLen 7.91 # Average write queue length when enqueuing +system.physmem.readRowHits 705929 # Number of row buffer hits during reads +system.physmem.writeRowHits 897152 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.01 # Row buffer hit rate for writes +system.physmem.avgGap 23888305.63 # Average gap between requests +system.physmem.pageHitRate 73.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2146397400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1171149375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3510585000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3998568240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384695652000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1301998363920 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29950494857250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34648015573185 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.609580 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49824747021214 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730417000000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 243166128592 # Time in different power states +system.physmem_0.memoryStateTime::ACT 265835434786 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1609879320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 878406375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2785777800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3130429680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3383273718240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1282982007105 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29954113659000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34628773877520 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.519119 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49831003018963 # Time in different power states -system.physmem_1.memoryStateTime::REF 1729690040000 # Time in different power states +system.physmem_1.actEnergy 2112914160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1152879750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3803904000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3963556800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384695652000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1301510416275 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29950922881500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34648162204485 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.612409 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49825423536265 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730417000000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 238538435537 # Time in different power states +system.physmem_1.memoryStateTime::ACT 265157286235 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -400,70 +403,64 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 118484 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 118484 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17724 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 86321 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 118475 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.236337 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 81.347587 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 118474 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 118475 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 104054 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 25330.679263 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21934.679716 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16178.136591 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 103422 99.39% 99.39% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.39% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 549 0.53% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 13 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 39 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 17 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 133030 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 133030 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 21129 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 95696 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 133019 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 133019 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 133019 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 116836 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 25679.131432 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 22619.213536 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 13703.555245 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 115888 99.19% 99.19% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 821 0.70% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 61 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 31 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 22 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 104054 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -2515798788 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.690729 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1737735704 -69.07% -69.07% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -4253534492 169.07% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -2515798788 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 86322 82.97% 82.97% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 17724 17.03% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 104046 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 118484 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 116836 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 9230012852 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.024648 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -227501296 -2.46% -2.46% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 9457514148 102.46% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 9230012852 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 95697 81.91% 81.91% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 21129 18.09% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 116826 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 133030 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 118484 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 104046 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 133030 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 116826 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 104046 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 222530 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 116826 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 249856 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 78608030 # DTB read hits -system.cpu0.dtb.read_misses 90806 # DTB read misses -system.cpu0.dtb.write_hits 71283429 # DTB write hits -system.cpu0.dtb.write_misses 27678 # DTB write misses -system.cpu0.dtb.flush_tlb 51806 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 83528271 # DTB read hits +system.cpu0.dtb.read_misses 101098 # DTB read misses +system.cpu0.dtb.write_hits 76299925 # DTB write hits +system.cpu0.dtb.write_misses 31932 # DTB write misses +system.cpu0.dtb.flush_tlb 51828 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 19521 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 503 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 69055 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 21506 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 536 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 73288 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4281 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4644 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9631 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 78698836 # DTB read accesses -system.cpu0.dtb.write_accesses 71311107 # DTB write accesses +system.cpu0.dtb.perms_faults 9926 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 83629369 # DTB read accesses +system.cpu0.dtb.write_accesses 76331857 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 149891459 # DTB hits -system.cpu0.dtb.misses 118484 # DTB misses -system.cpu0.dtb.accesses 150009943 # DTB accesses +system.cpu0.dtb.hits 159828196 # DTB hits +system.cpu0.dtb.misses 133030 # DTB misses +system.cpu0.dtb.accesses 159961226 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -493,555 +490,555 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 76645 # Table walker walks requested -system.cpu0.itb.walker.walksLong 76645 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4248 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67077 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 76645 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 76645 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 76645 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 71325 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 28947.290571 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 25637.754479 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 19237.260354 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 70555 98.92% 98.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 2 0.00% 98.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 668 0.94% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 18 0.03% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 42 0.06% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 71325 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 1705681704 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 1705681704 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1705681704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 67077 94.04% 94.04% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 4248 5.96% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 71325 # Table walker page sizes translated +system.cpu0.itb.walker.walks 78025 # Table walker walks requested +system.cpu0.itb.walker.walksLong 78025 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4409 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67964 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 78025 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 78025 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 78025 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 72373 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 28767.572161 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 25800.961773 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 15890.832899 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 71328 98.56% 98.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 906 1.25% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 58 0.08% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 43 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 72373 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -294749296 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -294749296 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -294749296 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 67964 93.91% 93.91% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 4409 6.09% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 72373 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 76645 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 76645 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 78025 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 78025 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 71325 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 71325 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 147970 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 417906874 # ITB inst hits -system.cpu0.itb.inst_misses 76645 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72373 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72373 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 150398 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 446488504 # ITB inst hits +system.cpu0.itb.inst_misses 78025 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 51806 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 51828 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 19521 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 503 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 51690 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21506 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 536 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 53811 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 417983519 # ITB inst accesses -system.cpu0.itb.hits 417906874 # DTB hits -system.cpu0.itb.misses 76645 # DTB misses -system.cpu0.itb.accesses 417983519 # DTB accesses -system.cpu0.numCycles 51800067955 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 446566529 # ITB inst accesses +system.cpu0.itb.hits 446488504 # DTB hits +system.cpu0.itb.misses 78025 # DTB misses +system.cpu0.itb.accesses 446566529 # DTB accesses +system.cpu0.numCycles 51821574278 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16018 # number of quiesce instructions executed -system.cpu0.committedInsts 417645333 # Number of instructions committed -system.cpu0.committedOps 490761503 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 451046619 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 435772 # Number of float alu accesses -system.cpu0.num_func_calls 25047272 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 63386661 # number of instructions that are conditional controls -system.cpu0.num_int_insts 451046619 # number of integer instructions -system.cpu0.num_fp_insts 435772 # number of float instructions -system.cpu0.num_int_register_reads 653989680 # number of times the integer registers were read -system.cpu0.num_int_register_writes 357583746 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 703407 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 366712 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 108509856 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 108205607 # number of times the CC registers were written -system.cpu0.num_mem_refs 149883436 # number of memory refs -system.cpu0.num_load_insts 78604497 # Number of load instructions -system.cpu0.num_store_insts 71278939 # Number of store instructions -system.cpu0.num_idle_cycles 50264779959.264511 # Number of idle cycles -system.cpu0.num_busy_cycles 1535287995.735491 # Number of busy cycles -system.cpu0.not_idle_fraction 0.029639 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.970361 # Percentage of idle cycles -system.cpu0.Branches 93191056 # Number of branches fetched +system.cpu0.kern.inst.quiesce 16348 # number of quiesce instructions executed +system.cpu0.committedInsts 446216062 # Number of instructions committed +system.cpu0.committedOps 524400051 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 481388306 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 440832 # Number of float alu accesses +system.cpu0.num_func_calls 26357525 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 68205669 # number of instructions that are conditional controls +system.cpu0.num_int_insts 481388306 # number of integer instructions +system.cpu0.num_fp_insts 440832 # number of float instructions +system.cpu0.num_int_register_reads 703333504 # number of times the integer registers were read +system.cpu0.num_int_register_writes 381971540 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 708271 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 380080 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 117540708 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 117236412 # number of times the CC registers were written +system.cpu0.num_mem_refs 159819450 # number of memory refs +system.cpu0.num_load_insts 83525533 # Number of load instructions +system.cpu0.num_store_insts 76293917 # Number of store instructions +system.cpu0.num_idle_cycles 50236144373.803871 # Number of idle cycles +system.cpu0.num_busy_cycles 1585429904.196130 # Number of busy cycles +system.cpu0.not_idle_fraction 0.030594 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.969406 # Percentage of idle cycles +system.cpu0.Branches 99643757 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 339970284 69.23% 69.23% # Class of executed instruction -system.cpu0.op_class::IntMult 1088528 0.22% 69.46% # Class of executed instruction -system.cpu0.op_class::IntDiv 48838 0.01% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 4 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 11 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 16 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 53987 0.01% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::MemRead 78604497 16.01% 85.48% # Class of executed instruction -system.cpu0.op_class::MemWrite 71278939 14.52% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 363667031 69.31% 69.31% # Class of executed instruction +system.cpu0.op_class::IntMult 1107197 0.21% 69.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 49205 0.01% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 55532 0.01% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::MemRead 83525533 15.92% 85.46% # Class of executed instruction +system.cpu0.op_class::MemWrite 76293917 14.54% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 491045105 # Class of executed instruction -system.cpu0.dcache.tags.replacements 9348690 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.942765 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 290545917 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9349202 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 31.077082 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 5830459500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 239.060392 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 272.882373 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.466915 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.532973 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy +system.cpu0.op_class::total 524698416 # Class of executed instruction +system.cpu0.dcache.tags.replacements 10234473 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.965653 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 310064662 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10234985 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.294589 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 3504381500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 238.684462 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 273.281191 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.466181 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.533752 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1209380446 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1209380446 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 73565050 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 73675214 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 147240264 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67654945 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 67959241 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 135614186 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 188452 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 185421 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 373873 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 174201 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 157964 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 332165 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1663387 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1666647 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3330034 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1801503 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1811825 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3613328 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 141394196 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 141792419 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 283186615 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 141582648 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 141977840 # number of overall hits -system.cpu0.dcache.overall_hits::total 283560488 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2455322 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2424347 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 4879669 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1010929 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 979195 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1990124 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 579794 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 548628 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1128422 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 615937 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 604869 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1220806 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 138893 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 146035 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 284928 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 1291899613 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1291899613 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 78014225 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 78760782 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 156775007 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72354151 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 72480719 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 144834870 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 196883 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 197851 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 394734 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 165349 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 170410 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 335759 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1859357 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1826349 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3685706 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2010395 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1982201 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 3992596 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 150533725 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 151411911 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 301945636 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 150730608 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 151609762 # number of overall hits +system.cpu0.dcache.overall_hits::total 302340370 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2625385 # 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mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.770234 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.765295 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767784 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.789986 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.781729 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.785875 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057648 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060980 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059302 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027919 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.027339 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027629 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031731 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.030940 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031335 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16118.940424 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15946.282062 # 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average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23756.481717 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22961.095144 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23347.429092 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23152.014437 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185555.072633 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182271.629536 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183941.505459 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89946.537145 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94189.598153 # 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number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 84606442500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 84117530000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 168723972500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 84606442500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 84117530000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 168723972500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 84606442500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 84117530000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 168723972500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780591500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2656208000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5436799500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2780591500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 2656208000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 5436799500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015978 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015859 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015918 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015978 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015859 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.015918 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015978 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015859 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.015918 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12670.540197 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12679.028329 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12674.770544 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12670.540197 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12679.028329 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12674.770544 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12670.540197 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12679.028329 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12674.770544 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.713043 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126070.713043 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 85279523000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 86108596000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 171388119000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 85279523000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 86108596000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 171388119000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 85279523000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 86108596000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 171388119000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1959551500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1303928500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3263480000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1959551500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1303928500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 3263480000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015364 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015454 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015409 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015364 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015454 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.015409 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015364 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015454 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.015409 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12432.077008 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12432.384326 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12432.231409 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12432.077008 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12432.384326 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12432.231409 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12432.077008 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12432.384326 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12432.231409 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75674.898551 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75674.898551 # average overall mshr uncacheable latency system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1071,68 +1068,73 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 116402 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 116402 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17438 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84735 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 8 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 116394 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.103098 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 35.173529 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-1023 116393 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 116394 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 102181 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 25297.388947 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21878.077952 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16308.937968 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 101549 99.38% 99.38% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2 0.00% 99.38% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 548 0.54% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 11 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 41 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 2 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 24 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 102181 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 344855740 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean -3.415840 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1522827704 441.58% 441.58% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -1177971964 -341.58% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 344855740 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 84735 82.93% 82.93% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17438 17.07% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 102173 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 116402 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 133445 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 133445 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20908 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 96452 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 13 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 133432 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.299778 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 83.395537 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 133430 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 133432 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 117373 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 25894.485955 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 22861.122715 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13849.356083 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 74140 63.17% 63.17% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 42199 35.95% 99.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 555 0.47% 99.59% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 343 0.29% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 6 0.01% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 48 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 11 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 29 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 23 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 117373 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 6007861436 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 1.129422 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -777548296 -12.94% -12.94% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 6785409732 112.94% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 6007861436 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 96452 82.18% 82.18% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 20908 17.82% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 117360 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 133445 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 116402 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 102173 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 133445 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 117360 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 102173 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 218575 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 117360 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 250805 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 78662844 # DTB read hits -system.cpu1.dtb.read_misses 89684 # DTB read misses -system.cpu1.dtb.write_hits 71537174 # DTB write hits -system.cpu1.dtb.write_misses 26718 # DTB write misses -system.cpu1.dtb.flush_tlb 51800 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 84301684 # DTB read hits +system.cpu1.dtb.read_misses 101780 # DTB read misses +system.cpu1.dtb.write_hits 76371214 # DTB write hits +system.cpu1.dtb.write_misses 31665 # DTB write misses +system.cpu1.dtb.flush_tlb 51822 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 18845 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 504 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 67247 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 21521 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 74029 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 3767 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4498 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9113 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 78752528 # DTB read accesses -system.cpu1.dtb.write_accesses 71563892 # DTB write accesses +system.cpu1.dtb.perms_faults 10027 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 84403464 # DTB read accesses +system.cpu1.dtb.write_accesses 76402879 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 150200018 # DTB hits -system.cpu1.dtb.misses 116402 # DTB misses -system.cpu1.dtb.accesses 150316420 # DTB accesses +system.cpu1.dtb.hits 160672898 # DTB hits +system.cpu1.dtb.misses 133445 # DTB misses +system.cpu1.dtb.accesses 160806343 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1162,127 +1164,131 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 74223 # Table walker walks requested -system.cpu1.itb.walker.walksLong 74223 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4163 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 64958 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 74223 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 74223 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 74223 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 69121 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28935.417601 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25541.870805 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19930.697059 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 68364 98.90% 98.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 4 0.01% 98.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 655 0.95% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 17 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 38 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 18 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 69121 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1449734704 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1449734704 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1449734704 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 64958 93.98% 93.98% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 4163 6.02% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 69121 # Table walker page sizes translated +system.cpu1.itb.walker.walks 78111 # Table walker walks requested +system.cpu1.itb.walker.walksLong 78111 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4330 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 68231 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 78111 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 78111 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 78111 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 72561 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28942.620692 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 25930.573552 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 16143.079615 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 35934 49.52% 49.52% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 35483 48.90% 98.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 386 0.53% 98.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 612 0.84% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 10 0.01% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 47 0.06% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 20 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 31 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 12 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 11 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 72561 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -850152296 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -850152296 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -850152296 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 68231 94.03% 94.03% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 4330 5.97% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 72561 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 74223 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 74223 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 78111 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 78111 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 69121 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 69121 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 143344 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 418345598 # ITB inst hits -system.cpu1.itb.inst_misses 74223 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72561 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72561 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 150672 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 448183312 # ITB inst hits +system.cpu1.itb.inst_misses 78111 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 51800 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 51822 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 18845 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 504 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 49961 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21521 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 53985 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 418419821 # ITB inst accesses -system.cpu1.itb.hits 418345598 # DTB hits -system.cpu1.itb.misses 74223 # DTB misses -system.cpu1.itb.accesses 418419821 # DTB accesses -system.cpu1.numCycles 51798396348 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 448261423 # ITB inst accesses +system.cpu1.itb.hits 448183312 # DTB hits +system.cpu1.itb.misses 78111 # DTB misses +system.cpu1.itb.accesses 448261423 # DTB accesses +system.cpu1.numCycles 51820425457 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 418091469 # Number of instructions committed -system.cpu1.committedOps 491344077 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 451749452 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 464131 # Number of float alu accesses -system.cpu1.num_func_calls 25120971 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 63413635 # number of instructions that are conditional controls -system.cpu1.num_int_insts 451749452 # number of integer instructions -system.cpu1.num_fp_insts 464131 # number of float instructions -system.cpu1.num_int_register_reads 653305653 # number of times the integer registers were read -system.cpu1.num_int_register_writes 357922313 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 749406 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 392664 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 108141039 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 107840924 # number of times the CC registers were written -system.cpu1.num_mem_refs 150187574 # number of memory refs -system.cpu1.num_load_insts 78657446 # Number of load instructions -system.cpu1.num_store_insts 71530128 # Number of store instructions -system.cpu1.num_idle_cycles 50264307367.295029 # Number of idle cycles -system.cpu1.num_busy_cycles 1534088980.704967 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029617 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970383 # Percentage of idle cycles -system.cpu1.Branches 93317418 # Number of branches fetched +system.cpu1.committedInsts 447903186 # Number of instructions committed +system.cpu1.committedOps 526302841 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 483164392 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 453837 # Number of float alu accesses +system.cpu1.num_func_calls 26485275 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 68482317 # number of instructions that are conditional controls +system.cpu1.num_int_insts 483164392 # number of integer instructions +system.cpu1.num_fp_insts 453837 # number of float instructions +system.cpu1.num_int_register_reads 704985819 # number of times the integer registers were read +system.cpu1.num_int_register_writes 383399771 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 733419 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 379508 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 118000089 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 117710485 # number of times the CC registers were written +system.cpu1.num_mem_refs 160666503 # number of memory refs +system.cpu1.num_load_insts 84298667 # Number of load instructions +system.cpu1.num_store_insts 76367836 # Number of store instructions +system.cpu1.num_idle_cycles 50233099437.419525 # Number of idle cycles +system.cpu1.num_busy_cycles 1587326019.580469 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030631 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969369 # Percentage of idle cycles +system.cpu1.Branches 100046269 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 340283943 69.22% 69.22% # Class of executed instruction -system.cpu1.op_class::IntMult 1041145 0.21% 69.43% # Class of executed instruction -system.cpu1.op_class::IntDiv 48269 0.01% 69.44% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 4 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 2 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 5 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 58327 0.01% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::MemRead 78657446 16.00% 85.45% # Class of executed instruction -system.cpu1.op_class::MemWrite 71530128 14.55% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 364713411 69.26% 69.26% # Class of executed instruction +system.cpu1.op_class::IntMult 1116791 0.21% 69.47% # Class of executed instruction +system.cpu1.op_class::IntDiv 48530 0.01% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 54891 0.01% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::MemRead 84298667 16.01% 85.50% # Class of executed instruction +system.cpu1.op_class::MemWrite 76367836 14.50% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 491619269 # Class of executed instruction -system.iobus.trans_dist::ReadReq 40338 # Transaction distribution -system.iobus.trans_dist::ReadResp 40338 # Transaction distribution +system.cpu1.op_class::total 526600168 # Class of executed instruction +system.iobus.trans_dist::ReadReq 40318 # Transaction distribution +system.iobus.trans_dist::ReadResp 40318 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1299,11 +1305,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231034 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231034 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230994 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230994 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353818 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353778 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1318,14 +1324,14 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334408 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334408 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492488 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42145500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42147500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 323000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1335,9 +1341,9 @@ system.iobus.reqLayer4.occupancy 11000 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) @@ -1345,73 +1351,73 @@ system.iobus.reqLayer16.occupancy 17000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25719500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25749000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38601500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38609000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 566847151 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568885533 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147794000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147754000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115499 # number of replacements -system.iocache.tags.tagsinuse 10.451110 # Cycle average of tags in use +system.iocache.tags.replacements 115478 # number of replacements +system.iocache.tags.tagsinuse 10.457315 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115515 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115494 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13171691140000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.508460 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.942650 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219279 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433916 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653194 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13153888090000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.511180 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946135 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219449 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434133 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653582 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040010 # Number of tag accesses -system.iocache.tags.data_accesses 1040010 # Number of data accesses +system.iocache.tags.tag_accesses 1039830 # Number of tag accesses +system.iocache.tags.data_accesses 1039830 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8853 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8890 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8833 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8870 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115517 # number of demand (read+write) misses -system.iocache.demand_misses::total 115557 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115497 # number of demand (read+write) misses +system.iocache.demand_misses::total 115537 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115517 # number of overall misses -system.iocache.overall_misses::total 115557 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1618419141 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1623489641 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115497 # number of overall misses +system.iocache.overall_misses::total 115537 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1609929768 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1615016268 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13411968510 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13411968510 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15030387651 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15035809151 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15030387651 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15035809151 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12771447265 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12771447265 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14381377033 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14386814533 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14381377033 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14386814533 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8853 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8890 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8833 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8870 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115517 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115557 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115497 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115537 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115517 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115557 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115497 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115537 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1425,53 +1431,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 182810.249746 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182619.757143 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182263.078003 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182076.242165 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125740.348290 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125740.348290 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130114.075426 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130115.952742 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130114.075426 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130115.952742 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31642 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119735.311492 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119735.311492 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124517.321082 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124521.274856 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124517.321082 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124521.274856 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31700 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3353 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3352 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.436922 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.457041 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8853 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8890 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8833 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8870 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115517 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115557 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115497 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115537 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115517 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115557 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1175769141 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1178989641 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115497 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115537 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1168279768 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1171516268 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073599158 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8073599158 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9249368299 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9252789799 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9249368299 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9252789799 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7431457785 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7431457785 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8599737553 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8603175053 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8599737553 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8603175053 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1485,564 +1491,571 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132810.249746 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 132619.757143 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132263.078003 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 132076.242165 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.884403 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.884403 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80069.325718 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80071.218524 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80069.325718 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80071.218524 # average overall mshr miss latency -system.l2c.tags.replacements 1026360 # number of replacements -system.l2c.tags.tagsinuse 65258.201118 # Cycle average of tags in use -system.l2c.tags.total_refs 41749797 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1088957 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 38.339252 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 12386120500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37949.534950 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 104.286779 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 159.329733 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4753.488207 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9126.220322 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 118.614839 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 183.809686 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3411.314898 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 9451.601704 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.579064 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001591 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002431 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.072532 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.139255 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001810 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002805 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.052053 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.144220 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995761 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62377 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 220 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2461 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5447 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54048 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.951797 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 372663502 # Number of tag accesses -system.l2c.tags.data_accesses 372663502 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 212373 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 162936 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 207984 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 157286 # number of ReadReq hits -system.l2c.ReadReq_hits::total 740579 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 7311510 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 7311510 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 13309724 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 13309724 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 4522 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4435 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 8957 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 815767 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 776062 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1591829 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 6641663 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 6598566 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 13240229 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 3014297 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 2962809 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 5977106 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 376322 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 363170 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 739492 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 212373 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 162936 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 6641663 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3830064 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 207984 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 157286 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6598566 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3738871 # number of demand (read+write) hits -system.l2c.demand_hits::total 21549743 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 212373 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 162936 # number of overall hits -system.l2c.overall_hits::cpu0.inst 6641663 # number of overall hits -system.l2c.overall_hits::cpu0.data 3830064 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 207984 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 157286 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6598566 # number of overall hits -system.l2c.overall_hits::cpu1.data 3738871 # number of overall hits -system.l2c.overall_hits::total 21549743 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1170 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1257 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1193 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1217 # number of ReadReq misses -system.l2c.ReadReq_misses::total 4837 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 16637 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16471 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 33108 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69671.658526 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69671.658526 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74458.536178 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74462.510304 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74458.536178 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74462.510304 # average overall mshr miss latency +system.l2c.tags.replacements 1307385 # number of replacements +system.l2c.tags.tagsinuse 65260.397522 # Cycle average of tags in use +system.l2c.tags.total_refs 44030779 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1370457 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 32.128537 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 6646395500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38500.682373 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 145.371302 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 226.787619 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3397.197981 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9485.761310 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 150.823098 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 211.566669 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2947.507944 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 10194.699226 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.587474 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002218 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003461 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.051837 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.144741 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002301 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003228 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.044975 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.155559 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995795 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 284 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62788 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 283 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2444 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5467 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54432 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.958069 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 395683924 # Number of tag accesses +system.l2c.tags.data_accesses 395683924 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 246270 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 166121 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 249681 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 166863 # number of ReadReq hits +system.l2c.ReadReq_hits::total 828935 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 7894898 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 7894898 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 13783694 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 13783694 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 4999 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5005 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 10004 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 822661 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 809558 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1632219 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 6820625 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 6886530 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 13707155 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3255016 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3312365 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 6567381 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 362783 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 360629 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 723412 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 246270 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 166121 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 6820625 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4077677 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 249681 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 166863 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 6886530 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4121923 # number of demand (read+write) hits +system.l2c.demand_hits::total 22735690 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 246270 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 166121 # number of overall hits +system.l2c.overall_hits::cpu0.inst 6820625 # number of overall hits +system.l2c.overall_hits::cpu0.data 4077677 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 249681 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 166863 # number of overall hits +system.l2c.overall_hits::cpu1.inst 6886530 # number of overall hits +system.l2c.overall_hits::cpu1.data 4121923 # number of overall hits +system.l2c.overall_hits::total 22735690 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 1919 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1974 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2347 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2061 # number of ReadReq misses +system.l2c.ReadReq_misses::total 8301 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 17868 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 18114 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 35982 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 3 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 164166 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 170807 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 334973 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 35751 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 35817 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 71568 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 113964 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 110564 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 224528 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 239615 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 241699 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 481314 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1170 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1257 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 35751 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 278130 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1193 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1217 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 35817 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 281371 # number of demand (read+write) misses -system.l2c.demand_misses::total 635906 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1170 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1257 # number of overall misses -system.l2c.overall_misses::cpu0.inst 35751 # number of overall misses -system.l2c.overall_misses::cpu0.data 278130 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1193 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1217 # number of overall misses -system.l2c.overall_misses::cpu1.inst 35817 # number of overall misses -system.l2c.overall_misses::cpu1.data 281371 # number of overall misses -system.l2c.overall_misses::total 635906 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 158334000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 173858500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 161742000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 169455500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 663390000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 664049000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 658035500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1322084500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 77500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 79500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 157000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 21519096500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 22411791000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 43930887500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 4720674000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 4748397000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 9469071000 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 15191781000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 14765909500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 29957690500 # number of ReadSharedReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu0.data 155000 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu1.data 387500 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::total 542500 # number of InvalidateReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 158334000 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121991.405875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125575.859179 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129240.345111 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122573.833654 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122130.138582 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 122127.735764 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173032.961904 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169747.690636 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138947.871247 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83876.530641 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87717.802321 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 96575.168720 # average overall mshr uncacheable latency -system.membus.trans_dist::ReadReq 76829 # Transaction distribution -system.membus.trans_dist::ReadResp 386652 # Transaction distribution -system.membus.trans_dist::WriteReq 33709 # Transaction distribution -system.membus.trans_dist::WriteResp 33709 # Transaction distribution -system.membus.trans_dist::WritebackDirty 978778 # Transaction distribution -system.membus.trans_dist::CleanEvict 162070 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33685 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 334406 # Transaction distribution -system.membus.trans_dist::ReadExResp 334406 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 309823 # Transaction distribution -system.membus.trans_dist::InvalidateReq 587971 # Transaction distribution +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.245375 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.241261 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.243340 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005687 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005721 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005704 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.041166 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.040639 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.416724 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.409113 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.412955 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.007732 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011743 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005687 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.090803 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.009312 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.012201 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005721 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.087625 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.037673 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.007732 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011743 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005687 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.090803 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.009312 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.012201 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005721 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.087625 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.037673 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76169.880146 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78131.965552 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75604.388581 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77879.184862 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 76900.975786 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18924.669801 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18923.291377 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18923.975877 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 36166.666667 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 70500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 44750 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 72050.491966 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71881.386450 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 71967.562553 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72959.780575 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72606.251420 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72781.640257 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74479.073353 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74378.277580 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74428.910610 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 18671.781922 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18663.857839 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 18667.893869 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76169.880146 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78131.965552 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72959.780575 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72883.868824 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75604.388581 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77879.184862 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72606.251420 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72754.639228 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 72854.824694 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76169.880146 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78131.965552 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72959.780575 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72883.868824 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75604.388581 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77879.184862 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72606.251420 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72754.639228 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 72854.824694 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173784.623188 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171027.320470 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 111091.538572 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 91362.585482 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81557.769149 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 77213.649234 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 2972233 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1487104 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3352 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 76831 # Transaction distribution +system.membus.trans_dist::ReadResp 450834 # Transaction distribution +system.membus.trans_dist::WriteReq 33710 # Transaction distribution +system.membus.trans_dist::WriteResp 33710 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1228413 # Transaction distribution +system.membus.trans_dist::CleanEvict 193324 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36554 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 524356 # Transaction distribution +system.membus.trans_dist::ReadExResp 524356 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 374003 # Transaction distribution +system.membus.trans_dist::InvalidateReq 615538 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6936 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2901743 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3031441 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237241 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237241 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3268682 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3721390 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3851094 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237382 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237382 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4088476 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 96630432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 96800270 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7220224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7220224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 104020494 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3365 # Total snoops (count) -system.membus.snoop_fanout::samples 2517308 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 128872672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 129042522 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7231808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7231808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 136274330 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3165 # Total snoops (count) +system.membus.snoop_fanout::samples 1660996 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019349 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.137749 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2517308 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1628857 98.07% 98.07% # Request fanout histogram +system.membus.snoop_fanout::1 32139 1.93% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2517308 # Request fanout histogram -system.membus.reqLayer0.occupancy 106894000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1660996 # Request fanout histogram +system.membus.reqLayer0.occupancy 106934500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5659000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5678000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6490935886 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8069625955 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3578419285 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4926078787 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44788681 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44722660 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2096,61 +2109,61 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 45897959 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 23236926 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1749 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2692 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2692 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 48668708 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 24647917 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1743 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2076 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2076 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 1189053 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 20703336 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33709 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33709 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 8290323 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 13311280 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2200261 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 42068 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 42070 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1926802 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1926802 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 13311797 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6210524 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1327470 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1220806 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 40021124 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28266989 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 766613 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1091027 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 70145753 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1704049428 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 988401530 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2581568 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3381760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2698414286 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1625114 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 25183319 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021416 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.144767 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 1292402 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 21924695 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 9016681 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 13785272 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2525177 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 45989 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 45993 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2157137 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2157137 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 13785789 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6848293 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1261037 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1232293 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 41443100 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30932231 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 796412 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1256395 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 74428138 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1764720404 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1081696966 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2696152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 4001736 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2853115258 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1718109 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 26731746 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021922 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.146427 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 24643989 97.86% 97.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 539330 2.14% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 26145745 97.81% 97.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 586001 2.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 25183319 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 43932563500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 26731746 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 46403347500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1579898 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1695386 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 20010820500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 20721808500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 12874657982 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 14193795462 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 443917000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 459393000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 668307000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 756178000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 63eb8fdf2..30d85e2f4 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.230834 # Nu sim_ticks 5230834315000 # Number of ticks simulated final_tick 5230834315000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185450 # Simulator instruction rate (inst/s) -host_op_rate 366593 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2377836678 # Simulator tick rate (ticks/s) -host_mem_usage 757080 # Number of bytes of host memory used -host_seconds 2199.83 # Real time elapsed on the host +host_inst_rate 207627 # Simulator instruction rate (inst/s) +host_op_rate 410431 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2662189440 # Simulator tick rate (ticks/s) +host_mem_usage 751184 # Number of bytes of host memory used +host_seconds 1964.86 # Real time elapsed on the host sim_insts 407959263 # Number of instructions simulated sim_ops 806441023 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index 867862e29..0e6bf5b77 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.220167 # Nu sim_ticks 5220166723500 # Number of ticks simulated final_tick 5220166723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149296 # Simulator instruction rate (inst/s) -host_op_rate 289896 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5158950187 # Simulator tick rate (ticks/s) -host_mem_usage 785372 # Number of bytes of host memory used -host_seconds 1011.87 # Real time elapsed on the host +host_inst_rate 281505 # Simulator instruction rate (inst/s) +host_op_rate 546613 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9727443238 # Simulator tick rate (ticks/s) +host_mem_usage 784792 # Number of bytes of host memory used +host_seconds 536.64 # Real time elapsed on the host sim_insts 151067812 # Number of instructions simulated sim_ops 293336428 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index d05c61c9b..70169df1b 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,149 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.140315 # Number of seconds simulated -sim_ticks 5140314861500 # Number of ticks simulated -final_tick 5140314861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.142303 # Number of seconds simulated +sim_ticks 5142302696000 # Number of ticks simulated +final_tick 5142302696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 305956 # Simulator instruction rate (inst/s) -host_op_rate 608211 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6473981728 # Simulator tick rate (ticks/s) -host_mem_usage 946268 # Number of bytes of host memory used -host_seconds 794.00 # Real time elapsed on the host -sim_insts 242927760 # Number of instructions simulated -sim_ops 482917054 # Number of ops (including micro ops) simulated +host_inst_rate 292534 # Simulator instruction rate (inst/s) +host_op_rate 581577 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6171937350 # Simulator tick rate (ticks/s) +host_mem_usage 967756 # Number of bytes of host memory used +host_seconds 833.17 # Real time elapsed on the host +sim_insts 243732330 # Number of instructions simulated +sim_ops 484555405 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 520064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5497600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 84480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1835520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 3392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 349504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2870720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 495360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5776768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 125248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2074112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 322688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2420672 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11189952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 520064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 84480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 349504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 954048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8999680 # Number of bytes written to this memory -system.physmem.bytes_written::total 8999680 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 8126 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 85900 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1320 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 28680 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 53 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5461 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 44855 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11247552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 495360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 125248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 322688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 943296 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9049984 # Number of bytes written to this memory +system.physmem.bytes_written::total 9049984 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7740 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 90262 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1957 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 32408 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 62 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5042 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 37823 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 174843 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 140620 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140620 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 101174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1069506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 357083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 67993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 558472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2176900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 101174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16435 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 67993 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 185601 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1750803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1750803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1750803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 101174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1069506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 357083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 67993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 558472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3927703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 80812 # Number of read requests accepted -system.physmem.writeReqs 75442 # Number of write requests accepted -system.physmem.readBursts 80812 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 75442 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5166976 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4992 # Total number of bytes read from write queue -system.physmem.bytesWritten 4828288 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5171968 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4828288 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 78 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 175743 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141406 # Number of write requests responded to by this memory +system.physmem.num_writes::total 141406 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 96330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1123382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 24356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 403343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 62752 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 470737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2187260 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 96330 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 24356 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 62752 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 183438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1759909 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1759909 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1759909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 96330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1123382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 24356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 403343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 62752 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 470737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3947169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 77737 # Number of read requests accepted +system.physmem.writeReqs 69857 # Number of write requests accepted +system.physmem.readBursts 77737 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 69857 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 4969408 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5760 # Total number of bytes read from write queue +system.physmem.bytesWritten 4469312 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 4975168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4470848 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 90 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4794 # Per bank write bursts -system.physmem.perBankRdBursts::1 4935 # Per bank write bursts -system.physmem.perBankRdBursts::2 5679 # Per bank write bursts -system.physmem.perBankRdBursts::3 5481 # Per bank write bursts -system.physmem.perBankRdBursts::4 5227 # Per bank write bursts -system.physmem.perBankRdBursts::5 4545 # Per bank write bursts -system.physmem.perBankRdBursts::6 4803 # Per bank write bursts -system.physmem.perBankRdBursts::7 4398 # Per bank write bursts -system.physmem.perBankRdBursts::8 4149 # Per bank write bursts -system.physmem.perBankRdBursts::9 4569 # Per bank write bursts -system.physmem.perBankRdBursts::10 4618 # Per bank write bursts -system.physmem.perBankRdBursts::11 5314 # Per bank write bursts -system.physmem.perBankRdBursts::12 5529 # Per bank write bursts -system.physmem.perBankRdBursts::13 6006 # Per bank write bursts -system.physmem.perBankRdBursts::14 5624 # Per bank write bursts -system.physmem.perBankRdBursts::15 5063 # Per bank write bursts -system.physmem.perBankWrBursts::0 4779 # Per bank write bursts -system.physmem.perBankWrBursts::1 4598 # Per bank write bursts -system.physmem.perBankWrBursts::2 5104 # Per bank write bursts -system.physmem.perBankWrBursts::3 4643 # Per bank write bursts -system.physmem.perBankWrBursts::4 4893 # Per bank write bursts -system.physmem.perBankWrBursts::5 4408 # Per bank write bursts -system.physmem.perBankWrBursts::6 5020 # Per bank write bursts +system.physmem.perBankRdBursts::0 4738 # Per bank write bursts +system.physmem.perBankRdBursts::1 4587 # Per bank write bursts +system.physmem.perBankRdBursts::2 5683 # Per bank write bursts +system.physmem.perBankRdBursts::3 5272 # Per bank write bursts +system.physmem.perBankRdBursts::4 4460 # Per bank write bursts +system.physmem.perBankRdBursts::5 4242 # Per bank write bursts +system.physmem.perBankRdBursts::6 4391 # Per bank write bursts +system.physmem.perBankRdBursts::7 4725 # Per bank write bursts +system.physmem.perBankRdBursts::8 4783 # Per bank write bursts +system.physmem.perBankRdBursts::9 4859 # Per bank write bursts +system.physmem.perBankRdBursts::10 4723 # Per bank write bursts +system.physmem.perBankRdBursts::11 4859 # Per bank write bursts +system.physmem.perBankRdBursts::12 4897 # Per bank write bursts +system.physmem.perBankRdBursts::13 5764 # Per bank write bursts +system.physmem.perBankRdBursts::14 5025 # Per bank write bursts +system.physmem.perBankRdBursts::15 4639 # Per bank write bursts +system.physmem.perBankWrBursts::0 4788 # Per bank write bursts +system.physmem.perBankWrBursts::1 4346 # Per bank write bursts +system.physmem.perBankWrBursts::2 4813 # Per bank write bursts +system.physmem.perBankWrBursts::3 4456 # Per bank write bursts +system.physmem.perBankWrBursts::4 4399 # Per bank write bursts +system.physmem.perBankWrBursts::5 4368 # Per bank write bursts +system.physmem.perBankWrBursts::6 4481 # Per bank write bursts system.physmem.perBankWrBursts::7 4596 # Per bank write bursts -system.physmem.perBankWrBursts::8 4781 # Per bank write bursts -system.physmem.perBankWrBursts::9 4864 # Per bank write bursts -system.physmem.perBankWrBursts::10 4212 # Per bank write bursts -system.physmem.perBankWrBursts::11 4809 # Per bank write bursts -system.physmem.perBankWrBursts::12 4547 # Per bank write bursts -system.physmem.perBankWrBursts::13 4942 # Per bank write bursts -system.physmem.perBankWrBursts::14 4756 # Per bank write bursts -system.physmem.perBankWrBursts::15 4490 # Per bank write bursts +system.physmem.perBankWrBursts::8 3541 # Per bank write bursts +system.physmem.perBankWrBursts::9 3660 # Per bank write bursts +system.physmem.perBankWrBursts::10 3623 # Per bank write bursts +system.physmem.perBankWrBursts::11 4308 # Per bank write bursts +system.physmem.perBankWrBursts::12 4463 # Per bank write bursts +system.physmem.perBankWrBursts::13 5017 # Per bank write bursts +system.physmem.perBankWrBursts::14 4599 # Per bank write bursts +system.physmem.perBankWrBursts::15 4375 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 5136542953000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 5141302561000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 80812 # Read request sizes (log2) +system.physmem.readPktSize::6 77737 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 75442 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 74967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 732 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 150 # What read queue length does an incoming req see +system.physmem.writePktSize::6 69857 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 73816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3057 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 113 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see @@ -161,1100 +169,1103 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 35991 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 277.715651 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.626258 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 306.002665 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14739 40.95% 40.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8609 23.92% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3739 10.39% 75.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1992 5.53% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1395 3.88% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 963 2.68% 87.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 662 1.84% 89.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 569 1.58% 90.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3323 9.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 35991 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3467 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.286415 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 249.714027 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 3465 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-14847 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3467 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3467 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.760023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.110727 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 15.816281 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 15 0.43% 0.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 5 0.14% 0.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 2 0.06% 0.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 8 0.23% 0.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 2898 83.59% 84.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 92 2.65% 87.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 31 0.89% 88.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 31 0.89% 88.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 12 0.35% 89.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 9 0.26% 89.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 66 1.90% 91.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.03% 91.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 98 2.83% 94.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.17% 94.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.09% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 10 0.29% 94.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 79 2.28% 97.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.03% 97.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.03% 97.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 16 0.46% 97.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 63 1.82% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.03% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.03% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.03% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.03% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 9 0.26% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.06% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.06% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3467 # Writes before turning the bus around for reads -system.physmem.totQLat 959600537 # Total ticks spent queuing -system.physmem.totMemAccLat 2473363037 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 403670000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11885.95 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 3967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3423 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 34726 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 271.798192 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 162.605386 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 302.611478 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14316 41.23% 41.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8644 24.89% 66.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3494 10.06% 76.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1847 5.32% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1254 3.61% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 948 2.73% 87.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 605 1.74% 89.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 474 1.36% 90.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3144 9.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 34726 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3354 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.146989 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 204.184053 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 3351 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.03% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5632-6143 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9728-10239 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3354 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3354 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.820811 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.786469 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.927460 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 11 0.33% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.21% 0.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 8 0.24% 0.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 2796 83.36% 84.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 40 1.19% 85.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 43 1.28% 86.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 85 2.53% 89.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 115 3.43% 92.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 62 1.85% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 12 0.36% 94.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.18% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.33% 95.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.12% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.06% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.06% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 122 3.64% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.06% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.03% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.06% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.09% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.03% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.03% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.03% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.03% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.24% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3354 # Writes before turning the bus around for reads +system.physmem.totQLat 822128507 # Total ticks spent queuing +system.physmem.totMemAccLat 2278009757 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 388235000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10588.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30635.95 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.01 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.94 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.01 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.94 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29338.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.97 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.87 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.97 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtil 0.01 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing -system.physmem.avgWrQLen 2.44 # Average write queue length when enqueuing -system.physmem.readRowHits 63933 # Number of row buffer hits during reads -system.physmem.writeRowHits 56252 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.56 # Row buffer hit rate for writes -system.physmem.avgGap 32873033.35 # Average gap between requests -system.physmem.pageHitRate 76.95 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 136329480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 74217000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 310923600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 246505680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250343745600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 95969299725 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2238262188750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2585343209835 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.919112 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3685961618484 # Time in different power states -system.physmem_0.memoryStateTime::REF 127987600000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 3.53 # Average write queue length when enqueuing +system.physmem.readRowHits 61504 # Number of row buffer hits during reads +system.physmem.writeRowHits 51248 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.36 # Row buffer hit rate for writes +system.physmem.avgGap 34834089.20 # Average gap between requests +system.physmem.pageHitRate 76.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 129729600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 70607625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 297164400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 234880560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250511061840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 94606706745 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2237443433250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2583293584020 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.968853 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3690534116962 # Time in different power states +system.physmem_0.memoryStateTime::REF 128073140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 19335436766 # Time in different power states +system.physmem_0.memoryStateTime::ACT 17232140788 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 135762480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 73895250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 318801600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 242358480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250343745600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 95643572940 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2233792245000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2580550381350 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.048855 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3686442435237 # Time in different power states -system.physmem_1.memoryStateTime::REF 127987600000 # Time in different power states +system.physmem_1.actEnergy 132798960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 72319500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 308451000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 217637280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250511061840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 94562869185 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2235084583500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2580889721265 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.037449 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3690605945988 # Time in different power states +system.physmem_1.memoryStateTime::REF 128073140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18834570263 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17153124512 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1094391152 # number of cpu cycles simulated +system.cpu0.numCycles 902046715 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.committedInsts 74122895 # Number of instructions committed -system.cpu0.committedOps 150851838 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 138677128 # Number of integer alu accesses +system.cpu0.committedInsts 73959427 # Number of instructions committed +system.cpu0.committedOps 150307597 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 138246700 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1057792 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14577160 # number of instructions that are conditional controls -system.cpu0.num_int_insts 138677128 # number of integer instructions +system.cpu0.num_func_calls 1066960 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14495182 # number of instructions that are conditional controls +system.cpu0.num_int_insts 138246700 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 255069053 # number of times the integer registers were read -system.cpu0.num_int_register_writes 118998749 # number of times the integer registers were written +system.cpu0.num_int_register_reads 254560897 # number of times the integer registers were read +system.cpu0.num_int_register_writes 118518911 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 85946991 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 57322770 # number of times the CC registers were written -system.cpu0.num_mem_refs 14647041 # number of memory refs -system.cpu0.num_load_insts 10728215 # Number of load instructions -system.cpu0.num_store_insts 3918826 # Number of store instructions -system.cpu0.num_idle_cycles 1038841182.346683 # Number of idle cycles -system.cpu0.num_busy_cycles 55549969.653317 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050759 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949241 # Percentage of idle cycles -system.cpu0.Branches 16022842 # Number of branches fetched -system.cpu0.op_class::No_OpClass 99424 0.07% 0.07% # Class of executed instruction -system.cpu0.op_class::IntAlu 135987078 90.15% 90.21% # Class of executed instruction -system.cpu0.op_class::IntMult 67182 0.04% 90.26% # Class of executed instruction -system.cpu0.op_class::IntDiv 53535 0.04% 90.29% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.29% # Class of executed instruction -system.cpu0.op_class::MemRead 10726354 7.11% 97.40% # Class of executed instruction -system.cpu0.op_class::MemWrite 3918826 2.60% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 85690938 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 57098279 # number of times the CC registers were written +system.cpu0.num_mem_refs 14889374 # number of memory refs +system.cpu0.num_load_insts 10848208 # Number of load instructions +system.cpu0.num_store_insts 4041166 # Number of store instructions +system.cpu0.num_idle_cycles 853760386.040518 # Number of idle cycles +system.cpu0.num_busy_cycles 48286328.959482 # Number of busy cycles +system.cpu0.not_idle_fraction 0.053530 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.946470 # Percentage of idle cycles +system.cpu0.Branches 15948833 # Number of branches fetched +system.cpu0.op_class::No_OpClass 97349 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 135200596 89.95% 90.01% # Class of executed instruction +system.cpu0.op_class::IntMult 70034 0.05% 90.06% # Class of executed instruction +system.cpu0.op_class::IntDiv 52579 0.03% 90.10% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.10% # Class of executed instruction +system.cpu0.op_class::MemRead 10846498 7.22% 97.31% # Class of executed instruction +system.cpu0.op_class::MemWrite 4041166 2.69% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 150852399 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1650433 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999438 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 20513006 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1650945 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 12.425009 # Average number of references to valid blocks. +system.cpu0.op_class::total 150308222 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1651251 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.996861 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 20452818 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1651763 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 12.382417 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 375.993952 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 118.546121 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 17.459365 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.734363 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.231535 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.034100 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 417.977148 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 68.931894 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 25.087819 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.816362 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.134633 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.049000 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 91826885 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 91826885 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5461220 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2267893 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4648498 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 12377611 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3770628 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1595824 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2705065 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8071517 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 23383 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10395 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 28426 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 62204 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9231848 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3863717 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7353563 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 20449128 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9255231 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3874112 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7381989 # number of overall hits -system.cpu0.dcache.overall_hits::total 20511332 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 389922 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 165729 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 747444 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1303095 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 142600 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 62561 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 117557 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 322718 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 161787 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 68211 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 176838 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 406836 # number of SoftPFReq misses -system.cpu0.dcache.demand_misses::cpu0.data 532522 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 228290 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 865001 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1625813 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 694309 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 296501 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1041839 # number of overall misses -system.cpu0.dcache.overall_misses::total 2032649 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2394641000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12467623500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14862264500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 3804839500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 5678837917 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 9483677417 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 6199480500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 18146461417 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 24345941917 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 6199480500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 18146461417 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 24345941917 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5851142 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2433622 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 5395942 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13680706 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3913228 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1658385 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2822622 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8394235 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 185170 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 78606 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 205264 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 469040 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9764370 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4092007 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 8218564 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 22074941 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9949540 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4170613 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 8423828 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 22543981 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.066640 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.068100 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.138520 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.095251 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036441 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.037724 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.041648 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.038445 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.873721 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.867758 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.861515 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.867380 # miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.054537 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.055789 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.105250 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.073650 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069783 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.071093 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.123678 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.090164 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14449.136844 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16680.344614 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11405.357629 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 60818.073560 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48307.101381 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 29386.887056 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27156.163213 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20978.543859 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14974.626182 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20908.801319 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17417.721372 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11977.445155 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 181022 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 183 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 19401 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.330550 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 183 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 1556926 # number of writebacks -system.cpu0.dcache.writebacks::total 1556926 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 57 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 343172 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 343229 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1684 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 31593 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 33277 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1741 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 374765 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 376506 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1741 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 374765 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 376506 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 165672 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 404272 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 569944 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 60877 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 85964 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 146841 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 68211 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 173456 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 241667 # number of SoftPFReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 226549 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 490236 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 716785 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 294760 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 663692 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 958452 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 175893 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 193266 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 369159 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 2325 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 3182 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 5507 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 178218 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 196448 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 374666 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2228026000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5917391000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 8145417000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3569732500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4893697918 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8463430418 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 1135489000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2736217500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3871706500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 5797758500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10811088918 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16608847418 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6933247500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 13547306418 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 20480553918 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30576787000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 32909630500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63486417500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30576787000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 32909630500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 63486417500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.068076 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.074921 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041660 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036709 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.030455 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017493 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.867758 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.845039 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.515238 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.055364 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.059650 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032471 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.070675 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.078787 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.042515 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13448.416148 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14637.152709 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14291.609351 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 58638.443090 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 56927.294193 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 57636.698320 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16646.713873 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15774.706554 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16020.832385 # average SoftPFReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25591.631391 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 22052.825411 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23171.309972 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23521.670172 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20412.038141 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21368.366823 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173837.429574 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170281.531671 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171975.808527 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171569.577708 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 167523.367507 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 169448.035050 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 963636 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.754232 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 132561753 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 964148 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 137.491083 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 151167437500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 262.116311 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 168.300962 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 80.336959 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.511946 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.328713 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.156908 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997567 # Average percentage of cache occupancy +system.cpu0.dcache.tags.tag_accesses 91512129 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 91512129 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5600779 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2451508 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4254630 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 12306917 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3889675 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1677991 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2514442 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8082108 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 23860 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10736 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 27491 # 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number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8405281 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 182683 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 79632 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 206955 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 469270 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10024391 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4370204 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7601221 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21995816 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10207074 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4449836 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7808176 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 22465086 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064673 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.067151 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.144714 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.094449 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036339 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.036868 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.042740 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.038449 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.869391 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.865180 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.867164 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.867695 # miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.053264 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.055079 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.109476 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.073050 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067871 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069576 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.129558 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.089649 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13944.498277 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 13432.641231 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9450.441642 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42543.910311 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31947.930700 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19554.100841 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21576.354837 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 15930.534003 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 11482.585122 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16774.934483 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 13104.396582 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 9161.048966 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 149019 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 19247 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.742453 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 1557863 # number of writebacks +system.cpu0.dcache.writebacks::total 1557863 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 49 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 325442 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 325491 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1624 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 29845 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 31469 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1673 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 355287 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 356960 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1673 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 355287 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 356960 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 176423 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 394442 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 570865 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62609 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 82420 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 145029 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 68896 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 176057 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 244953 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 239032 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 476862 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 715894 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 307928 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 652919 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 960847 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 175968 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 193387 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 369355 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 2768 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4032 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 6800 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 178736 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 197419 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 376155 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2283564500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5222076000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7505640500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2580696991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2983674940 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5564371931 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 1020231000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2452891500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3473122500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4864261491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 8205750940 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13070012431 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5884492491 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10658642440 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16543134931 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30715210000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33235671500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63950881500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30715210000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33235671500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 63950881500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.067133 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.079293 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.042005 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035936 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031378 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017255 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.865180 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.850702 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.521987 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.054696 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.062735 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032547 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069200 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.083620 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.042771 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12943.689315 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13239.147961 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13147.837930 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41219.265457 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 36200.860713 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38367.305373 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14808.276242 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13932.371334 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14178.730205 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20349.833876 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17207.810520 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18256.910145 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19109.962365 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16324.601428 # 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Cycle average of tags in use +system.cpu0.icache.tags.total_refs 133067935 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 957218 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 139.015287 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 150766905000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 303.387688 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.665696 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 141.741316 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.592554 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.128253 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.276839 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997646 # 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number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 588814 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2116162000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5491871486 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7608033486 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2116162000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5491871486 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7608033486 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2116162000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5491871486 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7608033486 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004200 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.099647 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004391 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004200 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.099647 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004391 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004200 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.099647 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004391 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12855.141663 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12946.481327 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12920.945300 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12855.141663 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12946.481327 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12920.945300 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12855.141663 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12946.481327 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12920.945300 # average overall mshr miss latency +system.cpu1.numCycles 2608017339 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 34908148 # Number of instructions committed -system.cpu1.committedOps 67674268 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 62730034 # Number of integer alu accesses +system.cpu1.committedInsts 35627427 # Number of instructions committed +system.cpu1.committedOps 68998423 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64051827 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 443264 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6458850 # number of instructions that are conditional controls -system.cpu1.num_int_insts 62730034 # number of integer instructions +system.cpu1.num_func_calls 468203 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6587290 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64051827 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 115909409 # number of times the integer registers were read -system.cpu1.num_int_register_writes 54110121 # number of times the integer registers were written +system.cpu1.num_int_register_reads 118624529 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55196381 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 35540821 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26573137 # number of times the CC registers were written -system.cpu1.num_mem_refs 4349098 # number of memory refs -system.cpu1.num_load_insts 2688265 # Number of load instructions -system.cpu1.num_store_insts 1660833 # Number of store instructions -system.cpu1.num_idle_cycles 2478843361.099947 # Number of idle cycles -system.cpu1.num_busy_cycles 129174831.900053 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049530 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950470 # Percentage of idle cycles -system.cpu1.Branches 7053791 # Number of branches fetched -system.cpu1.op_class::No_OpClass 19486 0.03% 0.03% # Class of executed instruction -system.cpu1.op_class::IntAlu 63254522 93.47% 93.50% # Class of executed instruction -system.cpu1.op_class::IntMult 28142 0.04% 93.54% # Class of executed instruction -system.cpu1.op_class::IntDiv 23340 0.03% 93.57% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.57% # Class of executed instruction -system.cpu1.op_class::MemRead 2688234 3.97% 97.55% # Class of executed instruction -system.cpu1.op_class::MemWrite 1660833 2.45% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36419223 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27076219 # number of times the CC registers were written +system.cpu1.num_mem_refs 4628508 # number of memory refs +system.cpu1.num_load_insts 2883555 # Number of load instructions +system.cpu1.num_store_insts 1744953 # Number of store instructions +system.cpu1.num_idle_cycles 2479194289.218051 # Number of idle cycles +system.cpu1.num_busy_cycles 128823049.781949 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049395 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950605 # Percentage of idle cycles +system.cpu1.Branches 7222524 # Number of branches fetched +system.cpu1.op_class::No_OpClass 27694 0.04% 0.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 64285165 93.17% 93.21% # Class of executed instruction +system.cpu1.op_class::IntMult 28263 0.04% 93.25% # Class of executed instruction +system.cpu1.op_class::IntDiv 29212 0.04% 93.29% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.29% # Class of executed instruction +system.cpu1.op_class::MemRead 2883455 4.18% 97.47% # Class of executed instruction +system.cpu1.op_class::MemWrite 1744953 2.53% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 67674557 # Class of executed instruction -system.cpu2.branchPred.lookups 31525113 # Number of BP lookups -system.cpu2.branchPred.condPredicted 31525113 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 914299 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 30286127 # Number of BTB lookups +system.cpu1.op_class::total 68998742 # Class of executed instruction +system.cpu2.branchPred.lookups 31199361 # Number of BP lookups +system.cpu2.branchPred.condPredicted 31199361 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 851763 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 30042490 # Number of BTB lookups system.cpu2.branchPred.BTBHits 0 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 909220 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 192056 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 30286127 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 24878264 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 5407863 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 624695 # Number of mispredicted indirect branches. -system.cpu2.numCycles 158988186 # number of cpu cycles simulated +system.cpu2.branchPred.usedRAS 863549 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 181695 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 30042490 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 24994810 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 5047680 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 585906 # Number of mispredicted indirect branches. +system.cpu2.numCycles 154015967 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 11233712 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 154626280 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 31525113 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 25787484 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 144779980 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1869040 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 156982 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 17620 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 10414 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 116139 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 25 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 930 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4603960 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 388777 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3488 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 157249670 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.926249 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.092305 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10525182 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 153136013 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 31199361 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 25858359 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 140984091 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1735783 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 143780 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 16316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 7923 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 66490 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 26 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 488 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4257020 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 368090 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3025 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 152611536 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.969429 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.111517 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 99582992 63.33% 63.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 964125 0.61% 63.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23469226 14.92% 78.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 593390 0.38% 79.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 847641 0.54% 79.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 856615 0.54% 80.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 597782 0.38% 80.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 744225 0.47% 81.18% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 29593674 18.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 95212585 62.39% 62.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 896814 0.59% 62.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23718994 15.54% 78.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 549190 0.36% 78.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 778244 0.51% 79.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 799023 0.52% 79.91% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 532989 0.35% 80.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 720428 0.47% 80.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 29403269 19.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 157249670 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.198286 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.972565 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10427860 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 93427042 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 27103012 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4279379 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 935172 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 295647983 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 935172 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12376342 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 77584212 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4407531 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 29150273 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 11718994 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 291618982 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 179072 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5037051 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 41813 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 5015695 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 346213395 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 638570663 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 392106863 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 174 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 316477400 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 29735995 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 200602 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 204223 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 19899289 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 7937355 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 4436501 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 473319 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 392747 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 284970653 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 434962 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 278681427 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 430528 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 21014667 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 31387480 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 100533 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 157249670 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.772223 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.401212 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 152611536 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.202572 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.994287 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10167862 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 90185488 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 25340442 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4831486 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 868543 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 293911699 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 868543 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12378234 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 76415835 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 3891181 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 27683635 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 10156457 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 290176548 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 179480 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5269403 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 20140 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 2921556 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 344456385 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 633379614 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 389227303 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 120 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 317474127 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 26982256 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 189266 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 192828 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 22388341 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 7330700 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 4149427 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 414211 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 341335 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 283979915 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 425629 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 278392066 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 405323 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 19156154 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 28402257 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 93435 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 152611536 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.824188 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.420511 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 94617673 60.17% 60.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5061925 3.22% 63.39% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3636668 2.31% 65.70% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3244908 2.06% 67.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 23176493 14.74% 82.50% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2489677 1.58% 84.09% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 24037063 15.29% 99.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 647397 0.41% 99.79% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 337866 0.21% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 90358507 59.21% 59.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 4845557 3.18% 62.38% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3452107 2.26% 64.65% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3415281 2.24% 66.88% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 22680576 14.86% 81.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2703807 1.77% 83.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 24243891 15.89% 99.40% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 602713 0.39% 99.80% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 309097 0.20% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 157249670 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 152611536 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1411870 83.47% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 83.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 217423 12.85% 96.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 62231 3.68% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1789790 87.09% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 87.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 208308 10.14% 97.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 57058 2.78% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 115362 0.04% 0.04% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 267146597 95.86% 95.90% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 53270 0.02% 95.92% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 46547 0.02% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 45 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.94% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 7662410 2.75% 98.69% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3657196 1.31% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 101487 0.04% 0.04% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 267636712 96.14% 96.17% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 50542 0.02% 96.19% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 41904 0.02% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 34 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 7148788 2.57% 98.77% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3412599 1.23% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 278681427 # Type of FU issued -system.cpu2.iq.rate 1.752844 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1691524 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.006070 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 716734322 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 306424660 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 275127315 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 254 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 266 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 90 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 280257468 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 121 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 646730 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 278392066 # Type of FU issued +system.cpu2.iq.rate 1.807553 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2055156 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007382 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 711855943 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 303565687 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 275033680 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 203 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 174 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 83 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 280345636 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 99 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 602114 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2931016 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 14365 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5986 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1611688 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2634716 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 13210 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5396 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1520030 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 711699 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 22857 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 706535 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 19267 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 935172 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 70777745 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 3837930 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 285405615 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 65161 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 7937355 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 4436501 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 268097 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 149220 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3382117 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5986 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 291238 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 909786 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1201024 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 276567393 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 7166969 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1944228 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 868543 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 71343644 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 2239546 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 284405544 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 59883 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 7330707 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 4149427 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 256703 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 145075 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1788429 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5396 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 270430 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 847907 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1118337 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 276410000 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6693207 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1826872 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 10526010 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27939467 # Number of branches executed -system.cpu2.iew.exec_stores 3359041 # Number of stores executed -system.cpu2.iew.exec_rate 1.739547 # Inst execution rate -system.cpu2.iew.wb_sent 276091917 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 275127405 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 214085717 # num instructions producing a value -system.cpu2.iew.wb_consumers 350028244 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.730490 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611624 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 20995894 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 334429 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 920745 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 153916196 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.717759 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.626761 # Number of insts commited each cycle +system.cpu2.iew.exec_refs 9818298 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27929809 # Number of branches executed +system.cpu2.iew.exec_stores 3125091 # Number of stores executed +system.cpu2.iew.exec_rate 1.794684 # Inst execution rate +system.cpu2.iew.wb_sent 275971770 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 275033763 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 214243041 # num instructions producing a value +system.cpu2.iew.wb_consumers 350261962 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.785748 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611665 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 19130941 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 332194 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 855634 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 149565660 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.773464 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.653305 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 97481519 63.33% 63.33% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4123104 2.68% 66.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1212307 0.79% 66.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24190287 15.72% 82.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1026189 0.67% 83.18% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 685449 0.45% 83.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 433933 0.28% 83.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 22970494 14.92% 98.84% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1792914 1.16% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 93221920 62.33% 62.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 3884084 2.60% 64.93% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1108913 0.74% 65.67% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24362236 16.29% 81.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 961331 0.64% 82.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 644406 0.43% 83.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 409687 0.27% 83.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23249373 15.54% 98.85% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1723710 1.15% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 153916196 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 133896717 # Number of instructions committed -system.cpu2.commit.committedOps 264390948 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 149565660 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 134145476 # Number of instructions committed +system.cpu2.commit.committedOps 265249385 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 7831152 # Number of memory references committed -system.cpu2.commit.loads 5006339 # Number of loads committed -system.cpu2.commit.membars 148306 # Number of memory barriers committed -system.cpu2.commit.branches 26996003 # Number of branches committed +system.cpu2.commit.refs 7325387 # Number of memory references committed +system.cpu2.commit.loads 4695990 # Number of loads committed +system.cpu2.commit.membars 151817 # Number of memory barriers committed +system.cpu2.commit.branches 27066281 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 241389293 # Number of committed integer instructions. -system.cpu2.commit.function_calls 403260 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 53378 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 256414257 96.98% 97.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 47916 0.02% 97.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 44914 0.02% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.04% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5005654 1.89% 98.93% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2824813 1.07% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 241954507 # Number of committed integer instructions. +system.cpu2.commit.function_calls 387238 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 47651 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 257791047 97.19% 97.21% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 45496 0.02% 97.22% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 40577 0.02% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.24% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 4695201 1.77% 99.01% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2629397 0.99% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 264390948 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1792914 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 437472336 # The number of ROB reads -system.cpu2.rob.rob_writes 574170009 # The number of ROB writes -system.cpu2.timesIdled 144166 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1738516 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4904586400 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 133896717 # Number of Instructions Simulated -system.cpu2.committedOps 264390948 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.187394 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.187394 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.842180 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.842180 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 366421934 # number of integer regfile reads -system.cpu2.int_regfile_writes 220787905 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73116 # number of floating regfile reads +system.cpu2.commit.op_class_0::total 265249385 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1723710 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 432186718 # The number of ROB reads +system.cpu2.rob.rob_writes 571865889 # The number of ROB writes +system.cpu2.timesIdled 138407 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1404431 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4914533165 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 134145476 # Number of Instructions Simulated +system.cpu2.committedOps 265249385 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.148126 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.148126 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.870984 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.870984 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 365815904 # number of integer regfile reads +system.cpu2.int_regfile_writes 220629753 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73051 # number of floating regfile reads system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes -system.cpu2.cc_regfile_reads 138717483 # number of cc regfile reads -system.cpu2.cc_regfile_writes 106912566 # number of cc regfile writes -system.cpu2.misc_regfile_reads 90334480 # number of misc regfile reads -system.cpu2.misc_regfile_writes 137702 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3545370 # Transaction distribution -system.iobus.trans_dist::ReadResp 3545370 # Transaction distribution -system.iobus.trans_dist::WriteReq 57732 # Transaction distribution -system.iobus.trans_dist::WriteResp 57732 # Transaction distribution -system.iobus.trans_dist::MessageReq 1681 # Transaction distribution -system.iobus.trans_dist::MessageResp 1681 # Transaction distribution +system.cpu2.cc_regfile_reads 138624705 # number of cc regfile reads +system.cpu2.cc_regfile_writes 107019387 # number of cc regfile writes +system.cpu2.misc_regfile_reads 89775262 # number of misc regfile reads +system.cpu2.misc_regfile_writes 129105 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3544820 # Transaction distribution +system.iobus.trans_dist::ReadResp 3544820 # Transaction distribution +system.iobus.trans_dist::WriteReq 57702 # Transaction distribution +system.iobus.trans_dist::WriteResp 57702 # Transaction distribution +system.iobus.trans_dist::MessageReq 1686 # Transaction distribution +system.iobus.trans_dist::MessageResp 1686 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7066646 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7065558 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1126 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27898 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27910 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7110960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3362 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3362 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7209566 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7109792 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3372 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3372 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7208416 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3533323 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3532779 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2252 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13949 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13955 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3561640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027760 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027760 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6724 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6724 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6596124 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2248264 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3561050 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6744 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6744 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6595586 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2583988 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 36000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4543500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4499500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 934000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 934500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 19000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 14500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 17500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 199976500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 199160500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 364000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 352000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 124000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 77500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9295000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 13461500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 6000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 136645287 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 119181081 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 1156000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 1081000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 281326000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 283709000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 29430000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 25934000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 922000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1055000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47567 # number of replacements -system.iocache.tags.tagsinuse 0.087469 # Cycle average of tags in use +system.iocache.tags.replacements 47571 # number of replacements +system.iocache.tags.tagsinuse 0.093993 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47583 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47587 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5004689010009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.087469 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005467 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005467 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5004596403009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.093993 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005875 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005875 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428598 # Number of tag accesses -system.iocache.tags.data_accesses 428598 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 902 # number of ReadReq misses -system.iocache.ReadReq_misses::total 902 # number of ReadReq misses +system.iocache.tags.tag_accesses 428634 # Number of tag accesses +system.iocache.tags.data_accesses 428634 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses +system.iocache.ReadReq_misses::total 906 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47622 # number of demand (read+write) misses -system.iocache.demand_misses::total 47622 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47622 # number of overall misses -system.iocache.overall_misses::total 47622 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 126421308 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 126421308 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3306334979 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 3306334979 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 3432756287 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 3432756287 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 3432756287 # number of overall miss cycles -system.iocache.overall_miss_latency::total 3432756287 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 902 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 902 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47626 # number of demand (read+write) misses +system.iocache.demand_misses::total 47626 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47626 # number of overall misses +system.iocache.overall_misses::total 47626 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 120463801 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 120463801 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 2718328280 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2718328280 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 2838792081 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 2838792081 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 2838792081 # number of overall miss cycles +system.iocache.overall_miss_latency::total 2838792081 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47622 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47622 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47622 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47622 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47626 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47626 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47626 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47626 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1263,529 +1274,587 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 140156.660754 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 140156.660754 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 70769.156229 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 70769.156229 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 72083.412855 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 72083.412855 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 72083.412855 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 72083.412855 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 266 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 132962.252759 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 132962.252759 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 58183.396404 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 58183.396404 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 59605.931235 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 59605.931235 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 59605.931235 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 59605.931235 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 354 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 20 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.300000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.642857 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 739 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 26320 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 26320 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 27059 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 27059 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 27059 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 27059 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 89471308 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 89471308 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1989257405 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1989257405 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 2078728713 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2078728713 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 2078728713 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2078728713 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.819290 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.819290 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.563356 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.563356 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.568204 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.568204 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.568204 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.568204 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 121070.782138 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 121070.782138 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75579.688640 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75579.688640 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76822.081858 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76822.081858 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76822.081858 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76822.081858 # average overall mshr miss latency -system.l2c.tags.replacements 102044 # number of replacements -system.l2c.tags.tagsinuse 64688.139772 # Cycle average of tags in use -system.l2c.tags.total_refs 4947315 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 166296 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 29.750054 # Average number of references to valid blocks. +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 711 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 22880 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 22880 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 23591 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 23591 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 23591 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 23591 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 84913801 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 84913801 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1572541335 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1572541335 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 1657455136 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1657455136 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 1657455136 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1657455136 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.784768 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.784768 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.489726 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.489726 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.495339 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.495339 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.495339 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.495339 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 119428.693390 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 119428.693390 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68729.953453 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68729.953453 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 70257.943114 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70257.943114 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 70257.943114 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70257.943114 # average overall mshr miss latency +system.l2c.tags.replacements 102742 # number of replacements +system.l2c.tags.tagsinuse 64807.232548 # Cycle average of tags in use +system.l2c.tags.total_refs 4917874 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 166881 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 29.469346 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50751.500379 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134888 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1938.182385 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5577.575685 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 363.614942 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1703.759135 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 24.817109 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 802.838382 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3525.716867 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.774406 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50676.768734 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131121 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1597.619840 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5190.937172 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003338 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 233.485852 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1577.800752 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 27.152241 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.957955 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1336.692253 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4165.683291 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.773266 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.029574 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.085107 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.005548 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.025997 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000379 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.012250 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.053798 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.987063 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64252 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 267 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2776 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7602 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53531 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.980408 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 43883599 # Number of tag accesses -system.l2c.tags.data_accesses 43883599 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 20977 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 11744 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 3358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1300 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 142732 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 18004 # number of ReadReq hits -system.l2c.ReadReq_hits::total 198115 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.024378 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.079207 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003563 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.024075 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000414 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.020396 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.063563 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.988880 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64139 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 571 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3312 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7441 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52737 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.978683 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 43620877 # Number of tag accesses +system.l2c.tags.data_accesses 43620877 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 21700 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 11096 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4762 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2301 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 121788 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 15231 # number of ReadReq hits +system.l2c.ReadReq_hits::total 176878 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.WritebackDirty_hits::writebacks 1556926 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 1556926 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 962606 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 962606 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 145 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 47 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 88 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 280 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 71404 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 36289 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 53236 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 160929 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 355369 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 154744 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 439091 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 949204 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 535670 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 229279 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 564722 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 1329671 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 20977 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 11746 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 355369 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 607074 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 3358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1300 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 154744 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 265568 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 142732 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 18004 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 439091 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 617958 # number of demand (read+write) hits -system.l2c.demand_hits::total 2637921 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 20977 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 11746 # number of overall hits -system.l2c.overall_hits::cpu0.inst 355369 # number of overall hits -system.l2c.overall_hits::cpu0.data 607074 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 3358 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1300 # number of overall hits -system.l2c.overall_hits::cpu1.inst 154744 # number of overall hits -system.l2c.overall_hits::cpu1.data 265568 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 142732 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 18004 # number of overall hits -system.l2c.overall_hits::cpu2.inst 439091 # number of overall hits -system.l2c.overall_hits::cpu2.data 617958 # number of overall hits -system.l2c.overall_hits::total 2637921 # number of overall hits -system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 53 # number of ReadReq misses -system.l2c.ReadReq_misses::total 58 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 712 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 228 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 393 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1333 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 70339 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 24315 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 32300 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 126954 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 8126 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1320 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 5463 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 14909 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 16039 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 4604 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 12954 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 33597 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8126 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 86378 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1320 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 28919 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 53 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 5463 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 45254 # number of demand (read+write) misses -system.l2c.demand_misses::total 175518 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.inst 8126 # number of overall misses -system.l2c.overall_misses::cpu0.data 86378 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1320 # number of overall misses -system.l2c.overall_misses::cpu1.data 28919 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 53 # number of overall misses -system.l2c.overall_misses::cpu2.inst 5463 # number of overall misses -system.l2c.overall_misses::cpu2.data 45254 # number of overall misses -system.l2c.overall_misses::total 175518 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 7207500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 7207500 # 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Transaction distribution -system.membus.trans_dist::CleanEvict 8953 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1610 # Transaction distribution -system.membus.trans_dist::UpgradeResp 846 # Transaction distribution -system.membus.trans_dist::ReadExReq 126677 # Transaction distribution -system.membus.trans_dist::ReadExResp 126677 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 49464 # Transaction distribution -system.membus.trans_dist::MessageReq 1681 # Transaction distribution -system.membus.trans_dist::MessageResp 1681 # Transaction distribution -system.membus.trans_dist::BadAddressError 190 # Transaction distribution +system.l2c.writebacks::writebacks 94739 # number of writebacks +system.l2c.writebacks::total 94739 # number of writebacks +system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 1 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 62 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 293 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 283 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 576 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 27814 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 28615 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 56429 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1957 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5042 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 6999 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 4841 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 9660 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 14501 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1957 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 32655 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 62 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 5042 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 38275 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 77993 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1957 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 32655 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 62 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 5042 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 38275 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 77993 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 175968 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2.data 193387 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 369355 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2768 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 4032 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 6800 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 178736 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 197419 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 376155 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 73500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 4800500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 73500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 4947500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 6159500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 5718500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 11878000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1836096500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1998176500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 3834273000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 139728500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 379329000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 519057500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 360827000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 746886000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 1107713000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 73500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 139728500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2196923500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 4800500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 73500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 379329000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2745062500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5465991000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 73500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 139728500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2196923500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 4800500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 73500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 379329000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2745062500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5465991000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28515609500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30818304000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59333913500 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28515609500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30818304000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59333913500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000434 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000509 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000066 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000362 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.816156 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.820290 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.355995 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.446725 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.348470 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.194490 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011888 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.011887 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.007312 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.019733 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.016934 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.010648 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000434 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011888 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.106167 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000509 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000066 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011887 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.058652 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.027993 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000434 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011888 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.106167 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000509 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000066 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011887 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.058652 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.027993 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77427.419355 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 77304.687500 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21022.184300 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20206.713781 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20621.527778 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66013.392536 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69829.687227 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 67948.625707 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71399.335718 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 75233.835779 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74161.665952 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74535.633134 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 77317.391304 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76388.731812 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71399.335718 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67276.787628 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77427.419355 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 75233.835779 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71719.464402 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 70083.097201 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71399.335718 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67276.787628 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77427.419355 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 75233.835779 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71719.464402 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 70083.097201 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162049.972154 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 159360.784334 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160641.966401 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 159540.380785 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 156106.068818 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 157737.936489 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 375707 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 160970 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 1170 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 5049003 # Transaction distribution +system.membus.trans_dist::ReadResp 5098173 # Transaction distribution +system.membus.trans_dist::WriteReq 13918 # Transaction distribution +system.membus.trans_dist::WriteResp 13918 # Transaction distribution +system.membus.trans_dist::WritebackDirty 141406 # Transaction distribution +system.membus.trans_dist::CleanEvict 8879 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1627 # Transaction distribution +system.membus.trans_dist::UpgradeResp 897 # Transaction distribution +system.membus.trans_dist::ReadExReq 127688 # Transaction distribution +system.membus.trans_dist::ReadExResp 127688 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 49387 # Transaction distribution +system.membus.trans_dist::MessageReq 1686 # Transaction distribution +system.membus.trans_dist::MessageResp 1686 # Transaction distribution +system.membus.trans_dist::BadAddressError 217 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::InvalidateResp 20400 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3362 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3362 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7110960 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3044366 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 454255 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 380 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10609961 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 116195 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 116195 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10729518 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6724 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6724 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3561640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6088729 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17196864 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 26847233 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3025472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3025472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 29879429 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 601 # Total snoops (count) -system.membus.snoop_fanout::samples 5453391 # Request fanout histogram -system.membus.snoop_fanout::mean 1.000308 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.017554 # Request fanout histogram +system.membus.trans_dist::InvalidateResp 23840 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7109792 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3016050 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 434 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10583090 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 119675 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 119675 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10706137 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6744 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6744 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3561050 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6032097 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17304384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 26897531 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3027520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3027520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 29931795 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 596 # Total snoops (count) +system.membus.snoop_fanout::samples 5365465 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001972 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.044366 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5451710 99.97% 99.97% # Request fanout histogram -system.membus.snoop_fanout::2 1681 0.03% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5354883 99.80% 99.80% # Request fanout histogram +system.membus.snoop_fanout::1 10582 0.20% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 5453391 # Request fanout histogram -system.membus.reqLayer0.occupancy 216495500 # Layer occupancy (ticks) +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 5365465 # Request fanout histogram +system.membus.reqLayer0.occupancy 219694000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 286493500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 286587500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2249736 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2585012 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 499824904 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 464604174 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 233000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 267500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1327736 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1530012 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1171418252 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1157102500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 3779540 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 3622087 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -1795,61 +1864,60 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.snoop_filter.tot_requests 5271274 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2656110 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1659 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1097 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1097 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5251700 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2642649 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1467 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 797 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 797 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 5290849 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7618295 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13945 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13945 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 1632371 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 963636 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 98691 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1613 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1613 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 287883 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 287883 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 964168 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1364007 # Transaction distribution -system.toL2Bus.trans_dist::MessageReq 922 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 190 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 26320 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2891930 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15111487 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 71145 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 360729 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 18435291 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 123376768 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 214967937 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 268760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 1369184 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 339982649 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 221710 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9176706 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.004700 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.068396 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5252356 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7571420 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13920 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13920 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1604861 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 956706 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 97687 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1618 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1618 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 290139 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 290139 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 957232 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1362205 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 217 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4436 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2871137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15084519 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 67785 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 321441 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18344882 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 122489920 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 215022523 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 256088 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 1230880 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 338999411 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 130547 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9049191 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.003896 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.062298 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 9133575 99.53% 99.53% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 43131 0.47% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 9013933 99.61% 99.61% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 35258 0.39% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9176706 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3345415999 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9049191 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3319937995 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 351896 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 330397 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 901439087 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 883646129 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1808797701 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1813359528 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23276465 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 21309973 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 164740668 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 140489176 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |