diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-27 16:08:05 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-27 16:08:05 -0400 |
| commit | b1a58933e07d7af0eb5f43942f8ad9bc93f28039 (patch) | |
| tree | 21f36b849ba0aed06ec18ed45aef46feeacd7532 /tests/long/fs/10.linux-boot/ref | |
| parent | 630068be6f7b6dc5c612867c764c37e41fd90a4a (diff) | |
| download | gem5-b1a58933e07d7af0eb5f43942f8ad9bc93f28039.tar.xz | |
stats: update stats for icache change not allowing dirty data
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref')
24 files changed, 5148 insertions, 6219 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 1c28eff64..028711e47 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -1005,7 +1005,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port[0] +master=system.bridge.slave system.physmem.port slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 11f244941..acdd4bc1c 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,12 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 11:07:21 +gem5 compiled Jul 26 2012 21:20:05 +gem5 started Jul 26 2012 22:30:48 gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 112168000 -Exiting @ tick 1900530800500 because m5_exit instruction encountered +Exiting @ tick 1900530295500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 3f76d2026..a7a1d7396 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.900531 # Number of seconds simulated -sim_ticks 1900530800500 # Number of ticks simulated -final_tick 1900530800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.900530 # Number of seconds simulated +sim_ticks 1900530295500 # Number of ticks simulated +final_tick 1900530295500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119697 # Simulator instruction rate (inst/s) -host_op_rate 119697 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3968630665 # Simulator tick rate (ticks/s) -host_mem_usage 303044 # Number of bytes of host memory used -host_seconds 478.89 # Real time elapsed on the host -sim_insts 57321719 # Number of instructions simulated -sim_ops 57321719 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 875648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24657536 # Number of bytes read from this memory +host_inst_rate 128893 # Simulator instruction rate (inst/s) +host_op_rate 128893 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4273489918 # Simulator tick rate (ticks/s) +host_mem_usage 307500 # Number of bytes of host memory used +host_seconds 444.73 # Real time elapsed on the host +sim_insts 57321882 # Number of instructions simulated +sim_ops 57321882 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 875200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24658176 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 107456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 693056 # Number of bytes read from this memory -system.physmem.bytes_read::total 28984512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 875648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 107456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 983104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7921792 # Number of bytes written to this memory -system.physmem.bytes_written::total 7921792 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13682 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385274 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 108032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 692736 # Number of bytes read from this memory +system.physmem.bytes_read::total 28984960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 875200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 108032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 983232 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7922432 # Number of bytes written to this memory +system.physmem.bytes_written::total 7922432 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13675 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385284 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1679 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10829 # Number of read requests responded to by this memory -system.physmem.num_reads::total 452883 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123778 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123778 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 460739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12974026 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1688 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10824 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452890 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123788 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123788 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 460503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12974366 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1394777 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 364664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15250746 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 460739 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56540 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4168200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4168200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4168200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 460739 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12974026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56843 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 364496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15250986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 460503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517346 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4168538 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4168538 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4168538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 460503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12974366 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1394777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 364664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19418945 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 345959 # number of replacements -system.l2c.tagsinuse 65264.030293 # Cycle average of tags in use -system.l2c.total_refs 2564962 # Total number of references to valid blocks. -system.l2c.sampled_refs 411131 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.238795 # Average number of references to valid blocks. +system.physmem.bw_total::cpu1.inst 56843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 364496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19419523 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 345965 # number of replacements +system.l2c.tagsinuse 65264.028554 # Cycle average of tags in use +system.l2c.total_refs 2565305 # Total number of references to valid blocks. +system.l2c.sampled_refs 411137 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.239538 # Average number of references to valid blocks. system.l2c.warmup_cycle 6370050000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53566.099176 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5313.179425 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6099.564968 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 209.813021 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 75.373703 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.817354 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.081073 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.093072 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.003201 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 53566.065326 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5313.128544 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 6099.641645 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 209.824884 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 75.368156 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.817353 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.081072 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.093073 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.003202 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.001150 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.995850 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 777532 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 689515 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 314287 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 100987 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1882321 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 806312 # number of Writeback hits -system.l2c.Writeback_hits::total 806312 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 440 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 616 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 51 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 81 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 128023 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 44351 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172374 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 777532 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 817538 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 314287 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 145338 # number of demand (read+write) hits -system.l2c.demand_hits::total 2054695 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 777532 # number of overall hits -system.l2c.overall_hits::cpu0.data 817538 # number of overall hits -system.l2c.overall_hits::cpu1.inst 314287 # number of overall hits -system.l2c.overall_hits::cpu1.data 145338 # number of overall hits -system.l2c.overall_hits::total 2054695 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13684 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272967 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1696 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 861 # number of ReadReq misses +system.l2c.ReadReq_hits::cpu0.inst 778193 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 689575 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 314248 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 100958 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1882974 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 806039 # number of Writeback hits +system.l2c.Writeback_hits::total 806039 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 439 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 613 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 52 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 83 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 128167 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 44386 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172553 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 778193 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 817742 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 314248 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 145344 # number of demand (read+write) hits +system.l2c.demand_hits::total 2055527 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 778193 # number of overall hits +system.l2c.overall_hits::cpu0.data 817742 # number of overall hits +system.l2c.overall_hits::cpu1.inst 314248 # number of overall hits +system.l2c.overall_hits::cpu1.data 145344 # number of overall hits +system.l2c.overall_hits::total 2055527 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13677 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 272973 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1705 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 853 # number of ReadReq misses system.l2c.ReadReq_misses::total 289208 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2867 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1568 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4435 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 726 # number of SCUpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2871 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1574 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4445 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 724 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 747 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1473 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113091 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 10063 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 123154 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13684 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 386058 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1696 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10924 # number of demand (read+write) misses -system.l2c.demand_misses::total 412362 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13684 # number of overall misses -system.l2c.overall_misses::cpu0.data 386058 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1696 # number of overall misses -system.l2c.overall_misses::cpu1.data 10924 # number of overall misses -system.l2c.overall_misses::total 412362 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 728665998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14214168999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 90803000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 47077499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 15080715496 # number of ReadReq miss cycles +system.l2c.SCUpgradeReq_misses::total 1471 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 113108 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 10072 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 123180 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13677 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 386081 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1705 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10925 # number of demand (read+write) misses +system.l2c.demand_misses::total 412388 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13677 # number of overall misses +system.l2c.overall_misses::cpu0.data 386081 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1705 # number of overall misses +system.l2c.overall_misses::cpu1.data 10925 # number of overall misses +system.l2c.overall_misses::total 412388 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 728382998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 14214430499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 91270500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 46668499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15080752496 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.data 2584000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 19661414 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 22245414 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2793000 # number of SCUpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 19818914 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 22402914 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2792500 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 314000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3107000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6061091997 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 549004499 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6610096496 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 728665998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20275260996 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 90803000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 596081998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21690811992 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 728665998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20275260996 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 90803000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 596081998 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21690811992 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 791216 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 962482 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 315983 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 101848 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2171529 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 806312 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 806312 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3043 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2008 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5051 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 777 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 777 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_miss_latency::total 3106500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6061979997 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 549631499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6611611496 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 728382998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 20276410496 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 91270500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 596299998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21692363992 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 728382998 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 20276410496 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 91270500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 596299998 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21692363992 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 791870 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 962548 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 315953 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 101811 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2172182 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 806039 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 806039 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3045 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2013 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5058 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 776 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 778 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1554 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 241114 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 54414 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295528 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 791216 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1203596 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 315983 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 156262 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2467057 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 791216 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1203596 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 315983 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 156262 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2467057 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.017295 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.283607 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005367 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.008454 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.133182 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942162 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780876 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.878044 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.934363 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.961390 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.947876 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.469035 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.184934 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.416725 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.017295 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.320754 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005367 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.069908 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.167147 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.017295 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.320754 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005367 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.069908 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.167147 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53249.488308 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.847630 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53539.504717 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 54677.699187 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52144.876684 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 901.290548 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12539.167092 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5015.876888 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3847.107438 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_accesses::cpu0.data 241275 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 54458 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295733 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 791870 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1203823 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 315953 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 156269 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2467915 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 791870 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1203823 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 315953 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 156269 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2467915 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.017272 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.283594 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.005396 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.008378 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.133142 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942857 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.781918 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.878806 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.932990 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.960154 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.946589 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.468793 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.184950 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.416524 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.017272 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.320712 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.005396 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.069911 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.167100 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.017272 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.320712 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.005396 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.069911 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.167100 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53256.050157 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.661029 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53531.085044 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 54711.018757 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52145.004620 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 900.034831 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12591.432020 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5040.025647 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3857.044199 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 420.348059 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2109.300747 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53594.821843 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54556.742423 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53673.421050 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 53249.488308 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52518.691482 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 53539.504717 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 54566.275906 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52601.384201 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 53249.488308 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52518.691482 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 53539.504717 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 54566.275906 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52601.384201 # average overall miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 2111.828688 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53594.617507 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54570.244142 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53674.391102 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 53256.050157 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52518.540141 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 53531.085044 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 54581.235515 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52601.831266 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 53256.050157 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52518.540141 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 53531.085044 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 54581.235515 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52601.831266 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -221,8 +221,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 82258 # number of writebacks -system.l2c.writebacks::total 82258 # number of writebacks +system.l2c.writebacks::writebacks 82268 # number of writebacks +system.l2c.writebacks::total 82268 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits @@ -232,111 +232,111 @@ system.l2c.demand_mshr_hits::total 18 # nu system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 13683 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 272967 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1679 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 861 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 13676 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 272973 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1688 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 853 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 289190 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2867 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1568 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 4435 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 726 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2871 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1574 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4445 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 724 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 747 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1473 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 113091 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 10063 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 123154 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13683 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 386058 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1679 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 10924 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 412344 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13683 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 386058 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1679 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 10924 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 412344 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 561385998 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10939069000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 69521500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 36634000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 11606610498 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 114796000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 62749500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 177545500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 29087500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_misses::total 1471 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 113108 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 10072 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 123180 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13676 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 386081 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1688 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10925 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 412370 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13676 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 386081 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1688 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10925 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 412370 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 561190998 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10939303500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 69880000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 36325000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11606699498 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 114956000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 62989500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 177945500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 29007500 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 29880000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 58967500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4695316997 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 427005999 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5122322996 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 561385998 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 15634385997 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 69521500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 463639999 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16728933494 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 561385998 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 15634385997 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 69521500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 463639999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16728933494 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 820941530 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 58887500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4696029997 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 427574999 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5123604996 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 561190998 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 15635333497 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 69880000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 463899999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16730304494 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 561190998 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 15635333497 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 69880000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 463899999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16730304494 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 820944530 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 16650000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 837591530 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1194248500 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 837594530 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1194274500 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 359420000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1553668500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2015190030 # number of overall MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1553694500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2015219030 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.data 376070000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 2391260030 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.283607 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.008454 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.133173 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942162 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.780876 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.878044 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.934363 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961390 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.947876 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.469035 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.184934 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.416725 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.320754 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.069908 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.167140 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.320754 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.069908 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.167140 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40074.694011 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42548.199768 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40134.895736 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.460412 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40018.813776 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.807215 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40065.426997 # average SCUpgradeReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::total 2391289030 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.017271 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.283594 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005343 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.008378 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.133133 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942857 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.781918 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.878806 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.932990 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.960154 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.946589 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.468793 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.184950 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.416524 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017271 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.320712 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005343 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.069911 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.167092 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017271 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.320712 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005343 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.069911 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.167092 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41034.732232 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40074.672220 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41398.104265 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42584.994138 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40135.203493 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40018.742058 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.733408 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40065.607735 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40032.247115 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41518.042965 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42433.270297 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41592.826835 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40497.505548 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42442.328726 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40570.333251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40497.505548 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42442.328726 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40570.333251 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40032.290959 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41518.106562 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42451.846604 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41594.455236 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41034.732232 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40497.547139 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41398.104265 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42462.242471 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40571.099968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41034.732232 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40497.547139 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41398.104265 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42462.242471 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40571.099968 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -348,12 +348,12 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41698 # number of replacements -system.iocache.tagsinuse 0.465240 # Cycle average of tags in use +system.iocache.tagsinuse 0.465235 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1711281170000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.465240 # Average occupied blocks per requestor +system.iocache.occ_blocks::tsunami.ide 0.465235 # Average occupied blocks per requestor system.iocache.occ_percent::tsunami.ide 0.029077 # Average percentage of cache occupancy system.iocache.occ_percent::total 0.029077 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses @@ -366,12 +366,12 @@ system.iocache.overall_misses::tsunami.ide 41730 # system.iocache.overall_misses::total 41730 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21238998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21238998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7637775806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7637775806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7659014804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7659014804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 7659014804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7659014804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 7637828806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 7637828806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 7659067804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7659067804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 7659067804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7659067804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -390,17 +390,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119320.213483 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119320.213483 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183812.471265 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183812.471265 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183537.378481 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183537.378481 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183537.378481 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183537.378481 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7710000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183813.746775 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183813.746775 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183538.648550 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183538.648550 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183538.648550 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183538.648550 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7685000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7151 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7152 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1078.170885 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1074.524609 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -416,12 +416,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41730 system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11982000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11982000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5476916000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5476916000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5488898000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5488898000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5488898000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5488898000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5476969000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5476969000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5488951000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5488951000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5488951000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5488951000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -432,12 +432,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67314.606742 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67314.606742 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131808.721602 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131808.721602 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131533.620896 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131533.620896 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131533.620896 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131533.620896 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131809.997112 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131809.997112 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131534.890966 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131534.890966 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131534.890966 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131534.890966 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +455,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8334313 # DTB read hits -system.cpu0.dtb.read_misses 29661 # DTB read misses -system.cpu0.dtb.read_acv 416 # DTB read access violations -system.cpu0.dtb.read_accesses 650050 # DTB read accesses -system.cpu0.dtb.write_hits 5360515 # DTB write hits -system.cpu0.dtb.write_misses 6017 # DTB write misses -system.cpu0.dtb.write_acv 275 # DTB write access violations -system.cpu0.dtb.write_accesses 211537 # DTB write accesses -system.cpu0.dtb.data_hits 13694828 # DTB hits -system.cpu0.dtb.data_misses 35678 # DTB misses -system.cpu0.dtb.data_acv 691 # DTB access violations -system.cpu0.dtb.data_accesses 861587 # DTB accesses -system.cpu0.itb.fetch_hits 972456 # ITB hits -system.cpu0.itb.fetch_misses 29747 # ITB misses -system.cpu0.itb.fetch_acv 802 # ITB acv -system.cpu0.itb.fetch_accesses 1002203 # ITB accesses +system.cpu0.dtb.read_hits 8334041 # DTB read hits +system.cpu0.dtb.read_misses 29708 # DTB read misses +system.cpu0.dtb.read_acv 432 # DTB read access violations +system.cpu0.dtb.read_accesses 650283 # DTB read accesses +system.cpu0.dtb.write_hits 5360343 # DTB write hits +system.cpu0.dtb.write_misses 6029 # DTB write misses +system.cpu0.dtb.write_acv 281 # DTB write access violations +system.cpu0.dtb.write_accesses 211361 # DTB write accesses +system.cpu0.dtb.data_hits 13694384 # DTB hits +system.cpu0.dtb.data_misses 35737 # DTB misses +system.cpu0.dtb.data_acv 713 # DTB access violations +system.cpu0.dtb.data_accesses 861644 # DTB accesses +system.cpu0.itb.fetch_hits 975254 # ITB hits +system.cpu0.itb.fetch_misses 26821 # ITB misses +system.cpu0.itb.fetch_acv 801 # ITB acv +system.cpu0.itb.fetch_accesses 1002075 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -483,143 +483,143 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 107494535 # number of cpu cycles simulated +system.cpu0.numCycles 107505653 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 11769770 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 9862090 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 345528 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 8388023 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5075121 # Number of BTB hits +system.cpu0.BPredUnit.lookups 11783453 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 9875598 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 345606 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 8356965 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5072042 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 768289 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 29261 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 25151812 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 60423976 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 11769770 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5843410 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11477495 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1678868 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 36441754 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 35468 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 189532 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 310248 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 196 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7504127 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 232204 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 74712100 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.808758 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.135218 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 768478 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 29315 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 25158431 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 60438649 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11783453 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5840520 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11478099 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1678793 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 36446213 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 35059 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 187963 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 310129 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 172 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7506544 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 232672 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 74721559 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.808852 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.135528 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 63234605 84.64% 84.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 741221 0.99% 85.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1559530 2.09% 87.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 686170 0.92% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2492076 3.34% 91.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 531561 0.71% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 568906 0.76% 93.44% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 718608 0.96% 94.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4179423 5.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 63243460 84.64% 84.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 740935 0.99% 85.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1559450 2.09% 87.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 686263 0.92% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2492339 3.34% 91.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 528695 0.71% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 568727 0.76% 93.44% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 718688 0.96% 94.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4183002 5.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 74712100 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.109492 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.562112 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26235752 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36073897 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10433111 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 896014 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1073325 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 504398 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 32602 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 59387121 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 93497 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1073325 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27172169 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 15317742 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17291837 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9793019 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4064006 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 56407383 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7139 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 656540 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1492805 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 37953017 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 68861567 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 68508934 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 352633 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33050954 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4902063 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1333181 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 200244 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 10589201 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8773580 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5638577 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1132250 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 738910 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50116652 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1669804 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 48856794 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 108488 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5944129 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3041029 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1132337 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 74712100 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.653934 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.297915 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 74721559 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.109608 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.562190 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26241114 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36078495 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10432905 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 895868 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1073176 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 504459 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 32663 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 59394337 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 93513 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1073176 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27177088 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 15322085 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17293060 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9793199 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4062949 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 56409108 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7164 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 656382 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1492215 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 37953965 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 68862069 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 68509500 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 352569 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33051447 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4902518 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1333146 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 200213 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10586539 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8773665 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5638420 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1132750 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 738704 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50116530 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1671338 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 48856724 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 108345 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5942974 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3041199 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1133867 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 74721559 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.653850 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.297886 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 52667189 70.49% 70.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10185163 13.63% 84.13% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4563652 6.11% 90.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2983683 3.99% 94.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2257783 3.02% 97.25% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1142078 1.53% 98.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 582516 0.78% 99.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 283628 0.38% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 46408 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 52677257 70.50% 70.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10184833 13.63% 84.13% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4563049 6.11% 90.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2984127 3.99% 94.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2257312 3.02% 97.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1142410 1.53% 98.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 582471 0.78% 99.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 283512 0.38% 99.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 46588 0.06% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 74712100 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 74721559 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 73121 11.93% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 287582 46.92% 58.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 252262 41.15% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 73394 11.97% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 287556 46.90% 58.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 252163 41.13% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 4467 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 33934109 69.46% 69.47% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 53582 0.11% 69.58% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.58% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 33933939 69.46% 69.47% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 53607 0.11% 69.57% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.57% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 16546 0.03% 69.61% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.61% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.61% # Type of FU issued @@ -646,116 +646,116 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.61% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.61% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.61% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.61% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8675974 17.76% 87.37% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5426955 11.11% 98.48% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 742930 1.52% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8676123 17.76% 87.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5426873 11.11% 98.48% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 742938 1.52% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 48856794 # Type of FU issued -system.cpu0.iq.rate 0.454505 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 612965 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012546 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 172645923 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 57499135 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 47860626 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 501218 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 243758 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 236014 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 49202996 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 262296 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 518056 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 48856724 # Type of FU issued +system.cpu0.iq.rate 0.454457 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 613113 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012549 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 172655307 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57499462 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 47860573 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 501158 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 243682 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 236026 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 49203092 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 262278 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 518007 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1116510 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2510 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12661 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 476371 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1116542 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2532 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12656 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 476196 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18849 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 94368 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18844 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 94055 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1073325 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10798667 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 779958 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 54837290 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 559703 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8773580 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5638577 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1469305 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 544312 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 8344 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12661 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 186183 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 327984 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 514167 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 48431427 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8385093 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 425367 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1073176 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10803844 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 780020 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 54838073 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 560128 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8773665 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5638420 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1470903 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 544426 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 8361 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12656 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186168 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 328100 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 514268 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 48431034 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8384906 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 425690 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3050834 # number of nop insts executed -system.cpu0.iew.exec_refs 13764236 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7758760 # Number of branches executed -system.cpu0.iew.exec_stores 5379143 # Number of stores executed -system.cpu0.iew.exec_rate 0.450548 # Inst execution rate -system.cpu0.iew.wb_sent 48183951 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 48096640 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24100280 # num instructions producing a value -system.cpu0.iew.wb_consumers 32401803 # num instructions consuming a value +system.cpu0.iew.exec_nop 3050205 # number of nop insts executed +system.cpu0.iew.exec_refs 13763900 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7759085 # Number of branches executed +system.cpu0.iew.exec_stores 5378994 # Number of stores executed +system.cpu0.iew.exec_rate 0.450498 # Inst execution rate +system.cpu0.iew.wb_sent 48183963 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 48096599 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24100955 # num instructions producing a value +system.cpu0.iew.wb_consumers 32404442 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.447433 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.743794 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.447387 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.743755 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 48294177 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 48294177 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 6449436 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 537467 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 480768 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 73638775 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.655825 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.560295 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 48294855 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 48294855 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6449755 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 537471 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 480800 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 73648383 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.655749 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.560255 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 55222738 74.99% 74.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7735232 10.50% 85.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4278280 5.81% 91.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2283958 3.10% 94.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1242509 1.69% 96.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 524248 0.71% 96.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 435052 0.59% 97.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 385141 0.52% 97.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1531617 2.08% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 55233499 75.00% 75.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7733418 10.50% 85.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4278651 5.81% 91.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2283988 3.10% 94.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1242605 1.69% 96.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 524240 0.71% 96.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 434900 0.59% 97.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 385505 0.52% 97.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1531577 2.08% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 73638775 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 48294177 # Number of instructions committed -system.cpu0.commit.committedOps 48294177 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 73648383 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 48294855 # Number of instructions committed +system.cpu0.commit.committedOps 48294855 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12819276 # Number of memory references committed -system.cpu0.commit.loads 7657070 # Number of loads committed +system.cpu0.commit.refs 12819347 # Number of memory references committed +system.cpu0.commit.loads 7657123 # Number of loads committed system.cpu0.commit.membars 181890 # Number of memory barriers committed -system.cpu0.commit.branches 7325526 # Number of branches committed +system.cpu0.commit.branches 7325688 # Number of branches committed system.cpu0.commit.fp_insts 233448 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 44748110 # Number of committed integer instructions. -system.cpu0.commit.function_calls 610965 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1531617 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 44748779 # Number of committed integer instructions. +system.cpu0.commit.function_calls 610967 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1531577 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 126666255 # The number of ROB reads -system.cpu0.rob.rob_writes 110560293 # The number of ROB writes -system.cpu0.timesIdled 1221795 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 32782435 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693291566 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 45532520 # Number of Instructions Simulated -system.cpu0.committedOps 45532520 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 45532520 # Number of Instructions Simulated -system.cpu0.cpi 2.360830 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.360830 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.423580 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.423580 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 63860317 # number of integer regfile reads -system.cpu0.int_regfile_writes 34945795 # number of integer regfile writes -system.cpu0.fp_regfile_reads 117013 # number of floating regfile reads -system.cpu0.fp_regfile_writes 117648 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1550179 # number of misc regfile reads -system.cpu0.misc_regfile_writes 750147 # number of misc regfile writes +system.cpu0.rob.rob_reads 126676900 # The number of ROB reads +system.cpu0.rob.rob_writes 110562172 # The number of ROB writes +system.cpu0.timesIdled 1222053 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 32784094 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3693280483 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 45533193 # Number of Instructions Simulated +system.cpu0.committedOps 45533193 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 45533193 # Number of Instructions Simulated +system.cpu0.cpi 2.361039 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.361039 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.423542 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.423542 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 63859411 # number of integer regfile reads +system.cpu0.int_regfile_writes 34945756 # number of integer regfile writes +system.cpu0.fp_regfile_reads 117042 # number of floating regfile reads +system.cpu0.fp_regfile_writes 117632 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1550181 # number of misc regfile reads +system.cpu0.misc_regfile_writes 750158 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -787,247 +787,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 790628 # number of replacements -system.cpu0.icache.tagsinuse 510.000717 # Cycle average of tags in use -system.cpu0.icache.total_refs 6669453 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 791140 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.430180 # Average number of references to valid blocks. +system.cpu0.icache.replacements 791282 # number of replacements +system.cpu0.icache.tagsinuse 510.000823 # Cycle average of tags in use +system.cpu0.icache.total_refs 6671308 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 791794 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.425560 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 23654486000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.000717 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 510.000823 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.996095 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.996095 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6669453 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6669453 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6669453 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6669453 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6669453 # number of overall hits -system.cpu0.icache.overall_hits::total 6669453 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 834673 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 834673 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 834673 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 834673 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 834673 # number of overall misses -system.cpu0.icache.overall_misses::total 834673 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13767352493 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13767352493 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13767352493 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13767352493 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13767352493 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13767352493 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7504126 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7504126 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7504126 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7504126 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7504126 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7504126 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111229 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.111229 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111229 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.111229 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111229 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.111229 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16494.306744 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16494.306744 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16494.306744 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16494.306744 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16494.306744 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16494.306744 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1480996 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 6671308 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6671308 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6671308 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6671308 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6671308 # number of overall hits +system.cpu0.icache.overall_hits::total 6671308 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 835236 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 835236 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 835236 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 835236 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 835236 # number of overall misses +system.cpu0.icache.overall_misses::total 835236 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13775160993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13775160993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13775160993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13775160993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13775160993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13775160993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7506544 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7506544 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7506544 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7506544 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7506544 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7506544 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111268 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.111268 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111268 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.111268 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111268 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.111268 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16492.537430 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16492.537430 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16492.537430 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16492.537430 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16492.537430 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16492.537430 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1463996 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 158 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 9141.950617 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 9265.797468 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 247 # number of writebacks -system.cpu0.icache.writebacks::total 247 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43336 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43336 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43336 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43336 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43336 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43336 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791337 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 791337 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 791337 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 791337 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 791337 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 791337 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10689365997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10689365997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10689365997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10689365997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10689365997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10689365997 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105454 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.105454 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.105454 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13507.982057 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13507.982057 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13507.982057 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43249 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43249 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43249 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43249 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43249 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43249 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791987 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 791987 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 791987 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 791987 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 791987 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 791987 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10696262996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10696262996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10696262996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10696262996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10696262996 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10696262996 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105506 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105506 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105506 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.105506 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105506 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.105506 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13505.604254 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13505.604254 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13505.604254 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13505.604254 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13505.604254 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13505.604254 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1206208 # number of replacements -system.cpu0.dcache.tagsinuse 505.878050 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9822290 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1206649 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.140139 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1206262 # number of replacements +system.cpu0.dcache.tagsinuse 505.874752 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9821312 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1206702 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.138971 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 19675000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.878050 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.988043 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.988043 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6113680 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6113680 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3377171 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3377171 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150549 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 150549 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171656 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171656 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9490851 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9490851 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9490851 # number of overall hits -system.cpu0.dcache.overall_hits::total 9490851 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1478314 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1478314 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1593619 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1593619 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 18637 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18637 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4699 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 4699 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3071933 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3071933 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3071933 # number of overall misses -system.cpu0.dcache.overall_misses::total 3071933 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41272950000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 41272950000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 65317405497 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 65317405497 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 315155000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 315155000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68652000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 68652000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 106590355497 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 106590355497 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 106590355497 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 106590355497 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7591994 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7591994 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970790 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4970790 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 169186 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 169186 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176355 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 176355 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12562784 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12562784 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12562784 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12562784 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.194720 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.194720 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320597 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.320597 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110157 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110157 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026645 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026645 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244526 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.244526 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244526 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.244526 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27918.933325 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27918.933325 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40986.839073 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40986.839073 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16910.178677 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16910.178677 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14609.917004 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14609.917004 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34698.138109 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34698.138109 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34698.138109 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34698.138109 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 716537144 # number of cycles access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 505.874752 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.988037 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.988037 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6113380 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6113380 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3377082 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3377082 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150588 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 150588 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171660 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171660 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9490462 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9490462 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9490462 # number of overall hits +system.cpu0.dcache.overall_hits::total 9490462 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1478592 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1478592 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1593723 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1593723 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 18660 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18660 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4698 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4698 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3072315 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3072315 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3072315 # number of overall misses +system.cpu0.dcache.overall_misses::total 3072315 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41280324500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 41280324500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 65318664554 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 65318664554 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 315332000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 315332000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68573000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 68573000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 106598989054 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 106598989054 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 106598989054 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 106598989054 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7591972 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7591972 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970805 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4970805 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 169248 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 169248 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176358 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 176358 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12562777 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12562777 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12562777 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12562777 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.194757 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.194757 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320617 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.320617 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110252 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110252 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026639 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026639 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244557 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.244557 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244557 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.244557 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27918.671615 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27918.671615 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40984.954446 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40984.954446 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16898.821008 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16898.821008 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14596.211154 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14596.211154 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34696.633989 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34696.633989 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34696.633989 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34696.633989 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 716919646 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 65430 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 65391 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10951.201956 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10963.582848 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 693284 # number of writebacks -system.cpu0.dcache.writebacks::total 693284 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 515563 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 515563 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1344321 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1344321 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3732 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3732 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1859884 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1859884 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1859884 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1859884 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 962751 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 962751 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249298 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249298 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14905 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14905 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4699 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 4699 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1212049 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1212049 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1212049 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1212049 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25942792600 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25942792600 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8699231964 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8699231964 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186934001 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186934001 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 54037501 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 54037501 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34642024564 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 34642024564 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34642024564 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 34642024564 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 918343000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 918343000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1327727998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1327727998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2246070998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2246070998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.126811 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.126811 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050153 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050153 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088098 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088098 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026645 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026645 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096479 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.096479 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096479 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.096479 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26946.523660 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26946.523660 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34894.912771 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34894.912771 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.697484 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.697484 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11499.787402 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11499.787402 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28581.373001 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28581.373001 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28581.373001 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28581.373001 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 693314 # number of writebacks +system.cpu0.dcache.writebacks::total 693314 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 515793 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 515793 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1344404 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1344404 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3762 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3762 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1860197 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1860197 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1860197 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1860197 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 962799 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 962799 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249319 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249319 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14898 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14898 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4698 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4698 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1212118 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1212118 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1212118 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1212118 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25944695097 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25944695097 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8701407966 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8701407966 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186837501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186837501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 53961001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 53961001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34646103063 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34646103063 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34646103063 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34646103063 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 918480000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 918480000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1327721998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1327721998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2246201998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2246201998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.126818 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.126818 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050157 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050157 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088025 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088025 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026639 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026639 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096485 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096485 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096485 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096485 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26947.156257 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26947.156257 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34900.701375 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34900.701375 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.112968 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.112968 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11485.951682 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11485.951682 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28583.110772 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28583.110772 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28583.110772 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28583.110772 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1039,22 +1037,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2499316 # DTB read hits -system.cpu1.dtb.read_misses 12569 # DTB read misses +system.cpu1.dtb.read_hits 2497958 # DTB read hits +system.cpu1.dtb.read_misses 12385 # DTB read misses system.cpu1.dtb.read_acv 105 # DTB read access violations -system.cpu1.dtb.read_accesses 313735 # DTB read accesses -system.cpu1.dtb.write_hits 1734639 # DTB write hits -system.cpu1.dtb.write_misses 3525 # DTB write misses -system.cpu1.dtb.write_acv 140 # DTB write access violations -system.cpu1.dtb.write_accesses 132367 # DTB write accesses -system.cpu1.dtb.data_hits 4233955 # DTB hits -system.cpu1.dtb.data_misses 16094 # DTB misses -system.cpu1.dtb.data_acv 245 # DTB access violations -system.cpu1.dtb.data_accesses 446102 # DTB accesses -system.cpu1.itb.fetch_hits 489806 # ITB hits -system.cpu1.itb.fetch_misses 8851 # ITB misses -system.cpu1.itb.fetch_acv 360 # ITB acv -system.cpu1.itb.fetch_accesses 498657 # ITB accesses +system.cpu1.dtb.read_accesses 312687 # DTB read accesses +system.cpu1.dtb.write_hits 1734137 # DTB write hits +system.cpu1.dtb.write_misses 3404 # DTB write misses +system.cpu1.dtb.write_acv 137 # DTB write access violations +system.cpu1.dtb.write_accesses 131810 # DTB write accesses +system.cpu1.dtb.data_hits 4232095 # DTB hits +system.cpu1.dtb.data_misses 15789 # DTB misses +system.cpu1.dtb.data_acv 242 # DTB access violations +system.cpu1.dtb.data_accesses 444497 # DTB accesses +system.cpu1.itb.fetch_hits 488697 # ITB hits +system.cpu1.itb.fetch_misses 8773 # ITB misses +system.cpu1.itb.fetch_acv 366 # ITB acv +system.cpu1.itb.fetch_accesses 497470 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1067,144 +1065,144 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 22717311 # number of cpu cycles simulated +system.cpu1.numCycles 22715640 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 3442703 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 2849702 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 108899 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 2361843 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 1192387 # Number of BTB hits +system.cpu1.BPredUnit.lookups 3441563 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 2848590 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 108508 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 2344214 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 1191088 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 236332 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 10679 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 9037199 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 16321027 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3442703 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1428719 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2924126 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 526603 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 8306285 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 28121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 87140 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 64229 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1963514 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 75345 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 20778311 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.785484 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.154367 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 236176 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 10617 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 9035553 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 16314409 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3441563 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1427264 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2922038 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 525528 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 8308395 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 28029 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 86548 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 64086 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1962045 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 75286 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 20775175 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.785284 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.154306 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 17854185 85.93% 85.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 203613 0.98% 86.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 301133 1.45% 88.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 225724 1.09% 89.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 404540 1.95% 91.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 151692 0.73% 92.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 164507 0.79% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 309022 1.49% 94.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1163895 5.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 17853137 85.93% 85.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 203247 0.98% 86.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 300737 1.45% 88.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 225181 1.08% 89.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 403762 1.94% 91.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 151742 0.73% 92.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 164996 0.79% 92.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 308573 1.49% 94.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1163800 5.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 20778311 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.151545 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.718440 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 8812255 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 8762880 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2709089 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 172906 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 321180 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 151088 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 10133 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 16020033 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 29351 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 321180 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 9094333 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 882455 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6951469 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2594850 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 934022 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 14843152 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 114 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 83650 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 279958 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 9660007 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 17630674 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 17422680 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 207994 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 8331005 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1328994 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 594043 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 64597 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2775458 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2641121 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1825529 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 246953 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 159017 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 12975245 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 664400 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 12700763 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 35708 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1746535 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 829425 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 468662 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 20778311 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.611251 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.284414 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 20775175 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.151506 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.718202 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8809071 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8765539 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2707216 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 172890 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 320458 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 151147 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 10158 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 16014026 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 29482 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 320458 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 9091295 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 884150 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6951341 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2592964 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 934965 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 14837454 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 127 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 84091 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 280482 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 9656446 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 17623003 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 17415204 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 207799 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 8330618 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1325820 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 594023 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 64559 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2775443 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2639269 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1825014 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 248716 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 160479 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 12970444 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 664664 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 12696455 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 35550 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1743951 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 828101 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 468923 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 20775175 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.611136 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.284217 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 15115816 72.75% 72.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2653114 12.77% 85.52% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1112593 5.35% 90.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 724594 3.49% 94.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 603153 2.90% 97.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 287847 1.39% 98.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 182303 0.88% 99.52% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 88112 0.42% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 10779 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 15113498 72.75% 72.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2653136 12.77% 85.52% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1113601 5.36% 90.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 723121 3.48% 94.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 602829 2.90% 97.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 288191 1.39% 98.65% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 181892 0.88% 99.52% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 88125 0.42% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 10782 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 20778311 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 20775175 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3869 1.53% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 134765 53.16% 54.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 114892 45.32% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3857 1.52% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 134714 53.16% 54.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 114823 45.31% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 2823 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7927502 62.42% 62.44% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 20764 0.16% 62.60% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10543 0.08% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7925481 62.42% 62.45% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 20760 0.16% 62.61% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10544 0.08% 62.69% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued @@ -1230,357 +1228,355 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.70% # Ty system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.70% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.70% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2623377 20.66% 83.35% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1764952 13.90% 97.25% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 349391 2.75% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2621698 20.65% 83.35% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1764339 13.90% 97.25% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 349399 2.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 12700763 # Type of FU issued -system.cpu1.iq.rate 0.559079 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 253526 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019961 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 46169663 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 15243166 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 12341001 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 299407 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 145151 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 140846 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 12794667 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 156799 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 115193 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 12696455 # Type of FU issued +system.cpu1.iq.rate 0.558930 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 253394 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019958 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 46157750 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 15236198 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 12337265 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 299278 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 145041 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 140795 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 12790304 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 156722 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 115188 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 347930 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 808 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 2222 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 153073 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 346106 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 806 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 2268 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 152574 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 370 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 11635 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 376 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 11381 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 321180 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 537224 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 73444 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 14366092 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 206312 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2641121 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1825529 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 596088 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 55197 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6016 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 2222 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 53937 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 130013 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 183950 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 12579473 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2523314 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 121289 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 320458 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 536973 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 73252 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 14361364 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 205800 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2639269 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1825014 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 596393 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 55379 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 5710 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 2268 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 53644 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 129908 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 183552 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 12575424 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2521777 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 121030 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 726447 # number of nop insts executed -system.cpu1.iew.exec_refs 4269906 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1887172 # Number of branches executed -system.cpu1.iew.exec_stores 1746592 # Number of stores executed -system.cpu1.iew.exec_rate 0.553740 # Inst execution rate -system.cpu1.iew.wb_sent 12515990 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 12481847 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5700900 # num instructions producing a value -system.cpu1.iew.wb_consumers 8040202 # num instructions consuming a value +system.cpu1.iew.exec_nop 726256 # number of nop insts executed +system.cpu1.iew.exec_refs 4267761 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1886646 # Number of branches executed +system.cpu1.iew.exec_stores 1745984 # Number of stores executed +system.cpu1.iew.exec_rate 0.553602 # Inst execution rate +system.cpu1.iew.wb_sent 12512047 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 12478060 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5698826 # num instructions producing a value +system.cpu1.iew.wb_consumers 8037620 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.549442 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.709049 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.549316 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.709019 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 12433159 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 12433159 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 1857667 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 195738 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 173364 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 20457131 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.607767 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.554530 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 12432644 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 12432644 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1853978 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 195741 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 172939 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 20454717 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.607813 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.554325 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 15844350 77.45% 77.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2122437 10.38% 87.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 810532 3.96% 91.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 497134 2.43% 94.22% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 362445 1.77% 95.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 133722 0.65% 96.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 129038 0.63% 97.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 154146 0.75% 98.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 403327 1.97% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 15840554 77.44% 77.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2123906 10.38% 87.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 810748 3.96% 91.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 497113 2.43% 94.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 362163 1.77% 95.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 133438 0.65% 96.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 130960 0.64% 97.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 152379 0.74% 98.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 403456 1.97% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 20457131 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 12433159 # Number of instructions committed -system.cpu1.commit.committedOps 12433159 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 20454717 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 12432644 # Number of instructions committed +system.cpu1.commit.committedOps 12432644 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3965647 # Number of memory references committed -system.cpu1.commit.loads 2293191 # Number of loads committed -system.cpu1.commit.membars 64658 # Number of memory barriers committed -system.cpu1.commit.branches 1777478 # Number of branches committed +system.cpu1.commit.refs 3965603 # Number of memory references committed +system.cpu1.commit.loads 2293163 # Number of loads committed +system.cpu1.commit.membars 64660 # Number of memory barriers committed +system.cpu1.commit.branches 1777364 # Number of branches committed system.cpu1.commit.fp_insts 139699 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 11488003 # Number of committed integer instructions. +system.cpu1.commit.int_insts 11487490 # Number of committed integer instructions. system.cpu1.commit.function_calls 194670 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 403327 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 403456 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 34238592 # The number of ROB reads -system.cpu1.rob.rob_writes 28901418 # The number of ROB writes -system.cpu1.timesIdled 230949 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1939000 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3778341690 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 11789199 # Number of Instructions Simulated -system.cpu1.committedOps 11789199 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 11789199 # Number of Instructions Simulated -system.cpu1.cpi 1.926960 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.926960 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.518952 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.518952 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 16196586 # number of integer regfile reads -system.cpu1.int_regfile_writes 8796247 # number of integer regfile writes -system.cpu1.fp_regfile_reads 73611 # number of floating regfile reads -system.cpu1.fp_regfile_writes 74214 # number of floating regfile writes -system.cpu1.misc_regfile_reads 699711 # number of misc regfile reads -system.cpu1.misc_regfile_writes 299448 # number of misc regfile writes -system.cpu1.icache.replacements 315447 # number of replacements -system.cpu1.icache.tagsinuse 471.003081 # Cycle average of tags in use -system.cpu1.icache.total_refs 1635327 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 315959 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.175757 # Average number of references to valid blocks. +system.cpu1.rob.rob_reads 34231845 # The number of ROB reads +system.cpu1.rob.rob_writes 28892260 # The number of ROB writes +system.cpu1.timesIdled 230897 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1940465 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3778342351 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 11788689 # Number of Instructions Simulated +system.cpu1.committedOps 11788689 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 11788689 # Number of Instructions Simulated +system.cpu1.cpi 1.926901 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.926901 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.518968 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.518968 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 16191128 # number of integer regfile reads +system.cpu1.int_regfile_writes 8793643 # number of integer regfile writes +system.cpu1.fp_regfile_reads 73550 # number of floating regfile reads +system.cpu1.fp_regfile_writes 74224 # number of floating regfile writes +system.cpu1.misc_regfile_reads 699686 # number of misc regfile reads +system.cpu1.misc_regfile_writes 299450 # number of misc regfile writes +system.cpu1.icache.replacements 315418 # number of replacements +system.cpu1.icache.tagsinuse 471.006638 # Cycle average of tags in use +system.cpu1.icache.total_refs 1633897 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 315930 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.171706 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 1877367216000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 471.003081 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.919928 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.919928 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1635327 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1635327 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1635327 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1635327 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1635327 # number of overall hits -system.cpu1.icache.overall_hits::total 1635327 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 328187 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 328187 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 328187 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 328187 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 328187 # number of overall misses -system.cpu1.icache.overall_misses::total 328187 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5323842998 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5323842998 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5323842998 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5323842998 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5323842998 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5323842998 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1963514 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1963514 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1963514 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1963514 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1963514 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1963514 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.167143 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.167143 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.167143 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.167143 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.167143 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.167143 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.980145 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.980145 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.980145 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 16221.980145 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.980145 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 16221.980145 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 228998 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 471.006638 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.919935 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.919935 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1633897 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1633897 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1633897 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1633897 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1633897 # number of overall hits +system.cpu1.icache.overall_hits::total 1633897 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 328148 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 328148 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 328148 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 328148 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 328148 # number of overall misses +system.cpu1.icache.overall_misses::total 328148 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5323185498 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5323185498 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5323185498 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5323185498 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5323185498 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5323185498 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1962045 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1962045 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1962045 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1962045 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1962045 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1962045 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.167248 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.167248 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.167248 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.167248 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.167248 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.167248 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.904439 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.904439 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.904439 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 16221.904439 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.904439 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 16221.904439 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 248998 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 37 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6189.135135 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 5928.523810 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 38 # number of writebacks -system.cpu1.icache.writebacks::total 38 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12173 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 12173 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 12173 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 12173 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 12173 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 12173 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316014 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 316014 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 316014 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 316014 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 316014 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 316014 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4183208998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4183208998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4183208998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4183208998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4183208998 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4183208998 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.160943 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.160943 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.160943 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13237.416690 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13237.416690 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13237.416690 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12162 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 12162 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 12162 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 12162 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 12162 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 12162 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 315986 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 315986 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 315986 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 315986 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 315986 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 315986 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4183764998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4183764998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4183764998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4183764998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4183764998 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4183764998 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.161049 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.161049 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.161049 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.161049 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.161049 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.161049 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13240.349250 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13240.349250 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13240.349250 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13240.349250 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13240.349250 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13240.349250 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 159076 # number of replacements -system.cpu1.dcache.tagsinuse 488.854290 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3388834 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 159588 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 21.234892 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 159031 # number of replacements +system.cpu1.dcache.tagsinuse 488.853384 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3387429 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 159543 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 21.232075 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 42819944000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 488.854290 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.954794 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.954794 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2022458 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2022458 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1251052 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1251052 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49972 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 49972 # number of LoadLockedReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 488.853384 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.954792 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.954792 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2021122 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2021122 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1250999 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1250999 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49956 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 49956 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 48601 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 48601 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3273510 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3273510 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3273510 # number of overall hits -system.cpu1.dcache.overall_hits::total 3273510 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 307183 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 307183 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 360837 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 360837 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8700 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8700 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5048 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5048 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 668020 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 668020 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 668020 # number of overall misses -system.cpu1.dcache.overall_misses::total 668020 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6372115000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6372115000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11323925707 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 11323925707 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 121529000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 121529000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 68413000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 68413000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 17696040707 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 17696040707 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 17696040707 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 17696040707 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2329641 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2329641 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1611889 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1611889 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 58672 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 58672 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 53649 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 53649 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3941530 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3941530 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3941530 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3941530 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.131859 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.131859 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223860 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.223860 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.148282 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.148282 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094093 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094093 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.169482 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.169482 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.169482 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.169482 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20743.709776 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 20743.709776 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31382.385141 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 31382.385141 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13968.850575 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13968.850575 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13552.496038 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13552.496038 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26490.285780 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 26490.285780 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26490.285780 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 26490.285780 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 57515988 # number of cycles access was blocked +system.cpu1.dcache.demand_hits::cpu1.data 3272121 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3272121 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3272121 # number of overall hits +system.cpu1.dcache.overall_hits::total 3272121 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 307358 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 307358 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 360875 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 360875 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8692 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8692 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5047 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5047 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 668233 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 668233 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 668233 # number of overall misses +system.cpu1.dcache.overall_misses::total 668233 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6376981500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6376981500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11324805298 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 11324805298 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 121402000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 121402000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 68410000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 68410000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 17701786798 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 17701786798 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 17701786798 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 17701786798 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2328480 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2328480 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1611874 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1611874 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 58648 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 58648 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 53648 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 53648 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3940354 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3940354 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3940354 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3940354 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.131999 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.131999 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223885 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.223885 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.148206 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.148206 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094076 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094076 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.169587 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.169587 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.169587 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.169587 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20747.732286 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 20747.732286 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31381.517972 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 31381.517972 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13967.096180 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13967.096180 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13554.586883 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13554.586883 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26490.440906 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 26490.440906 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26490.440906 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 26490.440906 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 57267488 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6825 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6761 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8427.250989 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8470.268895 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 112743 # number of writebacks -system.cpu1.dcache.writebacks::total 112743 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 196860 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 196860 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 298722 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 298722 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1021 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1021 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 495582 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 495582 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 495582 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 495582 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110323 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 110323 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62115 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62115 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7679 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7679 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5048 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5048 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 172438 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 172438 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 172438 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 172438 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1760210564 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1760210564 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1471458330 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1471458330 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 78242000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 78242000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52885501 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52885501 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3231668894 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3231668894 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3231668894 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3231668894 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18623000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18623000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 400648500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 400648500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 419271500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 419271500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047356 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047356 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038536 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038536 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130880 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130880 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094093 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094093 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043749 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043749 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043749 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043749 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15955.064347 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15955.064347 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23689.259116 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23689.259116 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10189.087121 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10189.087121 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10476.525555 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10476.525555 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18741.048342 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18741.048342 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18741.048342 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18741.048342 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 112725 # number of writebacks +system.cpu1.dcache.writebacks::total 112725 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 197085 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 197085 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 298748 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 298748 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1016 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1016 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 495833 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 495833 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 495833 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 495833 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110273 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 110273 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62127 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62127 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7676 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7676 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5047 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5047 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 172400 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 172400 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 172400 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 172400 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1761266064 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1761266064 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1471935334 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1471935334 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 78208000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 78208000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52884501 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52884501 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3233201398 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3233201398 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3233201398 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3233201398 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18624000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18624000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 400633000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 400633000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 419257000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 419257000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047358 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047358 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038543 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038543 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130883 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130883 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094076 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094076 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043752 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043752 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043752 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043752 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15971.870394 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15971.870394 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23692.361357 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23692.361357 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10188.639917 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10188.639917 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10478.403210 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10478.403210 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18754.068434 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18754.068434 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18754.068434 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18754.068434 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1590,31 +1586,31 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6699 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 167510 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 167511 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 58590 40.24% 40.24% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 238 0.16% 40.40% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1924 1.32% 41.72% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 340 0.23% 41.96% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 84509 58.04% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 145601 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 84510 58.04% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 145602 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 57892 49.08% 49.08% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 238 0.20% 49.29% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1924 1.63% 50.92% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 340 0.29% 51.20% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 57552 48.80% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 117946 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862592276000 98.01% 98.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 96187500 0.01% 98.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 394889000 0.02% 98.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 155178500 0.01% 98.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 37157854000 1.96% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1900396385000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1862592154000 98.01% 98.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 96215500 0.01% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 394866000 0.02% 98.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 155183500 0.01% 98.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 37157983500 1.96% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1900396402500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.988087 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681016 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810063 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.681008 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810058 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 5 2.38% 2.38% # number of syscalls executed system.cpu0.kern.syscall::3 18 8.57% 10.95% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.43% 12.38% # number of syscalls executed @@ -1654,7 +1650,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.29% # nu system.cpu0.kern.callpal::swpctx 3076 2.00% 2.29% # number of callpals executed system.cpu0.kern.callpal::tbi 37 0.02% 2.32% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.32% # number of callpals executed -system.cpu0.kern.callpal::swpipl 138810 90.43% 92.75% # number of callpals executed +system.cpu0.kern.callpal::swpipl 138811 90.43% 92.75% # number of callpals executed system.cpu0.kern.callpal::rdps 6361 4.14% 96.89% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.89% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.89% # number of callpals executed @@ -1663,44 +1659,44 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.90% # nu system.cpu0.kern.callpal::rti 4288 2.79% 99.69% # number of callpals executed system.cpu0.kern.callpal::callsys 327 0.21% 99.90% # number of callpals executed system.cpu0.kern.callpal::imb 146 0.10% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 153507 # number of callpals executed +system.cpu0.kern.callpal::total 153508 # number of callpals executed system.cpu0.kern.mode_switch::kernel 6690 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1098 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1099 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1098 -system.cpu0.kern.mode_good::user 1098 +system.cpu0.kern.mode_good::kernel 1099 +system.cpu0.kern.mode_good::user 1099 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.164126 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.164275 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.281972 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1897963397000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1861803000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.282193 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1897960603000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1864923000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3077 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2601 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 74467 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 24565 38.36% 38.36% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1923 3.00% 41.36% # number of times we switched to this ipl +system.cpu1.kern.inst.hwrei 74469 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 24566 38.36% 38.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1923 3.00% 41.37% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 439 0.69% 42.05% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 37108 57.95% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 64035 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 23886 48.07% 48.07% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 37109 57.95% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 64037 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 23887 48.07% 48.07% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1923 3.87% 51.93% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 439 0.88% 52.82% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 23447 47.18% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 49695 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870827437000 98.44% 98.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 343518500 0.02% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 182737500 0.01% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29176221000 1.54% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1900529914000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.972359 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 23448 47.18% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 49697 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870827131500 98.44% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 343570500 0.02% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 182754500 0.01% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29175936000 1.54% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1900529392500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.972360 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.631858 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.776060 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.631868 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.776067 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 3 2.59% 2.59% # number of syscalls executed system.cpu1.kern.syscall::3 12 10.34% 12.93% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.86% 13.79% # number of syscalls executed @@ -1730,9 +1726,9 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.52% # nu system.cpu1.kern.callpal::swpctx 1824 2.74% 3.26% # number of callpals executed system.cpu1.kern.callpal::tbi 16 0.02% 3.28% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.29% # number of callpals executed -system.cpu1.kern.callpal::swpipl 57992 87.22% 90.51% # number of callpals executed +system.cpu1.kern.callpal::swpipl 57994 87.22% 90.51% # number of callpals executed system.cpu1.kern.callpal::rdps 2394 3.60% 94.11% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.11% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.12% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 94.12% # number of callpals executed system.cpu1.kern.callpal::rdusp 3 0.00% 94.13% # number of callpals executed system.cpu1.kern.callpal::whami 3 0.00% 94.13% # number of callpals executed @@ -1740,7 +1736,7 @@ system.cpu1.kern.callpal::rti 3680 5.53% 99.66% # nu system.cpu1.kern.callpal::callsys 188 0.28% 99.95% # number of callpals executed system.cpu1.kern.callpal::imb 34 0.05% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 66490 # number of callpals executed +system.cpu1.kern.callpal::total 66492 # number of callpals executed system.cpu1.kern.mode_switch::kernel 2119 # number of protection mode switches system.cpu1.kern.mode_switch::user 641 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2717 # number of protection mode switches @@ -1751,9 +1747,9 @@ system.cpu1.kern.mode_switch_good::kernel 0.473336 # f system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.133235 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.366259 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 7877043500 0.41% 0.41% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 912149500 0.05% 0.46% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1891740713000 99.54% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 7877089500 0.41% 0.41% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 911545000 0.05% 0.46% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1891740750000 99.54% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1825 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index b1df0f096..353ee4820 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -581,7 +581,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port[0] +master=system.bridge.slave system.physmem.port slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index a30a37ba8..f67dea3de 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 11:00:25 +gem5 compiled Jul 26 2012 21:20:05 +gem5 started Jul 26 2012 22:30:38 gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1865402113500 because m5_exit instruction encountered +Exiting @ tick 1864423957500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index a9a5c3cb0..0374f29ea 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,142 +1,146 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.865402 # Number of seconds simulated -sim_ticks 1865402113500 # Number of ticks simulated -final_tick 1865402113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.864424 # Number of seconds simulated +sim_ticks 1864423957500 # Number of ticks simulated +final_tick 1864423957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131129 # Simulator instruction rate (inst/s) -host_op_rate 131129 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4607058697 # Simulator tick rate (ticks/s) -host_mem_usage 298956 # Number of bytes of host memory used -host_seconds 404.90 # Real time elapsed on the host -sim_insts 53094243 # Number of instructions simulated -sim_ops 53094243 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 967424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24877312 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28497024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 967424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 967424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516928 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516928 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15116 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388708 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445266 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117452 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117452 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518614 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13336166 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1421832 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15276612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4029656 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4029656 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4029656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518614 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13336166 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1421832 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19306267 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 338323 # number of replacements -system.l2c.tagsinuse 65346.781313 # Cycle average of tags in use -system.l2c.total_refs 2566599 # Total number of references to valid blocks. -system.l2c.sampled_refs 403491 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.360982 # Average number of references to valid blocks. +host_inst_rate 128916 # Simulator instruction rate (inst/s) +host_op_rate 128916 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4527170908 # Simulator tick rate (ticks/s) +host_mem_usage 303408 # Number of bytes of host memory used +host_seconds 411.83 # Real time elapsed on the host +sim_insts 53091408 # Number of instructions simulated +sim_ops 53091408 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 967616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24878144 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652032 # Number of bytes read from this memory +system.physmem.bytes_read::total 28497792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 967616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 967616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7517760 # Number of bytes written to this memory +system.physmem.bytes_written::total 7517760 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15119 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388721 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41438 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445278 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117465 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117465 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13343609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1422440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15285039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518989 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518989 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4032216 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4032216 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4032216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13343609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1422440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19317254 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 338334 # number of replacements +system.l2c.tagsinuse 65348.280232 # Cycle average of tags in use +system.l2c.total_refs 2564971 # Total number of references to valid blocks. +system.l2c.sampled_refs 403499 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.356821 # Average number of references to valid blocks. system.l2c.warmup_cycle 4861120000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53937.288272 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 5357.413768 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6052.079273 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.823018 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.081748 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.092347 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.997113 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 1010692 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 829338 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1840030 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 843192 # number of Writeback hits -system.l2c.Writeback_hits::total 843192 # number of Writeback hits +system.l2c.occ_blocks::writebacks 53937.270475 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 5353.133006 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6057.876752 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.823017 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.081682 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.092436 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.997136 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 1009873 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 829098 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1838971 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 842689 # number of Writeback hits +system.l2c.Writeback_hits::total 842689 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 35 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 185767 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 185767 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 1010692 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1015105 # number of demand (read+write) hits -system.l2c.demand_hits::total 2025797 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 1010692 # number of overall hits -system.l2c.overall_hits::cpu.data 1015105 # number of overall hits -system.l2c.overall_hits::total 2025797 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 15118 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 273845 # number of ReadReq misses -system.l2c.ReadReq_misses::total 288963 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 49 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 49 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 115352 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115352 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 15118 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 389197 # number of demand (read+write) misses -system.l2c.demand_misses::total 404315 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 15118 # number of overall misses -system.l2c.overall_misses::cpu.data 389197 # number of overall misses -system.l2c.overall_misses::total 404315 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.inst 805739998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 14260725000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 15066464998 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 501500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 501500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6190534997 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6190534997 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.inst 805739998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 20451259997 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21256999995 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.inst 805739998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 20451259997 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21256999995 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 1025810 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1103183 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2128993 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 843192 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 843192 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 84 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 185872 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 185872 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 1009873 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1014970 # number of demand (read+write) hits +system.l2c.demand_hits::total 2024843 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 1009873 # number of overall hits +system.l2c.overall_hits::cpu.data 1014970 # number of overall hits +system.l2c.overall_hits::total 2024843 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 15121 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 273859 # number of ReadReq misses +system.l2c.ReadReq_misses::total 288980 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 50 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 50 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 115376 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115376 # number of ReadExReq misses +system.l2c.demand_misses::cpu.inst 15121 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 389235 # number of demand (read+write) misses +system.l2c.demand_misses::total 404356 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.inst 15121 # number of overall misses +system.l2c.overall_misses::cpu.data 389235 # number of overall misses +system.l2c.overall_misses::total 404356 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.inst 805852997 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 14261584000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15067436997 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 397000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 397000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6192128996 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6192128996 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.inst 805852997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 20453712996 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21259565993 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 805852997 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 20453712996 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21259565993 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 1024994 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1102957 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2127951 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 842689 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 842689 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 85 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 85 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 301119 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 301119 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 1025810 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1404302 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2430112 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1025810 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1404302 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2430112 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.014738 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.248232 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.135728 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.583333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.583333 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.383078 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.383078 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.014738 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.277146 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.166377 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.014738 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.277146 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.166377 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.inst 53296.732240 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52075.900601 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52139.772213 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 10234.693878 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 10234.693878 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 53666.473030 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53666.473030 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 53296.732240 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52547.321786 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52575.343470 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 53296.732240 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52547.321786 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52575.343470 # average overall miss latency +system.l2c.ReadExReq_accesses::cpu.data 301248 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 301248 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.inst 1024994 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1404205 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2429199 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1024994 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1404205 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2429199 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.014752 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.248295 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.135802 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.588235 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.588235 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.382993 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.382993 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.014752 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.277192 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.166457 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.014752 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.277192 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.166457 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 53293.631175 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52076.375069 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52140.068506 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 7940 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 7940 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 53669.125260 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53669.125260 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 53293.631175 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52548.493830 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52576.358439 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 53293.631175 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52548.493830 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52576.358439 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -145,72 +149,80 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 75940 # number of writebacks -system.l2c.writebacks::total 75940 # number of writebacks +system.l2c.writebacks::writebacks 75953 # number of writebacks +system.l2c.writebacks::total 75953 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.inst 15117 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 273845 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 288962 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 49 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 49 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 115352 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 115352 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 15117 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 389197 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 404314 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 15117 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 389197 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 404314 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 620965998 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 10975082500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 11596048498 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 2065000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 2065000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4796966997 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4796966997 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 620965998 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 15772049497 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16393015495 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 620965998 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 15772049497 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16393015495 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 810224030 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 810224030 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1103797000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1103797000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 1914021030 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1914021030 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014737 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248232 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.135727 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.583333 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.583333 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383078 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.383078 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.014737 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.277146 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.166377 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.014737 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.277146 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.166377 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41077.330026 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40077.717322 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40130.011898 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42142.857143 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42142.857143 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41585.468800 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41585.468800 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41077.330026 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40524.591652 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40545.258129 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41077.330026 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40524.591652 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40545.258129 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu.inst 15120 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 273859 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 288979 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 50 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 50 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 115376 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 115376 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 15120 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 389235 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 404355 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 15120 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 389235 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 404355 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 621011997 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 10975832000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11596843997 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 2105000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 2105000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 40000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 40000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4797954496 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4797954496 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 621011997 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 15773786496 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16394798493 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 621011997 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 15773786496 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16394798493 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809342530 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 809342530 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1103231500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1103231500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 1912574030 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1912574030 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014751 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248295 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.135802 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.588235 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.588235 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.382993 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.382993 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.014751 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.277192 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.166456 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.014751 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.277192 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.166456 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41072.222024 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40078.405311 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40130.403929 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42100 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42100 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41585.377340 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41585.377340 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41072.222024 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40525.097938 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40545.556486 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41072.222024 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40525.097938 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40545.556486 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -219,14 +231,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.294799 # Cycle average of tags in use +system.iocache.tagsinuse 1.287077 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1711277767000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.294799 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.080925 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.080925 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1711278506000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.287077 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.080442 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.080442 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -237,12 +249,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7641897806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7641897806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7662570804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7662570804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 7662570804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7662570804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 7639838806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 7639838806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 7660511804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7660511804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 7660511804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7660511804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -261,17 +273,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183911.672266 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183911.672266 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183644.596860 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183644.596860 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183644.596860 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183644.596860 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7656000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183862.119898 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183862.119898 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183595.249946 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183595.249946 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183595.249946 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183595.249946 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7420000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7143 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7102 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1071.818564 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1044.776119 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -287,12 +299,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5481043992 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5481043992 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5492719992 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5492719992 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5492719992 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5492719992 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5478984000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5478984000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5490660000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5490660000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5490660000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5490660000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -303,12 +315,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131908.066808 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131908.066808 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131640.982433 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131640.982433 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131640.982433 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131640.982433 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131858.490566 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131858.490566 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131591.611744 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131591.611744 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131591.611744 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131591.611744 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -326,22 +338,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9972402 # DTB read hits -system.cpu.dtb.read_misses 43929 # DTB read misses -system.cpu.dtb.read_acv 494 # DTB read access violations -system.cpu.dtb.read_accesses 957886 # DTB read accesses -system.cpu.dtb.write_hits 6649938 # DTB write hits -system.cpu.dtb.write_misses 10071 # DTB write misses -system.cpu.dtb.write_acv 391 # DTB write access violations -system.cpu.dtb.write_accesses 340693 # DTB write accesses -system.cpu.dtb.data_hits 16622340 # DTB hits -system.cpu.dtb.data_misses 54000 # DTB misses -system.cpu.dtb.data_acv 885 # DTB access violations -system.cpu.dtb.data_accesses 1298579 # DTB accesses -system.cpu.itb.fetch_hits 1343669 # ITB hits -system.cpu.itb.fetch_misses 37345 # ITB misses -system.cpu.itb.fetch_acv 1146 # ITB acv -system.cpu.itb.fetch_accesses 1381014 # ITB accesses +system.cpu.dtb.read_hits 9968108 # DTB read hits +system.cpu.dtb.read_misses 43556 # DTB read misses +system.cpu.dtb.read_acv 496 # DTB read access violations +system.cpu.dtb.read_accesses 957960 # DTB read accesses +system.cpu.dtb.write_hits 6640476 # DTB write hits +system.cpu.dtb.write_misses 10042 # DTB write misses +system.cpu.dtb.write_acv 402 # DTB write access violations +system.cpu.dtb.write_accesses 340316 # DTB write accesses +system.cpu.dtb.data_hits 16608584 # DTB hits +system.cpu.dtb.data_misses 53598 # DTB misses +system.cpu.dtb.data_acv 898 # DTB access violations +system.cpu.dtb.data_accesses 1298276 # DTB accesses +system.cpu.itb.fetch_hits 1341124 # ITB hits +system.cpu.itb.fetch_misses 40235 # ITB misses +system.cpu.itb.fetch_acv 1160 # ITB acv +system.cpu.itb.fetch_accesses 1381359 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -354,143 +366,143 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 122571263 # number of cpu cycles simulated +system.cpu.numCycles 122531860 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14075987 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11741614 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 452517 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10126525 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5926302 # Number of BTB hits +system.cpu.BPredUnit.lookups 14045558 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11719354 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 447776 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10129156 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5920510 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 942334 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45003 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31564050 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 71567580 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14075987 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6868636 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13486844 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2151091 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 41804632 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33708 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 276041 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 314295 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 187 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8859322 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 305645 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 88896899 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.805063 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.137281 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 939631 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 44501 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31544288 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 71453130 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14045558 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6860141 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13465921 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2135846 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 41803348 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 34171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 276891 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 309124 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8845261 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 302298 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 88840406 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.804286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.136255 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75410055 84.83% 84.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 885656 1.00% 85.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1762066 1.98% 87.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 856601 0.96% 88.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2772547 3.12% 91.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 605003 0.68% 92.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 676052 0.76% 93.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1014878 1.14% 94.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4914041 5.53% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75374485 84.84% 84.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 882693 0.99% 85.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1758870 1.98% 87.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 855110 0.96% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2773745 3.12% 91.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 603499 0.68% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 673337 0.76% 93.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1014466 1.14% 94.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4904201 5.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 88896899 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.114839 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.583885 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32604567 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 41610698 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12250426 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1057078 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1374129 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 617310 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43428 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 70293890 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 133239 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1374129 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33752767 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 16324711 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21058224 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11548980 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4838086 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66572257 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7187 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 753146 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1801877 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44498273 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80714962 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 80226097 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 488865 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38261328 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6236937 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1703640 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251709 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12757763 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10570492 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6981683 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1316603 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 922104 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58981346 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2097651 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57326676 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 120953 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7579711 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3887654 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1429592 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 88896899 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.644867 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.291957 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 88840406 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.114628 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.583139 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32595578 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 41593167 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12233698 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1054489 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1363473 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 614789 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43441 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 70185288 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 133206 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1363473 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33740803 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 16340010 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21029757 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11532133 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4834228 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66486071 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7165 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 750706 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1800875 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 44431145 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80611615 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 80123142 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 488473 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38259358 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6171779 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1702958 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251555 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12743501 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10564267 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6974375 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1310956 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 921637 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58920823 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2093860 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57272597 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 128544 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7527772 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3875760 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1425872 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 88840406 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.644668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.291770 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 62967728 70.83% 70.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 12048856 13.55% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5390899 6.06% 90.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3449544 3.88% 94.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2613461 2.94% 97.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1329807 1.50% 98.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 686975 0.77% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 354371 0.40% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 55258 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 62934632 70.84% 70.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 12040664 13.55% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5383860 6.06% 90.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3443587 3.88% 94.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2613267 2.94% 97.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1328836 1.50% 98.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 686879 0.77% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 354518 0.40% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 54163 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 88896899 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 88840406 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 75491 10.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 363771 48.19% 58.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 315594 41.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 73519 9.73% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 364094 48.19% 57.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 318003 42.09% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7291 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39127581 68.25% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61956 0.11% 68.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39090989 68.25% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61973 0.11% 68.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.42% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued @@ -517,116 +529,116 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10418296 18.17% 86.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6729507 11.74% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952802 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10411715 18.18% 86.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6718707 11.73% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952679 1.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57326676 # Type of FU issued -system.cpu.iq.rate 0.467701 # Inst issue rate -system.cpu.iq.fu_busy_cnt 754856 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013168 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 203729346 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68333375 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 56036726 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 696713 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 339202 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327718 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57709702 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 364539 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 594776 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57272597 # Type of FU issued +system.cpu.iq.rate 0.467410 # Inst issue rate +system.cpu.iq.fu_busy_cnt 755616 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013193 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 203573547 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68217667 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55990659 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 696212 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 338599 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327577 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57656594 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 364328 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 594908 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1456655 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2870 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14252 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 588832 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1450991 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2769 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14176 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 581838 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18348 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 104302 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18337 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 105015 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1374129 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 11393417 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 869281 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64652535 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 684492 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10570492 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6981683 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1845589 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 621506 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12714 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14252 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 241539 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 423865 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 665404 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56791406 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10044983 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 535269 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1363473 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11404151 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 871964 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64586243 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 684405 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10564267 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6974375 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1841535 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 624319 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12765 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14176 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 237440 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 422569 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 660009 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56745623 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10040371 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 526973 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3573538 # number of nop insts executed -system.cpu.iew.exec_refs 16720258 # number of memory reference insts executed -system.cpu.iew.exec_branches 9005988 # Number of branches executed -system.cpu.iew.exec_stores 6675275 # Number of stores executed -system.cpu.iew.exec_rate 0.463334 # Inst execution rate -system.cpu.iew.wb_sent 56476627 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56364444 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27797872 # num instructions producing a value -system.cpu.iew.wb_consumers 37663953 # num instructions consuming a value +system.cpu.iew.exec_nop 3571560 # number of nop insts executed +system.cpu.iew.exec_refs 16706164 # number of memory reference insts executed +system.cpu.iew.exec_branches 8999941 # Number of branches executed +system.cpu.iew.exec_stores 6665793 # Number of stores executed +system.cpu.iew.exec_rate 0.463109 # Inst execution rate +system.cpu.iew.wb_sent 56430087 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56318236 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27772479 # num instructions producing a value +system.cpu.iew.wb_consumers 37631426 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.459850 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738050 # average fanout of values written-back +system.cpu.iew.wb_rate 0.459621 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738013 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56288834 # The number of committed instructions -system.cpu.commit.commitCommittedOps 56288834 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 8251602 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 668059 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 621198 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 87522770 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.643134 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.558246 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56285915 # The number of committed instructions +system.cpu.commit.commitCommittedOps 56285915 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 8189376 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667988 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 616441 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 87476933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.643437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.558745 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 66254825 75.70% 75.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8962066 10.24% 85.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4828588 5.52% 91.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2603942 2.98% 94.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1449491 1.66% 96.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 603705 0.69% 96.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 515511 0.59% 97.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 488925 0.56% 97.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1815717 2.07% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 66214375 75.69% 75.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8956758 10.24% 85.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4831410 5.52% 91.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2600718 2.97% 94.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1447358 1.65% 96.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 605400 0.69% 96.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 515608 0.59% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 488345 0.56% 97.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1816961 2.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 87522770 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56288834 # Number of instructions committed -system.cpu.commit.committedOps 56288834 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 87476933 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56285915 # Number of instructions committed +system.cpu.commit.committedOps 56285915 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15506688 # Number of memory references committed -system.cpu.commit.loads 9113837 # Number of loads committed -system.cpu.commit.membars 227975 # Number of memory barriers committed -system.cpu.commit.branches 8463674 # Number of branches committed +system.cpu.commit.refs 15505813 # Number of memory references committed +system.cpu.commit.loads 9113276 # Number of loads committed +system.cpu.commit.membars 227944 # Number of memory barriers committed +system.cpu.commit.branches 8463135 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52126817 # Number of committed integer instructions. -system.cpu.commit.function_calls 744625 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1815717 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52124087 # Number of committed integer instructions. +system.cpu.commit.function_calls 744545 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1816961 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149996318 # The number of ROB reads -system.cpu.rob.rob_writes 130455868 # The number of ROB writes -system.cpu.timesIdled 1387986 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33674364 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3608226532 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 53094243 # Number of Instructions Simulated -system.cpu.committedOps 53094243 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 53094243 # Number of Instructions Simulated -system.cpu.cpi 2.308560 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.308560 # CPI: Total CPI of All Threads -system.cpu.ipc 0.433170 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.433170 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74446052 # number of integer regfile reads -system.cpu.int_regfile_writes 40661007 # number of integer regfile writes -system.cpu.fp_regfile_reads 166346 # number of floating regfile reads -system.cpu.fp_regfile_writes 166939 # number of floating regfile writes -system.cpu.misc_regfile_reads 1998850 # number of misc regfile reads -system.cpu.misc_regfile_writes 950370 # number of misc regfile writes +system.cpu.rob.rob_reads 149884134 # The number of ROB reads +system.cpu.rob.rob_writes 130314855 # The number of ROB writes +system.cpu.timesIdled 1389359 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 33691454 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3606309626 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 53091408 # Number of Instructions Simulated +system.cpu.committedOps 53091408 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 53091408 # Number of Instructions Simulated +system.cpu.cpi 2.307941 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.307941 # CPI: Total CPI of All Threads +system.cpu.ipc 0.433287 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.433287 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74386687 # number of integer regfile reads +system.cpu.int_regfile_writes 40627933 # number of integer regfile writes +system.cpu.fp_regfile_reads 166209 # number of floating regfile reads +system.cpu.fp_regfile_writes 166935 # number of floating regfile writes +system.cpu.misc_regfile_reads 1998011 # number of misc regfile reads +system.cpu.misc_regfile_writes 950291 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -658,247 +670,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1025209 # number of replacements -system.cpu.icache.tagsinuse 509.960172 # Cycle average of tags in use -system.cpu.icache.total_refs 7772148 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1025718 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.577276 # Average number of references to valid blocks. +system.cpu.icache.replacements 1024388 # number of replacements +system.cpu.icache.tagsinuse 509.959478 # Cycle average of tags in use +system.cpu.icache.total_refs 7759501 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1024896 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.571013 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 23722278000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.960172 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996016 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996016 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7772149 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7772149 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7772149 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7772149 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7772149 # number of overall hits -system.cpu.icache.overall_hits::total 7772149 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1087170 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1087170 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1087170 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1087170 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1087170 # number of overall misses -system.cpu.icache.overall_misses::total 1087170 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17528418489 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17528418489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17528418489 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17528418489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17528418489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17528418489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8859319 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8859319 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8859319 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8859319 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8859319 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8859319 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122715 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.122715 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122715 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.122715 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122715 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.122715 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16122.978457 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16122.978457 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16122.978457 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16122.978457 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16122.978457 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16122.978457 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1581994 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 509.959478 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996015 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996015 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7759502 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7759502 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7759502 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7759502 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7759502 # number of overall hits +system.cpu.icache.overall_hits::total 7759502 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1085755 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1085755 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1085755 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1085755 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1085755 # number of overall misses +system.cpu.icache.overall_misses::total 1085755 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17501015990 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17501015990 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17501015990 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17501015990 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17501015990 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17501015990 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8845257 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8845257 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8845257 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8845257 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8845257 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8845257 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122750 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.122750 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.122750 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.122750 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.122750 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.122750 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16118.752380 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16118.752380 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16118.752380 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16118.752380 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16118.752380 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16118.752380 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1777494 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 196 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 208 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 8071.397959 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 8545.644231 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 238 # number of writebacks -system.cpu.icache.writebacks::total 238 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61204 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 61204 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 61204 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 61204 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 61204 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 61204 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1025966 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1025966 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1025966 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1025966 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1025966 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1025966 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13510508994 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13510508994 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13510508994 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13510508994 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13510508994 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13510508994 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115806 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115806 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115806 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115806 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115806 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115806 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13168.573807 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13168.573807 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13168.573807 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13168.573807 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13168.573807 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13168.573807 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60612 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 60612 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 60612 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 60612 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 60612 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 60612 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1025143 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1025143 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1025143 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1025143 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1025143 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1025143 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13492714994 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13492714994 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13492714994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13492714994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13492714994 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13492714994 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115897 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115897 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115897 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115897 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115897 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115897 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13161.788154 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13161.788154 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13161.788154 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13161.788154 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13161.788154 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13161.788154 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1403926 # number of replacements -system.cpu.dcache.tagsinuse 511.995922 # Cycle average of tags in use -system.cpu.dcache.total_refs 11884045 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1404438 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.461780 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1403592 # number of replacements +system.cpu.dcache.tagsinuse 511.995920 # Cycle average of tags in use +system.cpu.dcache.total_refs 11877954 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1404104 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.459455 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 19693000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995922 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.995920 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7283526 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7283526 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4189382 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4189382 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 190687 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 190687 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 220149 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 220149 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11472908 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11472908 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11472908 # number of overall hits -system.cpu.dcache.overall_hits::total 11472908 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1829585 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1829585 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1968134 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1968134 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23417 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23417 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 7277634 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7277634 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4189219 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4189219 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 190679 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 190679 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 220144 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 220144 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11466853 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11466853 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11466853 # number of overall hits +system.cpu.dcache.overall_hits::total 11466853 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1830581 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1830581 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1967996 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1967996 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23423 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23423 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3797719 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3797719 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3797719 # number of overall misses -system.cpu.dcache.overall_misses::total 3797719 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 48849966500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 48849966500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 74989002011 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 74989002011 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 432032000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 432032000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 56500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 56500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 123838968511 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 123838968511 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 123838968511 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 123838968511 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9113111 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9113111 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6157516 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157516 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 214104 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 214104 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 220153 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 220153 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15270627 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15270627 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15270627 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15270627 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200764 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.200764 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319631 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.319631 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109372 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109372 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 3798577 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3798577 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3798577 # number of overall misses +system.cpu.dcache.overall_misses::total 3798577 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 48883672000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 48883672000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 74930562797 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 74930562797 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 428682000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 428682000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 98000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 98000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 123814234797 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 123814234797 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 123814234797 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 123814234797 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9108215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9108215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6157215 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157215 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 214102 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 214102 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 220148 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 220148 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15265430 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15265430 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15265430 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15265430 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200981 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200981 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.319624 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109401 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109401 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000018 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000018 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.248694 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.248694 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.248694 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.248694 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26700.025689 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26700.025689 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38101.573374 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38101.573374 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18449.502498 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18449.502498 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14125 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14125 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32608.776087 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32608.776087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32608.776087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32608.776087 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 732928021 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.248835 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.248835 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.248835 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.248835 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26703.910944 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26703.910944 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38074.550353 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38074.550353 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18301.754686 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18301.754686 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 24500 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 24500 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32594.899300 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32594.899300 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32594.899300 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32594.899300 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 731758024 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 72145 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 72544 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10159.096556 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10087.092303 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 842954 # number of writebacks -system.cpu.dcache.writebacks::total 842954 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 743747 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 743747 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667534 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1667534 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5230 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5230 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2411281 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2411281 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2411281 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2411281 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085838 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1085838 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300600 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300600 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18187 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 18187 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 842689 # number of writebacks +system.cpu.dcache.writebacks::total 842689 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 745053 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 745053 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667452 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1667452 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5206 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5206 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2412505 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2412505 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2412505 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2412505 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085528 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1085528 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300544 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300544 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18217 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 18217 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1386438 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1386438 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1386438 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1386438 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28239740000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 28239740000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9650792448 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9650792448 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 273508500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 273508500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 44000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 44000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37890532448 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37890532448 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37890532448 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37890532448 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 905949500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 905949500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1225663998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1225663998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2131613498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 2131613498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119151 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119151 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048818 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048818 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084945 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084945 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1386072 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1386072 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1386072 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1386072 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28234901500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28234901500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9648960448 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9648960448 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 269943500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 269943500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 85500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 85500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37883861948 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37883861948 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37883861948 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37883861948 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904971500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904971500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1224983998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1224983998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2129955498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2129955498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119181 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119181 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048812 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048812 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085086 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085086 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000018 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000018 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090791 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090791 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090791 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26007.323376 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26007.323376 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32105.097964 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32105.097964 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15038.681476 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15038.681476 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27329.409933 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27329.409933 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27329.409933 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27329.409933 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090798 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090798 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090798 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090798 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26010.293148 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26010.293148 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32104.984455 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32104.984455 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14818.219246 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14818.219246 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 21375 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 21375 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27331.813894 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27331.813894 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27331.813894 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27331.813894 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -907,28 +917,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211694 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74899 40.95% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 247 0.14% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1887 1.03% 42.11% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105884 57.89% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182917 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73532 49.28% 49.28% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 247 0.17% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1887 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73537 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149203 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1825754390000 97.87% 97.87% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 99081000 0.01% 97.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 381309500 0.02% 97.90% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 39166410000 2.10% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1865401190500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6430 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211669 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74897 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 243 0.13% 41.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1886 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105867 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182893 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73530 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1886 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73533 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149192 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1824783514500 97.87% 97.87% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 98568000 0.01% 97.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 384878500 0.02% 97.90% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 39156084500 2.10% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1864423045500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694505 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815687 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694579 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815734 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -967,29 +977,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175564 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175546 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6791 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5223 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5220 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192535 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5955 # number of protection mode switches +system.cpu.kern.callpal::total 192513 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5956 # number of protection mode switches system.cpu.kern.mode_switch::user 1736 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2110 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches system.cpu.kern.mode_good::kernel 1906 system.cpu.kern.mode_good::user 1736 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320067 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320013 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080569 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.388940 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29632954500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2782152500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832986075500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.389059 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29626491000 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2782272500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832014274000 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 7eac6f043..35fda0d55 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -168,7 +168,7 @@ type=O3Checker children=dtb itb tracer checker=Null clock=1 -cpu_id=-1 +cpu_id=0 defer_registration=false do_checkpoint_insts=true do_quiesce=true @@ -640,7 +640,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 3620c0fb4..8990e0cd7 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -4,31 +4,8 @@ warn: Sockets disabled, not accepting gdb connections warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -warn: The ccsidr register isn't implemented and always reads as 0. -warn: instruction 'mcr bpiallis' unimplemented -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr dccimvac' unimplemented -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: 5800930000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 5810491000: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 5849158000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 5865375000: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 6307702500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 -warn: LCD dual screen mode not supported -warn: 53639390500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented -warn: 2456135822500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2468351819500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2488200522500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2488780405500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2494975875500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2496192426500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2496193716500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 -warn: 2496816594500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 -hack: be nice to actually delete the event here +panic: Not supported on checker! + @ cycle 197694500 +[getInstPort:build/ARM/cpu/checker/cpu.hh, line 130] +Memory Usage: 355632 KBytes +Program aborted at cycle 197694500 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index f106f905a..8772dfecb 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 17:05:39 +gem5 compiled Jul 26 2012 21:40:00 +gem5 started Jul 27 2012 02:25:32 gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2502549875500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 4976e4992..e69de29bb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,978 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.502550 # Number of seconds simulated -sim_ticks 2502549875500 # Number of ticks simulated -final_tick 2502549875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75474 # Simulator instruction rate (inst/s) -host_op_rate 97450 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3170228022 # Simulator tick rate (ticks/s) -host_mem_usage 386888 # Number of bytes of host memory used -host_seconds 789.39 # Real time elapsed on the host -sim_insts 59578267 # Number of instructions simulated -sim_ops 76925839 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 118994504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 800128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory -system.physmem.bytes_read::total 128893400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 800128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 800128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6802248 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14874313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 59 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12502 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15029017 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813177 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47549304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 319725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3634264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51504828 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 319725 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 319725 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1512927 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1205200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2718127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1512927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47549304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 319725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4839464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54222954 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64431 # number of replacements -system.l2c.tagsinuse 51237.782352 # Cycle average of tags in use -system.l2c.total_refs 2028510 # Total number of references to valid blocks. -system.l2c.sampled_refs 129827 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.624716 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2492014554000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36760.884600 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 47.476285 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.000184 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8187.042847 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6242.378435 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.560927 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000724 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124924 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.095251 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.781827 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 121963 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11826 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 977935 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 383708 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1495432 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 675442 # number of Writeback hits -system.l2c.Writeback_hits::total 675442 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112737 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112737 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 121963 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11826 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 977935 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 496445 # number of demand (read+write) hits -system.l2c.demand_hits::total 1608169 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 121963 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11826 # number of overall hits -system.l2c.overall_hits::cpu.inst 977935 # number of overall hits -system.l2c.overall_hits::cpu.data 496445 # number of overall hits -system.l2c.overall_hits::total 1608169 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 59 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12384 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23135 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2909 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133229 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133229 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 59 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12384 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143920 # number of demand (read+write) misses -system.l2c.demand_misses::total 156364 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 59 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu.inst 12384 # number of overall misses -system.l2c.overall_misses::cpu.data 143920 # number of overall misses -system.l2c.overall_misses::total 156364 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3091500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 659591498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 562236498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1224979496 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 944500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 944500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7069904999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7069904999 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 3091500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 659591498 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7632141497 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8294884495 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 3091500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 659591498 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 7632141497 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8294884495 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 122022 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 11827 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 990319 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 394399 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1518567 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 675442 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 675442 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2951 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2951 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 245966 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 245966 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 122022 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 11827 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 990319 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 640365 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1764533 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 122022 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 11827 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 990319 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 640365 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1764533 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000484 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.012505 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.027107 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015235 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.985768 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.985768 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.157895 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.157895 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.541656 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541656 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000484 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.012505 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.224747 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.088615 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000484 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.012505 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.224747 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.088615 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52398.305085 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 53261.587371 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52589.701431 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52949.189367 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 324.682021 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 324.682021 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 53065.811490 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53065.811490 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 53048.556541 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 53048.556541 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59159 # number of writebacks -system.l2c.writebacks::total 59159 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.inst 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 71 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 59 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 12375 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 10629 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23064 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 133229 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133229 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 59 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 12375 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 143858 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156293 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 59 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 12375 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 143858 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156293 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2372000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 508160500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 430170499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 940750999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116825000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 116825000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5436034999 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5436034999 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2372000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 508160500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 5866205498 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6376785998 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2372000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 508160500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 5866205498 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6376785998 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5323000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131417115000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131422438000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31373446015 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 31373446015 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5323000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 162790561015 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 162795884015 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026950 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015188 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985768 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.985768 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541656 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541656 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088575 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088575 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41063.474747 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40471.398909 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40788.718306 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40159.848745 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40159.848745 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40802.190206 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40802.190206 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.checker.dtb.inst_hits 0 # ITB inst hits -system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15048164 # DTB read hits -system.cpu.checker.dtb.read_misses 7309 # DTB read misses -system.cpu.checker.dtb.write_hits 11293826 # DTB write hits -system.cpu.checker.dtb.write_misses 2190 # DTB write misses -system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB -system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 177 # Number of TLB faults due to prefetch -system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15055473 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11296016 # DTB write accesses -system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26341990 # DTB hits -system.cpu.checker.dtb.misses 9499 # DTB misses -system.cpu.checker.dtb.accesses 26351489 # DTB accesses -system.cpu.checker.itb.inst_hits 60744881 # ITB inst hits -system.cpu.checker.itb.inst_misses 4471 # ITB inst misses -system.cpu.checker.itb.read_hits 0 # DTB read hits -system.cpu.checker.itb.read_misses 0 # DTB read misses -system.cpu.checker.itb.write_hits 0 # DTB write hits -system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB -system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.itb.read_accesses 0 # DTB read accesses -system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 60749352 # ITB inst accesses -system.cpu.checker.itb.hits 60744881 # DTB hits -system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 60749352 # DTB accesses -system.cpu.checker.numCycles 77204260 # number of cpu cycles simulated -system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51771660 # DTB read hits -system.cpu.dtb.read_misses 81258 # DTB read misses -system.cpu.dtb.write_hits 11880398 # DTB write hits -system.cpu.dtb.write_misses 17961 # DTB write misses -system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 8043 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3044 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 609 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1282 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51852918 # DTB read accesses -system.cpu.dtb.write_accesses 11898359 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63652058 # DTB hits -system.cpu.dtb.misses 99219 # DTB misses -system.cpu.dtb.accesses 63751277 # DTB accesses -system.cpu.itb.inst_hits 13142261 # ITB inst hits -system.cpu.itb.inst_misses 12247 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5262 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13154508 # ITB inst accesses -system.cpu.itb.hits 13142261 # DTB hits -system.cpu.itb.misses 12247 # DTB misses -system.cpu.itb.accesses 13154508 # DTB accesses -system.cpu.numCycles 413642740 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14974990 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11915620 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 753400 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10068197 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7820088 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1448775 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 80927 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33422471 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 99542070 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14974990 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9268863 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21759182 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6002262 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 163536 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 93319816 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133610 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208459 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 397 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13138017 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1024097 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6504 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 153128307 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.804842 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.182667 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131386008 85.80% 85.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1369017 0.89% 86.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1759019 1.15% 87.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2640315 1.72% 89.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1819667 1.19% 90.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1142419 0.75% 91.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2920911 1.91% 93.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 807762 0.53% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9283189 6.06% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 153128307 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.036203 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.240647 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35537493 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 93048586 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19509299 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1086349 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3946580 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2100058 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174557 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116122172 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568338 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3946580 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37621271 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39594801 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46881047 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18412397 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6672211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 108597287 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4175 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1156489 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4484156 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 30967 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 113073752 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 499820515 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 499727174 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 93341 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77686691 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35387060 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898607 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797702 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13307124 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21058263 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13875749 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1965166 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2564814 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 99781831 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1555350 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124613166 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 199798 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23638127 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65777806 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 268083 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 153128307 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.813783 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.516400 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107849903 70.43% 70.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14560254 9.51% 79.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7302452 4.77% 84.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5913038 3.86% 88.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12593494 8.22% 96.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2809204 1.83% 98.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1536315 1.00% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 438168 0.29% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125479 0.08% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 153128307 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53462 0.61% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8367005 94.75% 95.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 409700 4.64% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 106530 0.09% 0.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58482659 46.93% 47.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95330 0.08% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 11 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53414157 42.86% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12512351 10.04% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124613166 # Type of FU issued -system.cpu.iq.rate 0.301258 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8830169 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070861 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 411460543 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124996425 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85630389 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22925 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12868 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10343 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 133324707 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12098 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 646336 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5343093 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11106 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35068 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2077574 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107202 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1049886 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3946580 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29463666 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540836 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 101593235 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 217276 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21058263 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13875749 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 964547 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 125689 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 40656 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35068 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 381127 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332167 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 713294 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121438397 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52461807 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3174769 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 256054 # number of nop insts executed -system.cpu.iew.exec_refs 64853171 # number of memory reference insts executed -system.cpu.iew.exec_branches 11412736 # Number of branches executed -system.cpu.iew.exec_stores 12391364 # Number of stores executed -system.cpu.iew.exec_rate 0.293583 # Inst execution rate -system.cpu.iew.wb_sent 120063166 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85640732 # cumulative count of insts written-back -system.cpu.iew.wb_producers 46459932 # num instructions producing a value -system.cpu.iew.wb_consumers 84649521 # num instructions consuming a value -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.207040 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.548851 # average fanout of values written-back -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59728648 # The number of committed instructions -system.cpu.commit.commitCommittedOps 77076220 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 24329020 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1287267 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625309 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149264139 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.516375 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.492760 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121340444 81.29% 81.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13976446 9.36% 90.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3929866 2.63% 93.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2230737 1.49% 94.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1774137 1.19% 95.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1064202 0.71% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1398926 0.94% 97.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 658331 0.44% 98.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2891050 1.94% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149264139 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59728648 # Number of instructions committed -system.cpu.commit.committedOps 77076220 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27513345 # Number of memory references committed -system.cpu.commit.loads 15715170 # Number of loads committed -system.cpu.commit.membars 413057 # Number of memory barriers committed -system.cpu.commit.branches 9904308 # Number of branches committed -system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68616986 # Number of committed integer instructions. -system.cpu.commit.function_calls 995953 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2891050 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 246021016 # The number of ROB reads -system.cpu.rob.rob_writes 206855771 # The number of ROB writes -system.cpu.timesIdled 1910853 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260514433 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4591368963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59578267 # Number of Instructions Simulated -system.cpu.committedOps 76925839 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59578267 # Number of Instructions Simulated -system.cpu.cpi 6.942846 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.942846 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144033 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.144033 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 551124725 # number of integer regfile reads -system.cpu.int_regfile_writes 87730819 # number of integer regfile writes -system.cpu.fp_regfile_reads 8186 # number of floating regfile reads -system.cpu.fp_regfile_writes 2858 # number of floating regfile writes -system.cpu.misc_regfile_reads 131789755 # number of misc regfile reads -system.cpu.misc_regfile_writes 912697 # number of misc regfile writes -system.cpu.icache.replacements 991190 # number of replacements -system.cpu.icache.tagsinuse 511.611770 # Cycle average of tags in use -system.cpu.icache.total_refs 12061455 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991702 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.162378 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6426198000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.611770 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999242 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999242 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12061455 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12061455 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12061455 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12061455 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12061455 # number of overall hits -system.cpu.icache.overall_hits::total 12061455 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1076423 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1076423 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1076423 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1076423 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1076423 # number of overall misses -system.cpu.icache.overall_misses::total 1076423 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16851120991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16851120991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16851120991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16851120991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16851120991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16851120991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13137878 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13137878 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13137878 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13137878 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13137878 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13137878 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081933 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081933 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081933 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081933 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081933 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15654.738881 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15654.738881 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15654.738881 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15654.738881 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2871493 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 461 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6228.835141 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 67899 # number of writebacks -system.cpu.icache.writebacks::total 67899 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84680 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84680 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84680 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84680 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84680 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84680 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991743 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 991743 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 991743 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 991743 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 991743 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 991743 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12825867499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12825867499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12825867499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12825867499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12825867499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12825867499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075487 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075487 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075487 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12932.652410 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12932.652410 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643139 # number of replacements -system.cpu.dcache.tagsinuse 511.991335 # Cycle average of tags in use -system.cpu.dcache.total_refs 21733833 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643651 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.766487 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991335 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13904166 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13904166 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7257095 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7257095 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 283844 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 283844 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285639 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285639 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21161261 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21161261 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21161261 # number of overall hits -system.cpu.dcache.overall_hits::total 21161261 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 765252 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 765252 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2993311 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2993311 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13765 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13765 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3758563 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3758563 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3758563 # number of overall misses -system.cpu.dcache.overall_misses::total 3758563 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14844603000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14844603000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129412035593 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129412035593 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223977000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 223977000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 405000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 405000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144256638593 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144256638593 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144256638593 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144256638593 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14669418 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14669418 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250406 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250406 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297609 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 297609 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285658 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285658 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24919824 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24919824 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24919824 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24919824 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052166 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052166 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292019 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.292019 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046252 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046252 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000067 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000067 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.150826 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.150826 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.150826 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.150826 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19398.319769 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19398.319769 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43233.742031 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43233.742031 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16271.485652 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16271.485652 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21315.789474 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21315.789474 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38380.795691 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38380.795691 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32633902 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7260500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7285 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4479.602196 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 25655.477032 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607543 # number of writebacks -system.cpu.dcache.writebacks::total 607543 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379767 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 379767 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744505 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2744505 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3124272 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3124272 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3124272 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3124272 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385485 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385485 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248806 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248806 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12312 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12312 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634291 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634291 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634291 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634291 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6242554097 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6242554097 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9246380950 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9246380950 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164108000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164108000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 341500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 341500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15488935047 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15488935047 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15488935047 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15488935047 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147082070000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147082070000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41215087708 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41215087708 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188297157708 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 188297157708 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024273 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024273 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041370 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041370 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000067 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000067 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025453 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025453 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16194.025960 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16194.025960 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37163.014357 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37163.014357 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13329.109812 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13329.109812 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17973.684211 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17973.684211 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1298563544001 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1298563544001 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88049 # number of quiesce instructions executed - ----------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 8ee00f929..7a79f323f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem midr_regval=890224640 multi_proc=true num_work_ids=16 @@ -1023,7 +1023,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 6f1b9eba3..523f8a126 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -10,10 +10,10 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index fe27005da..904402304 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 17:16:08 +gem5 compiled Jul 26 2012 21:40:00 +gem5 started Jul 27 2012 02:25:35 gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2581527583500 because m5_exit instruction encountered +Exiting @ tick 2582310281500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index ba015b214..977ccc85a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,16 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.581528 # Number of seconds simulated -sim_ticks 2581527583500 # Number of ticks simulated -final_tick 2581527583500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.582310 # Number of seconds simulated +sim_ticks 2582310281500 # Number of ticks simulated +final_tick 2582310281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89313 # Simulator instruction rate (inst/s) -host_op_rate 115365 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3717496726 # Simulator tick rate (ticks/s) -host_mem_usage 390980 # Number of bytes of host memory used -host_seconds 694.43 # Real time elapsed on the host -sim_insts 62021206 # Number of instructions simulated -sim_ops 80112751 # Number of ops (including micro ops) simulated +host_inst_rate 62666 # Simulator instruction rate (inst/s) +host_op_rate 80652 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2566586582 # Simulator tick rate (ticks/s) +host_mem_usage 395816 # Number of bytes of host memory used +host_seconds 1006.13 # Real time elapsed on the host +sim_insts 63050246 # Number of instructions simulated +sim_ops 81146063 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 396544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4372212 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 425600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5220016 # Number of bytes read from this memory +system.physmem.bytes_read::total 129953444 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 396544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 425600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 822144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4241024 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7270160 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6196 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68388 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6650 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81589 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15105053 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66266 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823550 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46290976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 153562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1693140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 273 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 164814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2021452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50324488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 153562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 164814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318375 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1642337 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1166450 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2815370 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1642337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46290976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 153562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1699723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 164814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3187902 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53139859 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory @@ -29,292 +84,237 @@ system.realview.nvmem.bw_inst_read::total 149 # I system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 395008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4372084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 425536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5226480 # Number of bytes read from this memory -system.physmem.bytes_read::total 129958756 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 395008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 425536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 820544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244480 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7273616 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6172 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6649 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81690 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15105136 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66320 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823604 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46305011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 153013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1693603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 164839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2024569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50341804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 153013 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 164839 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317852 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1644174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6585 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1166804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2817563 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1644174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46305011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 153013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1700189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 164839 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3191372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53159367 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72536 # number of replacements -system.l2c.tagsinuse 53024.626088 # Cycle average of tags in use -system.l2c.total_refs 2019266 # Total number of references to valid blocks. -system.l2c.sampled_refs 137732 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.660834 # Average number of references to valid blocks. +system.l2c.replacements 72453 # number of replacements +system.l2c.tagsinuse 52989.750711 # Cycle average of tags in use +system.l2c.total_refs 1967154 # Total number of references to valid blocks. +system.l2c.sampled_refs 137652 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.290777 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37701.415204 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.259804 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000179 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4215.968317 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2959.624437 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 13.637835 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4028.150256 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4102.570055 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.575278 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000050 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 37689.434458 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.667894 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.004429 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4220.453796 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2953.326384 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 6.708393 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4009.126872 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4107.028485 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.575095 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000056 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064331 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.045160 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000208 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061465 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062600 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809092 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 53338 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6106 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 398719 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 164464 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 78886 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6452 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 615129 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 199702 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1522796 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 645710 # number of Writeback hits -system.l2c.Writeback_hits::total 645710 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1043 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 806 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1849 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 213 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 356 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48030 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 59189 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107219 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 53338 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6106 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 398719 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 212494 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 78886 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6452 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 615129 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 258891 # number of demand (read+write) hits -system.l2c.demand_hits::total 1630015 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 53338 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6106 # number of overall hits -system.l2c.overall_hits::cpu0.inst 398719 # number of overall hits -system.l2c.overall_hits::cpu0.data 212494 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 78886 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6452 # number of overall hits -system.l2c.overall_hits::cpu1.inst 615129 # number of overall hits -system.l2c.overall_hits::cpu1.data 258891 # number of overall hits -system.l2c.overall_hits::total 1630015 # number of overall hits +system.l2c.occ_percent::cpu0.inst 0.064399 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.045064 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000102 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.061174 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.062668 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.808559 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 54491 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6158 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 400629 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 165440 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 78380 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6682 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 615050 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 201442 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1528272 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 583270 # number of Writeback hits +system.l2c.Writeback_hits::total 583270 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1037 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 784 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1821 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 208 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 159 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 367 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48010 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 59262 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107272 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 54491 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 6158 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 400629 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 213450 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 78380 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6682 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 615050 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 260704 # number of demand (read+write) hits +system.l2c.demand_hits::total 1635544 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 54491 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 6158 # number of overall hits +system.l2c.overall_hits::cpu0.inst 400629 # number of overall hits +system.l2c.overall_hits::cpu0.data 213450 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 78380 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6682 # number of overall hits +system.l2c.overall_hits::cpu1.inst 615050 # number of overall hits +system.l2c.overall_hits::cpu1.data 260704 # number of overall hits +system.l2c.overall_hits::total 1635544 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6044 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6302 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 21 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6609 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6068 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6301 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6610 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 6328 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25314 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5683 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4287 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 9970 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 777 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 589 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1366 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63451 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76572 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140023 # number of ReadExReq misses +system.l2c.ReadReq_misses::total 25329 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5681 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4309 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 9990 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 780 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 578 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1358 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63459 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 76486 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139945 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6044 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69753 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 21 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6609 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 82900 # number of demand (read+write) misses -system.l2c.demand_misses::total 165337 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6068 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69760 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6610 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 82814 # number of demand (read+write) misses +system.l2c.demand_misses::total 165274 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 9 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6044 # number of overall misses -system.l2c.overall_misses::cpu0.data 69753 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 21 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6609 # number of overall misses -system.l2c.overall_misses::cpu1.data 82900 # number of overall misses -system.l2c.overall_misses::total 165337 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 471000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 60000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 322261499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 330895497 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1101000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 351559997 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 332583499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1338932492 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 20202500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 27410499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 47612999 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1721500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7138500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 8860000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3379920986 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4071556980 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7451477966 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 471000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 60000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 322261499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3710816483 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1101000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 351559997 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4404140479 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8790410458 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 471000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 60000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 322261499 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3710816483 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1101000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 351559997 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4404140479 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8790410458 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 53347 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6107 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 404763 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 170766 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 78907 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6452 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 621738 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 206030 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1548110 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 645710 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 645710 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6726 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6068 # number of overall misses +system.l2c.overall_misses::cpu0.data 69760 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6610 # number of overall misses +system.l2c.overall_misses::cpu1.data 82814 # number of overall misses +system.l2c.overall_misses::total 165274 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 470500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 112500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 323600498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 331027497 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 573500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 351706500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 332606499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1340097494 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 20411497 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 27614499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 48025996 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1617000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6615500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 8232500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3380389982 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4066537489 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7446927471 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 470500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 112500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 323600498 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3711417479 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 573500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 351706500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4399143988 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8787024965 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 470500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 112500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 323600498 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3711417479 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 573500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 351706500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4399143988 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8787024965 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 54500 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6160 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 406697 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 171741 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 78391 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6682 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 621660 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 207770 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1553601 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 583270 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 583270 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6718 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 5093 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 11819 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 990 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 732 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1722 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111481 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 135761 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247242 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 53347 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6107 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 404763 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 282247 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 78907 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6452 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 621738 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 341791 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1795352 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 53347 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6107 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 404763 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 282247 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 78907 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6452 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 621738 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 341791 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1795352 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000169 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000164 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014932 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036904 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000266 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010630 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030714 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016352 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.844930 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.841744 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.843557 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784848 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.804645 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.793264 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.569164 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.564021 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.566340 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000169 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000164 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014932 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.247135 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000266 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010630 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.242546 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.092092 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000169 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000164 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014932 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.247135 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000266 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010630 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.242546 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.092092 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52333.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 60000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53319.242058 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52506.426055 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52428.571429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53194.128764 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52557.442952 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52892.964052 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3554.900581 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6393.864941 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 4775.626780 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2215.572716 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12119.694397 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 6486.090776 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53268.206742 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53172.921956 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53216.099969 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52333.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 60000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 53319.242058 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 53199.381862 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52428.571429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 53194.128764 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 53125.940639 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 53166.626091 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52333.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 60000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 53319.242058 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 53199.381862 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52428.571429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 53194.128764 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 53125.940639 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 53166.626091 # average overall miss latency +system.l2c.UpgradeReq_accesses::total 11811 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 988 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 737 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1725 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111469 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 135748 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247217 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 54500 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6160 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 406697 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 283210 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 78391 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6682 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 621660 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 343518 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1800818 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 54500 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6160 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 406697 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 283210 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 78391 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6682 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 621660 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 343518 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1800818 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000165 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014920 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036689 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000140 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010633 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030457 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016303 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.845639 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.846063 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.845822 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.789474 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.784261 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.787246 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.569297 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.563441 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.566082 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000165 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000325 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014920 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.246319 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000140 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010633 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.241076 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.091777 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000165 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000325 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014920 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.246319 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000140 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010633 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.241076 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.091777 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52277.777778 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 56250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53329.020765 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52535.708142 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52136.363636 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53208.245083 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52561.077592 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52907.635280 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3592.940855 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6408.563240 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 4807.407007 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2073.076923 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11445.501730 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 6062.223859 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53268.881987 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53167.082721 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53213.244282 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52277.777778 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 56250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 53329.020765 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 53202.658816 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52136.363636 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 53208.245083 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 53120.776535 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53166.408298 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52277.777778 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 56250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 53329.020765 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 53202.658816 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52136.363636 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 53208.245083 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 53120.776535 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53166.408298 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,170 +323,168 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66320 # number of writebacks -system.l2c.writebacks::total 66320 # number of writebacks +system.l2c.writebacks::writebacks 66266 # number of writebacks +system.l2c.writebacks::total 66266 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 23 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0.data 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 40 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 40 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 73 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 71 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 9 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6039 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6063 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.data 6263 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 21 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6604 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6605 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 6305 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25242 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5683 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4287 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 9970 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 777 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 589 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1366 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63450 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 76572 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140022 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25258 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5681 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4309 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 9990 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 780 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 578 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1358 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63459 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 76486 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139945 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 9 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6039 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 69713 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 21 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6604 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 82877 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165264 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6063 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69722 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6605 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 82791 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165203 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 9 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6039 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 69713 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 21 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6604 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 82877 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165264 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 6063 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69722 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6605 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 82791 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165203 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 360000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 48000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 248302999 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 253032000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 846000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270719997 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 254713500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1028022496 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 227576000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 171718000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 399294000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31112500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23586500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 54699000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2608560498 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3134816489 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5743376987 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 88000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 249380499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 253173000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 440000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270856500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 254736000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1029033999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 227403000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 172571500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 399974500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31217000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23131000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 54348000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2608915998 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3130662995 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5739578993 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 360000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 48000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 248302999 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2861592498 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 846000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 270719997 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3389529989 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6771399483 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 88000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 249380499 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2862088998 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 440000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 270856500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3385398995 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6768612992 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 360000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 48000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 248302999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2861592498 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 846000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 270719997 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3389529989 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6771399483 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 88000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 249380499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2862088998 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 440000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 270856500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3385398995 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6768612992 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5579000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9186859000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9186576500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2133500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122397706500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131592278000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 704572999 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30781654107 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 31486227106 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122396919500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131591208500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 704511999 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30785024883 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31489536882 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5579000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9891431999 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9891088499 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2133500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 153179360607 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 163078505106 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036676 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030602 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016305 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.844930 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.841744 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.843557 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784848 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.804645 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.793264 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569155 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564021 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.566336 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.242479 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.092051 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.242479 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.092051 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 153181944383 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 163080745382 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000165 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000325 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014908 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036468 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000140 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030346 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016258 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.845639 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.846063 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.845822 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.789474 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784261 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.787246 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569297 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.563441 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.566082 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000165 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000325 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014908 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.246185 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000140 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.241009 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091738 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000165 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000325 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014908 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.246185 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000140 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.241009 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091738 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40401.085742 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40398.651864 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40726.665716 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40045.046630 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40055.516678 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40049.548646 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.827542 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40044.991511 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40043.191801 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41112.064586 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40939.462062 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41017.675701 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41131.535379 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40423.598914 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41007.797123 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40402.220460 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40740.913730 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40028.692132 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40049.083314 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.487487 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40021.794872 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40019.031142 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40020.618557 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41111.835957 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40931.189956 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41013.105098 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41048.190409 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40898.319063 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40973.227581 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41131.535379 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41050.012880 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41007.797123 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40890.905956 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40971.489573 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41048.190409 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40898.319063 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40973.227581 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41131.535379 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41050.012880 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41007.797123 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40890.905956 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40971.489573 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -509,27 +507,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9084255 # DTB read hits -system.cpu0.dtb.read_misses 36769 # DTB read misses -system.cpu0.dtb.write_hits 5284576 # DTB write hits -system.cpu0.dtb.write_misses 6773 # DTB write misses +system.cpu0.dtb.read_hits 9083896 # DTB read hits +system.cpu0.dtb.read_misses 37543 # DTB read misses +system.cpu0.dtb.write_hits 5286239 # DTB write hits +system.cpu0.dtb.write_misses 6882 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2261 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1412 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 383 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2244 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1393 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 382 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 588 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9121024 # DTB read accesses -system.cpu0.dtb.write_accesses 5291349 # DTB write accesses +system.cpu0.dtb.perms_faults 574 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9121439 # DTB read accesses +system.cpu0.dtb.write_accesses 5293121 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14368831 # DTB hits -system.cpu0.dtb.misses 43542 # DTB misses -system.cpu0.dtb.accesses 14412373 # DTB accesses -system.cpu0.itb.inst_hits 4421795 # ITB inst hits -system.cpu0.itb.inst_misses 5958 # ITB inst misses +system.cpu0.dtb.hits 14370135 # DTB hits +system.cpu0.dtb.misses 44425 # DTB misses +system.cpu0.dtb.accesses 14414560 # DTB accesses +system.cpu0.itb.inst_hits 4418601 # ITB inst hits +system.cpu0.itb.inst_misses 6114 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -538,542 +536,544 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1415 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1409 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1713 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1633 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4427753 # ITB inst accesses -system.cpu0.itb.hits 4421795 # DTB hits -system.cpu0.itb.misses 5958 # DTB misses -system.cpu0.itb.accesses 4427753 # DTB accesses -system.cpu0.numCycles 66112093 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4424715 # ITB inst accesses +system.cpu0.itb.hits 4418601 # DTB hits +system.cpu0.itb.misses 6114 # DTB misses +system.cpu0.itb.accesses 4424715 # DTB accesses +system.cpu0.numCycles 66354055 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6172143 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4680207 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 316413 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3902841 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 2861272 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6346252 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4857071 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 316053 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 4075974 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 3037671 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 700420 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 30889 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12972431 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32579396 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6172143 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3561692 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7636967 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1568394 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 92289 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 21876805 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 73340 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 91549 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 175 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4419869 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 175391 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2999 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 43870869 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.963501 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.353712 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 700378 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 30829 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 12963003 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 33274045 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6346252 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3738049 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7812188 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1602844 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 89446 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 22023764 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5932 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 73578 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 90886 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 179 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4416774 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 175280 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3223 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 44209960 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.971808 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.352806 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 36242473 82.61% 82.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 623814 1.42% 84.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 820212 1.87% 85.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 686089 1.56% 87.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 622737 1.42% 88.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 578948 1.32% 90.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 720296 1.64% 91.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 370745 0.85% 92.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3205555 7.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 36406101 82.35% 82.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 622907 1.41% 83.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 820090 1.85% 85.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 691511 1.56% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 794774 1.80% 88.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 578673 1.31% 90.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 721468 1.63% 91.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 370773 0.84% 92.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3203663 7.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 43870869 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.093359 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.492790 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 13461534 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21912526 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6836712 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 603785 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1056312 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 995110 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 66550 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40827533 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 217718 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1056312 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 14066817 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6153021 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13456769 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6788701 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2349249 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39593607 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1040 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 472233 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1335984 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 103 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39791095 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 179675714 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 179640853 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34861 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31537071 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8254023 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 463697 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 419128 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5673165 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7928571 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5881726 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1132931 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1238845 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37538443 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 794373 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37739879 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 92690 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6264606 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14354053 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 137507 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 43870869 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.860249 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.478315 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 44209960 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.095642 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.501462 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 13460475 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 22052761 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 7004876 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 606078 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1085770 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 992839 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 66349 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 41502146 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 217622 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1085770 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 14072541 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6178049 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13569314 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6948288 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2355998 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 40249124 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2572 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 473537 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1335703 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 188 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 40597200 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 181819083 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 181783808 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 35275 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31678350 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8918849 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 463403 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 418800 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5692374 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7927385 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5883720 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1132627 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1230816 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 38008933 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 947103 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 38247071 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 93468 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6756686 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14324325 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 258267 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 44209960 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.865123 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.479533 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 28164784 64.20% 64.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6326126 14.42% 78.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3234526 7.37% 85.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2361316 5.38% 91.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2098246 4.78% 96.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 936106 2.13% 98.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 514694 1.17% 99.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 181493 0.41% 99.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53578 0.12% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 28324155 64.07% 64.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6346765 14.36% 78.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3236431 7.32% 85.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2507997 5.67% 91.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2107881 4.77% 96.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 937016 2.12% 98.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 515116 1.17% 99.47% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 180639 0.41% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53960 0.12% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 43870869 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 44209960 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27565 2.58% 2.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 466 0.04% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 837939 78.44% 81.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 202337 18.94% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27715 2.59% 2.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 460 0.04% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 839091 78.45% 81.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 202283 18.91% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 20407 0.05% 0.05% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22494595 59.60% 59.66% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 50051 0.13% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9563453 25.34% 85.13% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5610668 14.87% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22968400 60.05% 60.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 50115 0.13% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 11 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9563149 25.00% 85.33% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5612341 14.67% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37739879 # Type of FU issued -system.cpu0.iq.rate 0.570847 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1068307 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028307 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 120546534 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44606042 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34820056 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8333 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4740 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38783456 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4323 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 326383 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 38247071 # Type of FU issued +system.cpu0.iq.rate 0.576409 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1069549 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.027964 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 121902835 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 45721169 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 35306324 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8427 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4840 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3930 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 39259896 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4380 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 325721 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1507630 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4080 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13930 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 608245 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1504145 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3982 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13879 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 608088 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149509 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5404 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149487 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5263 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1056312 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4064319 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 129740 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38471177 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 88757 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7928571 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5881726 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 461616 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 49674 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 17745 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13930 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 159357 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 144737 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 304094 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37337331 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9402148 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 402548 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1085770 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4069341 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 129560 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 39094255 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 87678 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7927385 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5883720 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 614122 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 49261 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 17662 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13879 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 160370 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 144551 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 304921 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37828601 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9401576 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 418470 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 138361 # number of nop insts executed -system.cpu0.iew.exec_refs 14958639 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4921687 # Number of branches executed -system.cpu0.iew.exec_stores 5556491 # Number of stores executed -system.cpu0.iew.exec_rate 0.564758 # Inst execution rate -system.cpu0.iew.wb_sent 37117116 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34823949 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18360594 # num instructions producing a value -system.cpu0.iew.wb_consumers 34980725 # num instructions consuming a value +system.cpu0.iew.exec_nop 138219 # number of nop insts executed +system.cpu0.iew.exec_refs 14960222 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5069889 # Number of branches executed +system.cpu0.iew.exec_stores 5558646 # Number of stores executed +system.cpu0.iew.exec_rate 0.570102 # Inst execution rate +system.cpu0.iew.wb_sent 37608832 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 35310254 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18670977 # num instructions producing a value +system.cpu0.iew.wb_consumers 35573590 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.526741 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.524877 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.532149 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.524855 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 24134633 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 31866160 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 6466683 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 656866 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 267750 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 42850944 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.743651 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.697776 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 24262280 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 31997725 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6679991 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 688836 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 267429 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 43160582 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.741365 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.695624 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 30739496 71.74% 71.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6075340 14.18% 85.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1944692 4.54% 90.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1041937 2.43% 92.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 773699 1.81% 94.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 503770 1.18% 95.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 405337 0.95% 96.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 203427 0.47% 97.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1163246 2.71% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 31020137 71.87% 71.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6071618 14.07% 85.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1950463 4.52% 90.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1036843 2.40% 92.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 799662 1.85% 94.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 507487 1.18% 95.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 407135 0.94% 96.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 202137 0.47% 97.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1165100 2.70% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 42850944 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24134633 # Number of instructions committed -system.cpu0.commit.committedOps 31866160 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 43160582 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24262280 # Number of instructions committed +system.cpu0.commit.committedOps 31997725 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11694422 # Number of memory references committed -system.cpu0.commit.loads 6420941 # Number of loads committed -system.cpu0.commit.membars 234529 # Number of memory barriers committed -system.cpu0.commit.branches 4382702 # Number of branches committed +system.cpu0.commit.refs 11698872 # Number of memory references committed +system.cpu0.commit.loads 6423240 # Number of loads committed +system.cpu0.commit.membars 234547 # Number of memory barriers committed +system.cpu0.commit.branches 4415502 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28193395 # Number of committed integer instructions. -system.cpu0.commit.function_calls 499856 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1163246 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28265931 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499946 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1165100 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 79207972 # The number of ROB reads -system.cpu0.rob.rob_writes 77724528 # The number of ROB writes -system.cpu0.timesIdled 427936 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 22241224 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5096899290 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24053891 # Number of Instructions Simulated -system.cpu0.committedOps 31785418 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24053891 # Number of Instructions Simulated -system.cpu0.cpi 2.748499 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.748499 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.363835 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.363835 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 174526329 # number of integer regfile reads -system.cpu0.int_regfile_writes 34331240 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3280 # number of floating regfile reads -system.cpu0.fp_regfile_writes 898 # number of floating regfile writes -system.cpu0.misc_regfile_reads 46875879 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527497 # number of misc regfile writes -system.cpu0.icache.replacements 406974 # number of replacements -system.cpu0.icache.tagsinuse 511.614338 # Cycle average of tags in use -system.cpu0.icache.total_refs 3978434 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 407486 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.763364 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6469268000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.614338 # Average occupied blocks per requestor +system.cpu0.rob.rob_reads 79788976 # The number of ROB reads +system.cpu0.rob.rob_writes 78443760 # The number of ROB writes +system.cpu0.timesIdled 426851 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 22144095 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5098222727 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 24181538 # Number of Instructions Simulated +system.cpu0.committedOps 31916983 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 24181538 # Number of Instructions Simulated +system.cpu0.cpi 2.743996 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.743996 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.364432 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.364432 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 176533858 # number of integer regfile reads +system.cpu0.int_regfile_writes 35079827 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3404 # number of floating regfile reads +system.cpu0.fp_regfile_writes 942 # number of floating regfile writes +system.cpu0.misc_regfile_reads 47584444 # number of misc regfile reads +system.cpu0.misc_regfile_writes 527516 # number of misc regfile writes +system.cpu0.icache.replacements 406873 # number of replacements +system.cpu0.icache.tagsinuse 511.614484 # Cycle average of tags in use +system.cpu0.icache.total_refs 3975135 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 407385 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.757686 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6470209000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.614484 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.999247 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.999247 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3978434 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3978434 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3978434 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3978434 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3978434 # number of overall hits -system.cpu0.icache.overall_hits::total 3978434 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 441298 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 441298 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 441298 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 441298 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 441298 # number of overall misses -system.cpu0.icache.overall_misses::total 441298 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7186656997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7186656997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7186656997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7186656997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7186656997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7186656997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4419732 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4419732 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4419732 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4419732 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4419732 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4419732 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099847 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.099847 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099847 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.099847 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099847 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.099847 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16285.269811 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16285.269811 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16285.269811 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16285.269811 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16285.269811 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16285.269811 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1454497 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 3975135 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3975135 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3975135 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3975135 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3975135 # number of overall hits +system.cpu0.icache.overall_hits::total 3975135 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 441500 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 441500 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 441500 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 441500 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 441500 # number of overall misses +system.cpu0.icache.overall_misses::total 441500 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7129067996 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7129067996 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7129067996 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7129067996 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7129067996 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7129067996 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4416635 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4416635 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4416635 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4416635 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4416635 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4416635 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099963 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.099963 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099963 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.099963 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099963 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.099963 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16147.379379 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16147.379379 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16147.379379 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16147.379379 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16147.379379 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16147.379379 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1348496 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 171 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 167 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8505.830409 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 8074.826347 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 29234 # number of writebacks -system.cpu0.icache.writebacks::total 29234 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33802 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 33802 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 33802 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 33802 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 33802 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 33802 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407496 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 407496 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 407496 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 407496 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 407496 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 407496 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5527499503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5527499503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5527499503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5527499503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5527499503 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5527499503 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 34106 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 34106 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 34106 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 34106 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 34106 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 34106 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407394 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 407394 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 407394 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 407394 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 407394 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 407394 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5468654996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5468654996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5468654996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5468654996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5468654996 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5468654996 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8379000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8379000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8379000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 8379000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092199 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.092199 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.092199 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13564.549107 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13564.549107 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13564.549107 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092241 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092241 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092241 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.092241 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092241 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.092241 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13423.504018 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13423.504018 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13423.504018 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13423.504018 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13423.504018 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13423.504018 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275761 # number of replacements -system.cpu0.dcache.tagsinuse 476.305820 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9551525 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276273 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.572778 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 275592 # number of replacements +system.cpu0.dcache.tagsinuse 476.837382 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9554493 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276104 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.604689 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 51448000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 476.305820 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.930285 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.930285 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5934693 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5934693 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3224707 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3224707 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174478 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174478 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171499 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171499 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9159400 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9159400 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9159400 # number of overall hits -system.cpu0.dcache.overall_hits::total 9159400 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 401255 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 401255 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1594245 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1594245 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9007 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9007 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7794 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7794 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1995500 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1995500 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1995500 # number of overall misses -system.cpu0.dcache.overall_misses::total 1995500 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7289566500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 7289566500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71816395371 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 71816395371 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 114642500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 114642500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 93715000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 93715000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 79105961871 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 79105961871 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 79105961871 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 79105961871 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6335948 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6335948 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4818952 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4818952 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183485 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183485 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179293 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 179293 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11154900 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11154900 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11154900 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11154900 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063330 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063330 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330828 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.330828 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049088 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.049088 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043471 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043471 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178890 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.178890 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178890 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.178890 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18166.917546 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 18166.917546 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45047.276530 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45047.276530 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12728.155879 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12728.155879 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12023.992815 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12023.992815 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39642.175831 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39642.175831 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39642.175831 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39642.175831 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7140493 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1629000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1441 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 89 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4955.234559 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 18303.370787 # average number of cycles each access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 476.837382 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.931323 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.931323 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5935954 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5935954 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3226635 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3226635 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174405 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174405 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171548 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171548 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9162589 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9162589 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9162589 # number of overall hits +system.cpu0.dcache.overall_hits::total 9162589 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 400527 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 400527 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1594104 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1594104 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8985 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8985 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7776 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7776 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1994631 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1994631 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1994631 # number of overall misses +system.cpu0.dcache.overall_misses::total 1994631 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7261400500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 7261400500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71837415855 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 71837415855 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 113971500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 113971500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 93410500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 93410500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 79098816355 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 79098816355 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 79098816355 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 79098816355 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6336481 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6336481 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4820739 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4820739 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183390 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183390 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179324 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 179324 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11157220 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11157220 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11157220 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11157220 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063210 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063210 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330676 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.330676 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048994 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048994 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043363 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043363 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178775 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178775 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18129.615482 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 18129.615482 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45064.447398 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45064.447398 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12684.641068 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12684.641068 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12012.667181 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12012.667181 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39655.864345 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39655.864345 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39655.864345 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39655.864345 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 7527492 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1548500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1462 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 87 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 5148.763338 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 17798.850575 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255942 # number of writebacks -system.cpu0.dcache.writebacks::total 255942 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211815 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 211815 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463184 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1463184 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 509 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 509 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1674999 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1674999 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1674999 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1674999 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189440 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189440 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131061 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131061 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8498 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8498 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7791 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7791 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320501 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320501 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320501 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320501 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2806583905 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2806583905 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4685193022 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4685193022 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 80265007 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 80265007 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 69214057 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 69214057 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7491776927 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7491776927 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7491776927 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7491776927 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10315161000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10315161000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 849550399 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 849550399 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11164711399 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11164711399 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029899 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029899 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027197 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027197 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046314 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046314 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043454 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043454 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028732 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028732 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028732 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028732 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14815.159971 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14815.159971 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35748.186127 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35748.186127 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9445.164392 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9445.164392 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8883.847645 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8883.847645 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23375.206090 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23375.206090 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23375.206090 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23375.206090 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255542 # number of writebacks +system.cpu0.dcache.writebacks::total 255542 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211236 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 211236 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463026 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1463026 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 516 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 516 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1674262 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1674262 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1674262 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1674262 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189291 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189291 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131078 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131078 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8469 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8469 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7773 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7773 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320369 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320369 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 320369 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320369 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2800937917 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2800937917 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4685815512 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4685815512 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79569505 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79569505 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 68924555 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 68924555 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7486753429 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7486753429 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7486753429 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7486753429 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10315126500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10315126500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 849486399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 849486399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11164612899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11164612899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029873 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029873 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027190 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027190 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046180 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046180 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043346 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043346 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028714 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028714 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028714 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028714 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14796.994664 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14796.994664 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35748.298814 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35748.298814 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9395.383753 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9395.383753 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8867.175479 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8867.175479 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23369.156907 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23369.156907 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23369.156907 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23369.156907 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1083,27 +1083,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43446349 # DTB read hits -system.cpu1.dtb.read_misses 46684 # DTB read misses -system.cpu1.dtb.write_hits 7088138 # DTB write hits -system.cpu1.dtb.write_misses 12274 # DTB write misses +system.cpu1.dtb.read_hits 43445270 # DTB read hits +system.cpu1.dtb.read_misses 46285 # DTB read misses +system.cpu1.dtb.write_hits 7088572 # DTB write hits +system.cpu1.dtb.write_misses 12217 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2545 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3731 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 361 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2504 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3688 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 371 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 673 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43493033 # DTB read accesses -system.cpu1.dtb.write_accesses 7100412 # DTB write accesses +system.cpu1.dtb.perms_faults 674 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43491555 # DTB read accesses +system.cpu1.dtb.write_accesses 7100789 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50534487 # DTB hits -system.cpu1.dtb.misses 58958 # DTB misses -system.cpu1.dtb.accesses 50593445 # DTB accesses -system.cpu1.itb.inst_hits 9221438 # ITB inst hits -system.cpu1.itb.inst_misses 6034 # ITB inst misses +system.cpu1.dtb.hits 50533842 # DTB hits +system.cpu1.dtb.misses 58502 # DTB misses +system.cpu1.dtb.accesses 50592344 # DTB accesses +system.cpu1.itb.inst_hits 9223213 # ITB inst hits +system.cpu1.itb.inst_misses 6180 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1112,121 +1112,121 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1610 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1615 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1730 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1780 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 9227472 # ITB inst accesses -system.cpu1.itb.hits 9221438 # DTB hits -system.cpu1.itb.misses 6034 # DTB misses -system.cpu1.itb.accesses 9227472 # DTB accesses -system.cpu1.numCycles 353824423 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 9229393 # ITB inst accesses +system.cpu1.itb.hits 9223213 # DTB hits +system.cpu1.itb.misses 6180 # DTB misses +system.cpu1.itb.accesses 9229393 # DTB accesses +system.cpu1.numCycles 355232424 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9470897 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7703385 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 447489 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6420671 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5281203 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9848764 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 8083275 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 447123 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6868345 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5662939 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 834152 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 50449 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 22167103 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 70445168 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9470897 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6115355 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14956565 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4597208 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 88094 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 73687570 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 6011 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 61739 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 141755 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 9219303 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 857673 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3541 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114241434 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.747913 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.114106 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 832004 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 49676 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 22148379 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 71952458 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9848764 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6494943 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 15333431 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4632908 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 88364 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 74838070 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5775 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 63991 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 141562 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 138 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 9221022 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 859641 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3677 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 115781579 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.750934 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.109459 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 99293168 86.92% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 828706 0.73% 87.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1015866 0.89% 88.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2054648 1.80% 90.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1280264 1.12% 91.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 613123 0.54% 91.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2273093 1.99% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 467514 0.41% 94.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6415052 5.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100456410 86.76% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 829573 0.72% 87.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1015846 0.88% 88.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2061622 1.78% 90.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1645380 1.42% 91.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 616095 0.53% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2274849 1.96% 94.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 467300 0.40% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6414504 5.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114241434 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.026767 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.199096 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 23740446 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 73499308 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13432186 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 537783 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3031711 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1242419 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102480 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 79700896 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 342426 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3031711 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 25267828 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33699109 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 35312301 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12394168 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4536317 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 73261010 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3244 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 714923 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3281779 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33706 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 77426546 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 339504965 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 339445449 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59516 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49265102 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 28161444 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 486276 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 420659 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8155263 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 14019935 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8605996 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1069297 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1521896 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 66318588 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 855610 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 90596015 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 108958 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18341957 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53651445 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 163223 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114241434 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.793022 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.525613 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 115781579 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.027725 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.202550 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 23776389 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 74601447 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13781615 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 561009 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3061119 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1241407 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 102665 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 81190791 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 341149 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3061119 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 25333003 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33967991 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 36116187 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12703540 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4599739 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 74711209 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 20422 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 719883 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3284162 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 33659 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 79078972 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 344223554 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 344164086 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59468 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50180386 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 28898586 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 486916 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 421354 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8389500 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 14026564 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8607423 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1068694 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1518812 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 67421543 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1209489 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 91958955 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 109721 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18898752 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 53543776 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 290002 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 115781579 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.794245 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521941 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83094748 72.74% 72.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8828314 7.73% 80.46% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4518450 3.96% 84.42% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3737052 3.27% 87.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10664138 9.33% 97.02% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1972512 1.73% 98.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1063413 0.93% 99.68% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 282401 0.25% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 80406 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83973534 72.53% 72.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 9124499 7.88% 80.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4576997 3.95% 84.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4009566 3.46% 87.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10699106 9.24% 97.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1974757 1.71% 98.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1060771 0.92% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 281863 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 80486 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114241434 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 115781579 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29108 0.37% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29310 0.37% 0.37% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 993 0.01% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available @@ -1255,403 +1255,397 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7574349 95.84% 96.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 298565 3.78% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7573445 95.84% 96.23% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 298199 3.77% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 86745 0.10% 0.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 38337785 42.32% 42.41% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61539 0.07% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 4 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1698 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44639306 49.27% 91.76% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7468915 8.24% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 39470238 42.92% 43.26% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61477 0.07% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1690 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 44643108 48.55% 91.88% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7468676 8.12% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 90596015 # Type of FU issued -system.cpu1.iq.rate 0.256048 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7903015 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.087234 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 303489486 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 85529327 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54443530 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14763 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8091 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6830 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 98404572 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7713 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 368848 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 91958955 # Type of FU issued +system.cpu1.iq.rate 0.258870 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7901947 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.085929 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 307754751 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 87542996 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 55769663 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14772 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8137 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6817 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 99539441 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7724 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 371642 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4030694 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6909 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 21919 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1587988 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4037130 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6814 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 21954 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1589436 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965710 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1045299 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965709 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1043610 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3031711 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25598263 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 405605 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 67299344 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 135063 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 14019935 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8605996 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 545729 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 81019 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 7196 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 21919 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 232087 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 197105 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 429192 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87765278 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43831578 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2830737 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3061119 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25601852 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 406330 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 68756671 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 131432 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 14026564 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8607423 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 899609 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 81519 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 7124 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 21954 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 226065 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 196785 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 422850 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 89098857 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43830249 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2860098 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 125146 # number of nop insts executed -system.cpu1.iew.exec_refs 51224987 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7024509 # Number of branches executed -system.cpu1.iew.exec_stores 7393409 # Number of stores executed -system.cpu1.iew.exec_rate 0.248048 # Inst execution rate -system.cpu1.iew.wb_sent 86598496 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54450360 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30044182 # num instructions producing a value -system.cpu1.iew.wb_consumers 53342809 # num instructions consuming a value +system.cpu1.iew.exec_nop 125639 # number of nop insts executed +system.cpu1.iew.exec_refs 51224079 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7396455 # Number of branches executed +system.cpu1.iew.exec_stores 7393830 # Number of stores executed +system.cpu1.iew.exec_rate 0.250818 # Inst execution rate +system.cpu1.iew.wb_sent 87931251 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 55776480 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30792122 # num instructions producing a value +system.cpu1.iew.wb_consumers 54566321 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.153891 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.563228 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.157014 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.564306 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 38036954 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 48396972 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 18817114 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 692387 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 376510 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111258144 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.434997 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.402953 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 38938347 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 49298719 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 19014978 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 919487 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 376070 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 112768879 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.437166 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.403258 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94210177 84.68% 84.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8524716 7.66% 92.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2208233 1.98% 94.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1307974 1.18% 95.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1064973 0.96% 96.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 589982 0.53% 96.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1003368 0.90% 97.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 487910 0.44% 98.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1860811 1.67% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 95484340 84.67% 84.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8537208 7.57% 92.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2210726 1.96% 94.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1312266 1.16% 95.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1283048 1.14% 96.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 588048 0.52% 97.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1003635 0.89% 97.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 487845 0.43% 98.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1861763 1.65% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111258144 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38036954 # Number of instructions committed -system.cpu1.commit.committedOps 48396972 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 112768879 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38938347 # Number of instructions committed +system.cpu1.commit.committedOps 49298719 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17007249 # Number of memory references committed -system.cpu1.commit.loads 9989241 # Number of loads committed -system.cpu1.commit.membars 202226 # Number of memory barriers committed -system.cpu1.commit.branches 5993368 # Number of branches committed +system.cpu1.commit.refs 17007421 # Number of memory references committed +system.cpu1.commit.loads 9989434 # Number of loads committed +system.cpu1.commit.membars 202281 # Number of memory barriers committed +system.cpu1.commit.branches 6220621 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43235909 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556157 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1860811 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 43690243 # Number of committed integer instructions. +system.cpu1.commit.function_calls 556165 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1861763 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 175585773 # The number of ROB reads -system.cpu1.rob.rob_writes 137553768 # The number of ROB writes -system.cpu1.timesIdled 1520299 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 239582989 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4808538839 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37967315 # Number of Instructions Simulated -system.cpu1.committedOps 48327333 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37967315 # Number of Instructions Simulated -system.cpu1.cpi 9.319185 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 9.319185 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.107306 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.107306 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 393921761 # number of integer regfile reads -system.cpu1.int_regfile_writes 56840694 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4925 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2334 # number of floating regfile writes -system.cpu1.misc_regfile_reads 90313719 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429414 # number of misc regfile writes -system.cpu1.icache.replacements 622931 # number of replacements -system.cpu1.icache.tagsinuse 498.760560 # Cycle average of tags in use -system.cpu1.icache.total_refs 8545880 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 623443 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.707556 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74633827000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.760560 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974142 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974142 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 8545880 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8545880 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8545880 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8545880 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8545880 # number of overall hits -system.cpu1.icache.overall_hits::total 8545880 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 673372 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 673372 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 673372 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 673372 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 673372 # number of overall misses -system.cpu1.icache.overall_misses::total 673372 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10716931993 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10716931993 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10716931993 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10716931993 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10716931993 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10716931993 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 9219252 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 9219252 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 9219252 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 9219252 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 9219252 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 9219252 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073040 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.073040 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073040 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.073040 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073040 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.073040 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15915.321684 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15915.321684 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15915.321684 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15915.321684 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15915.321684 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15915.321684 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1332494 # number of cycles access was blocked +system.cpu1.rob.rob_reads 178106600 # The number of ROB reads +system.cpu1.rob.rob_writes 139781050 # The number of ROB writes +system.cpu1.timesIdled 1519184 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 239450845 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4808685831 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38868708 # Number of Instructions Simulated +system.cpu1.committedOps 49229080 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38868708 # Number of Instructions Simulated +system.cpu1.cpi 9.139291 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 9.139291 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.109418 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.109418 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 398713179 # number of integer regfile reads +system.cpu1.int_regfile_writes 58485097 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4918 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2338 # number of floating regfile writes +system.cpu1.misc_regfile_reads 91819776 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429481 # number of misc regfile writes +system.cpu1.icache.replacements 621812 # number of replacements +system.cpu1.icache.tagsinuse 498.762593 # Cycle average of tags in use +system.cpu1.icache.total_refs 8548797 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 622324 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.736891 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74633258000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.762593 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974146 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974146 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 8548797 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8548797 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 8548797 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 8548797 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 8548797 # number of overall hits +system.cpu1.icache.overall_hits::total 8548797 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 672174 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 672174 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 672174 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 672174 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 672174 # number of overall misses +system.cpu1.icache.overall_misses::total 672174 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10613540997 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10613540997 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 10613540997 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10613540997 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 10613540997 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10613540997 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 9220971 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 9220971 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 9220971 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 9220971 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 9220971 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 9220971 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.072896 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.072896 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.072896 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.072896 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.072896 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.072896 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15789.871368 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15789.871368 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15789.871368 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15789.871368 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15789.871368 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15789.871368 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1180997 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 205 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 198 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6499.970732 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 5964.631313 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 33068 # number of writebacks -system.cpu1.icache.writebacks::total 33068 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49906 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 49906 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 49906 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 49906 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 49906 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 49906 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 623466 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 623466 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 623466 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 623466 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 623466 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 623466 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8227032008 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8227032008 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8227032008 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8227032008 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8227032008 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8227032008 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49820 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 49820 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 49820 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 49820 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 49820 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 49820 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622354 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 622354 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 622354 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 622354 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 622354 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 622354 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8128418498 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8128418498 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8128418498 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8128418498 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8128418498 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8128418498 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3154000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3154000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3154000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3154000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067627 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.067627 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.067627 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13195.638588 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13195.638588 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13195.638588 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067493 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067493 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067493 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.067493 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067493 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.067493 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13060.763646 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13060.763646 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13060.763646 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13060.763646 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13060.763646 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13060.763646 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 362729 # number of replacements -system.cpu1.dcache.tagsinuse 487.126779 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13112337 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 363073 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.114878 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70483759000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.126779 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951419 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951419 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8613908 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8613908 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4252702 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4252702 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105106 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 105106 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100709 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 100709 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12866610 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12866610 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12866610 # number of overall hits -system.cpu1.dcache.overall_hits::total 12866610 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 410185 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 410185 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1595357 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1595357 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14278 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14278 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10900 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10900 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 2005542 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 2005542 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 2005542 # number of overall misses -system.cpu1.dcache.overall_misses::total 2005542 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8114216000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 8114216000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66620735237 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 66620735237 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166584000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 166584000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 94819000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 94819000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 74734951237 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 74734951237 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 74734951237 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 74734951237 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9024093 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9024093 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5848059 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5848059 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 119384 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 119384 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111609 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 111609 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14872152 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14872152 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14872152 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14872152 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045454 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045454 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272801 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.272801 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119597 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119597 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097662 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097662 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134852 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.134852 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134852 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.134852 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19781.844777 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19781.844777 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41759.139326 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41759.139326 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11667.180277 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11667.180277 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8698.990826 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8698.990826 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 37264.216475 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 37264.216475 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 37264.216475 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 37264.216475 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29196505 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5606000 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6645 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 174 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4393.755455 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 32218.390805 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 362958 # number of replacements +system.cpu1.dcache.tagsinuse 487.094495 # Cycle average of tags in use +system.cpu1.dcache.total_refs 13107479 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 363304 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 36.078543 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70482639000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 487.094495 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.951356 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.951356 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8608268 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8608268 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4252418 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4252418 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 106100 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 106100 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100714 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 100714 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12860686 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12860686 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12860686 # number of overall hits +system.cpu1.dcache.overall_hits::total 12860686 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 410615 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 410615 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1595619 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1595619 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14222 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14222 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10905 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10905 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 2006234 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 2006234 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 2006234 # number of overall misses +system.cpu1.dcache.overall_misses::total 2006234 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8133768000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8133768000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66485489237 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 66485489237 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 165213500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 165213500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 94467000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 94467000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 74619257237 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 74619257237 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 74619257237 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 74619257237 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9018883 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9018883 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5848037 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5848037 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 120322 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 120322 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111619 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 111619 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14866920 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14866920 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14866920 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14866920 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045528 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045528 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272847 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.272847 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118199 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118199 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097698 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097698 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134946 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.134946 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134946 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.134946 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19808.745418 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19808.745418 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41667.521656 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41667.521656 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11616.755731 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11616.755731 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8662.723521 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8662.723521 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 37193.695868 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 37193.695868 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 37193.695868 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 37193.695868 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 29476015 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5620000 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6671 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 172 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4418.530205 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 32674.418605 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 327467 # number of writebacks -system.cpu1.dcache.writebacks::total 327467 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 179191 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 179191 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432552 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1432552 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1457 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1457 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1611743 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1611743 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1611743 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1611743 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 230994 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 230994 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162805 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 162805 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12821 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12821 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10892 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10892 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 393799 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 393799 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 393799 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 393799 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3545762451 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3545762451 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5565749199 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5565749199 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104395505 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104395505 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60832506 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60832506 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9111511650 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9111511650 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9111511650 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9111511650 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137004750500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137004750500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40571899654 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40571899654 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 177576650154 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 177576650154 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025597 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027839 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027839 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107393 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107393 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097591 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097591 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026479 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026479 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026479 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026479 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15350.019702 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15350.019702 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34186.598686 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34186.598686 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8142.539973 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8142.539973 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5585.062982 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5585.062982 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23137.467718 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23137.467718 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23137.467718 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23137.467718 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327729 # number of writebacks +system.cpu1.dcache.writebacks::total 327729 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 179332 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 179332 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432824 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1432824 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1612156 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1612156 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1612156 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1612156 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231283 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231283 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162795 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 162795 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12775 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12775 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394078 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394078 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394078 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394078 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3556387454 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3556387454 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5557887685 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5557887685 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 103446504 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 103446504 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60421505 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60421505 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9114275139 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9114275139 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9114275139 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9114275139 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137004022500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137004022500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40580989302 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40580989302 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 177585011802 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 177585011802 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025644 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025644 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027838 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027838 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106173 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106173 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097654 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097654 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026507 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026507 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15376.778466 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15376.778466 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34140.407783 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34140.407783 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8097.573699 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8097.573699 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5543.257339 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5543.257339 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23128.099359 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23128.099359 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23128.099359 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23128.099359 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1673,18 +1667,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305278151135 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1305278151135 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305278151135 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1305278151135 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305599683923 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1305599683923 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305599683923 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1305599683923 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43785 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43782 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53912 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 53899 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 71f536288..9e6ff3218 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -581,7 +581,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 34717b2ec..c9f3d2864 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 17:04:56 +gem5 compiled Jul 26 2012 21:40:00 +gem5 started Jul 27 2012 02:23:14 gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2502549875500 because m5_exit instruction encountered +Exiting @ tick 2503329223500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 6df4de0df..b903804f3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.502550 # Number of seconds simulated -sim_ticks 2502549875500 # Number of ticks simulated -final_tick 2502549875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.503329 # Number of seconds simulated +sim_ticks 2503329223500 # Number of ticks simulated +final_tick 2503329223500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90191 # Simulator instruction rate (inst/s) -host_op_rate 116452 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3788406278 # Simulator tick rate (ticks/s) -host_mem_usage 386884 # Number of bytes of host memory used -host_seconds 660.58 # Real time elapsed on the host -sim_insts 59578267 # Number of instructions simulated -sim_ops 76925839 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 118994504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3776 # Number of bytes read from this memory +host_inst_rate 62297 # Simulator instruction rate (inst/s) +host_op_rate 80132 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2573650165 # Simulator tick rate (ticks/s) +host_mem_usage 394796 # Number of bytes of host memory used +host_seconds 972.68 # Real time elapsed on the host +sim_insts 60594713 # Number of instructions simulated +sim_ops 77942287 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3712 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 800128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory -system.physmem.bytes_read::total 128893400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 800128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 800128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 799552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094032 # Number of bytes read from this memory +system.physmem.bytes_read::total 129435024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6802248 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14874313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 59 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 58 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12502 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15029017 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12493 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096888 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813177 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47549304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1509 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47751475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1483 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 319725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3634264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51504828 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 319725 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 319725 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1512927 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1205200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2718127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1512927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47549304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 319395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3632775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51705154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 319395 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 319395 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1512073 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1204824 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2716897 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1512073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47751475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1483 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 319725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4839464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54222954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 319395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4837599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54422052 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,149 +61,149 @@ system.realview.nvmem.bw_inst_read::cpu.inst 26 system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64431 # number of replacements -system.l2c.tagsinuse 51237.782352 # Cycle average of tags in use -system.l2c.total_refs 2028510 # Total number of references to valid blocks. -system.l2c.sampled_refs 129827 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.624716 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2492014554000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36760.884600 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 47.476285 # Average occupied blocks per requestor +system.l2c.replacements 64407 # number of replacements +system.l2c.tagsinuse 51237.721374 # Cycle average of tags in use +system.l2c.total_refs 1963815 # Total number of references to valid blocks. +system.l2c.sampled_refs 129804 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.129079 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2492699118000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36773.515896 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 46.128401 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.itb.walker 0.000184 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8187.042847 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6242.378435 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.560927 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000724 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu.inst 8177.854263 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6240.222629 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.561119 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000704 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124924 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.095251 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.781827 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 121963 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11826 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 977935 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 383708 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1495432 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 675442 # number of Writeback hits -system.l2c.Writeback_hits::total 675442 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.l2c.occ_percent::cpu.inst 0.124784 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.095218 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.781826 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 123734 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11927 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 976636 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 387128 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1499425 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 607519 # number of Writeback hits +system.l2c.Writeback_hits::total 607519 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 41 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112737 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112737 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 121963 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11826 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 977935 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 496445 # number of demand (read+write) hits -system.l2c.demand_hits::total 1608169 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 121963 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11826 # number of overall hits -system.l2c.overall_hits::cpu.inst 977935 # number of overall hits -system.l2c.overall_hits::cpu.data 496445 # number of overall hits -system.l2c.overall_hits::total 1608169 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 59 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu.data 112732 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112732 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 123734 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11927 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 976636 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 499860 # number of demand (read+write) hits +system.l2c.demand_hits::total 1612157 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 123734 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11927 # number of overall hits +system.l2c.overall_hits::cpu.inst 976636 # number of overall hits +system.l2c.overall_hits::cpu.data 499860 # number of overall hits +system.l2c.overall_hits::total 1612157 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 58 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12384 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 12374 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23135 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23124 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2909 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133229 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133229 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 59 # number of demand (read+write) misses +system.l2c.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 133219 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133219 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 58 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12384 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143920 # number of demand (read+write) misses -system.l2c.demand_misses::total 156364 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 59 # number of overall misses +system.l2c.demand_misses::cpu.inst 12374 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 143910 # number of demand (read+write) misses +system.l2c.demand_misses::total 156343 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 58 # number of overall misses system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu.inst 12384 # number of overall misses -system.l2c.overall_misses::cpu.data 143920 # number of overall misses -system.l2c.overall_misses::total 156364 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3091500 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu.inst 12374 # number of overall misses +system.l2c.overall_misses::cpu.data 143910 # number of overall misses +system.l2c.overall_misses::total 156343 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3035000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 659591498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 562236498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1224979496 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 944500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 944500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7069904999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7069904999 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 3091500 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 659327498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 562370998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1224793496 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 994500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 994500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7086596499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7086596499 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 3035000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 659591498 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7632141497 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8294884495 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 3091500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu.inst 659327498 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7648967497 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8311389995 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 3035000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 659591498 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 7632141497 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8294884495 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 122022 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 11827 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 990319 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 394399 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1518567 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 675442 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 675442 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2951 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2951 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 245966 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 245966 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 122022 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 11827 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 990319 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 640365 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1764533 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 122022 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 11827 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 990319 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 640365 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1764533 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000484 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.012505 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.027107 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015235 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.985768 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.985768 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.157895 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.157895 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.541656 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541656 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000484 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.012505 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.224747 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.088615 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000484 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.012505 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.224747 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.088615 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52398.305085 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu.inst 659327498 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 7648967497 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8311389995 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 123792 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 11928 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 989010 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 397819 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1522549 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 607519 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 607519 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2950 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2950 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 18 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 18 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 245951 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 245951 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 123792 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 11928 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 989010 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 643770 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1768500 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 123792 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 11928 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 989010 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 643770 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1768500 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000469 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000084 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.012512 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.026874 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015188 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.986102 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.986102 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.111111 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.111111 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.541649 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541649 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000469 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000084 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.012512 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.223543 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.088404 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000469 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000084 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.012512 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.223543 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.088404 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52327.586207 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 53261.587371 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52589.701431 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52949.189367 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 324.682021 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 324.682021 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 53065.811490 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53065.811490 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 53283.295458 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52602.282106 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52966.333506 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 341.870058 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 341.870058 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 53195.088531 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53195.088531 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52327.586207 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 53048.556541 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 53283.295458 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 53151.049246 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53161.254389 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52327.586207 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 53048.556541 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 53283.295458 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 53151.049246 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53161.254389 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,109 +212,109 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59159 # number of writebacks -system.l2c.writebacks::total 59159 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.inst 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 71 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 59 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 59144 # number of writebacks +system.l2c.writebacks::total 59144 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 69 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 58 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 12375 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 10629 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23064 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 12366 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 10630 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23055 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 133229 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133229 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 59 # number of demand (read+write) MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 133219 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133219 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 58 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 12375 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 143858 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156293 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 59 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 12366 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 143849 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156274 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 58 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 12375 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 143858 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156293 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2372000 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu.inst 12366 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 143849 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156274 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2326000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 508160500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 430170499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 940750999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116825000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 116825000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5436034999 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5436034999 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2372000 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 507997999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 430294500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 940666499 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 117136000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 117136000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5457467999 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5457467999 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2326000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 508160500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 5866205498 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6376785998 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2372000 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 507997999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 5887762499 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6398134498 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2326000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 508160500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 5866205498 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6376785998 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 507997999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5887762499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6398134498 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5323000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131417115000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131422438000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31373446015 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 31373446015 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131412946500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131418269500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31416947511 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31416947511 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5323000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 162790561015 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 162795884015 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026950 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015188 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985768 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.985768 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541656 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541656 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088575 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088575 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu.data 162829894011 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 162835217011 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000469 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012503 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026721 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015142 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986102 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.986102 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.111111 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.111111 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541649 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541649 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000469 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012503 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.223448 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088365 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000469 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012503 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.223448 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088365 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41063.474747 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40471.398909 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40788.718306 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40159.848745 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40159.848745 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41080.219877 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40479.256820 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40800.975884 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.758336 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.758336 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40802.190206 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40802.190206 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40966.138456 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40966.138456 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41080.219877 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40930.159396 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40941.772131 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41080.219877 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40930.159396 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40941.772131 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -332,27 +332,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51771660 # DTB read hits -system.cpu.dtb.read_misses 81258 # DTB read misses -system.cpu.dtb.write_hits 11880398 # DTB write hits -system.cpu.dtb.write_misses 17961 # DTB write misses +system.cpu.dtb.read_hits 51771178 # DTB read hits +system.cpu.dtb.read_misses 82022 # DTB read misses +system.cpu.dtb.write_hits 11879780 # DTB write hits +system.cpu.dtb.write_misses 18404 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4471 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3044 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 609 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4476 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2874 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 631 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1282 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51852918 # DTB read accesses -system.cpu.dtb.write_accesses 11898359 # DTB write accesses +system.cpu.dtb.perms_faults 1260 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51853200 # DTB read accesses +system.cpu.dtb.write_accesses 11898184 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63652058 # DTB hits -system.cpu.dtb.misses 99219 # DTB misses -system.cpu.dtb.accesses 63751277 # DTB accesses -system.cpu.itb.inst_hits 13142261 # ITB inst hits -system.cpu.itb.inst_misses 12247 # ITB inst misses +system.cpu.dtb.hits 63650958 # DTB hits +system.cpu.dtb.misses 100426 # DTB misses +system.cpu.dtb.accesses 63751384 # DTB accesses +system.cpu.itb.inst_hits 13147400 # ITB inst hits +system.cpu.itb.inst_misses 12275 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -361,122 +361,122 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2634 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2641 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3416 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13154508 # ITB inst accesses -system.cpu.itb.hits 13142261 # DTB hits -system.cpu.itb.misses 12247 # DTB misses -system.cpu.itb.accesses 13154508 # DTB accesses -system.cpu.numCycles 413642740 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13159675 # ITB inst accesses +system.cpu.itb.hits 13147400 # DTB hits +system.cpu.itb.misses 12275 # DTB misses +system.cpu.itb.accesses 13159675 # DTB accesses +system.cpu.numCycles 415310668 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14974990 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11915620 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 753400 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10068197 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7820088 # Number of BTB hits +system.cpu.BPredUnit.lookups 15527738 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12466555 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 753811 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10646284 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8367014 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1448775 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 80927 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33422471 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 99542070 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14974990 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9268863 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21759182 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6002262 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 163536 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 93319816 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133610 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208459 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 397 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13138017 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1024097 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6504 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 153128307 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.804842 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.182667 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1449693 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80905 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33357472 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 101736318 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15527738 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9816707 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22310929 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6078281 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 161634 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 94635812 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2484 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 132549 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208778 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 375 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13143214 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1025665 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6564 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 154991090 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.809239 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.178893 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131386008 85.80% 85.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1369017 0.89% 86.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1759019 1.15% 87.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2640315 1.72% 89.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1819667 1.19% 90.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1142419 0.75% 91.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2920911 1.91% 93.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 807762 0.53% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9283189 6.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 132697054 85.62% 85.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1371702 0.89% 86.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1758298 1.13% 87.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2653739 1.71% 89.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2357523 1.52% 90.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1143564 0.74% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2918516 1.88% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 809258 0.52% 94.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9281436 5.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 153128307 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.036203 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.240647 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35537493 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 93048586 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19509299 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1086349 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3946580 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2100058 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174557 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116122172 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568338 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3946580 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37621271 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39594801 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46881047 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18412397 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6672211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 108597287 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4175 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1156489 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4484156 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 30967 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 113073752 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 499820515 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 499727174 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 93341 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77686691 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35387060 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898607 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797702 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13307124 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21058263 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13875749 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1965166 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2564814 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 99781831 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1555350 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124613166 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 199798 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23638127 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65777806 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 268083 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 153128307 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.813783 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.516400 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 154991090 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.037388 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.244964 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35540110 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94304374 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20024957 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1112327 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4009322 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2100739 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174603 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118268322 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 570412 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4009322 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37657945 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39869078 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47822984 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18880557 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6751204 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110681454 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22988 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1160036 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4497834 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 31020 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115504222 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 506609726 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 506516210 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 93516 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78727449 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36776772 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 900485 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 799637 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13564830 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21065339 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13879000 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1961867 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2663971 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101316574 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2057711 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126458108 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 199553 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24657438 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65563204 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 513311 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154991090 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.815906 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.514046 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107849903 70.43% 70.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14560254 9.51% 79.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7302452 4.77% 84.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5913038 3.86% 88.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12593494 8.22% 96.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2809204 1.83% 98.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1536315 1.00% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 438168 0.29% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125479 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108868078 70.24% 70.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14887887 9.61% 79.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7383585 4.76% 84.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6313472 4.07% 88.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12622401 8.14% 96.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2812506 1.81% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1537255 0.99% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 440277 0.28% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125629 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 153128307 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154991090 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53462 0.61% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 54148 0.61% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available @@ -504,399 +504,397 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8367005 94.75% 95.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 409700 4.64% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8364176 94.75% 95.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 409089 4.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 106530 0.09% 0.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58482659 46.93% 47.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95330 0.08% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 11 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53414157 42.86% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12512351 10.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60068751 47.50% 47.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95236 0.08% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53417106 42.24% 90.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12511205 9.89% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124613166 # Type of FU issued -system.cpu.iq.rate 0.301258 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8830169 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070861 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 411460543 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124996425 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85630389 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22925 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12868 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10343 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 133324707 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12098 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 646336 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126458108 # Type of FU issued +system.cpu.iq.rate 0.304490 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8827417 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.069805 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 417011386 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128052835 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87416470 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22950 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12920 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10331 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134909754 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12105 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 645788 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5343093 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11106 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35068 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2077574 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5350138 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11136 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35101 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2080838 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107202 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1049886 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107263 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1048290 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3946580 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29463666 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540836 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 101593235 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 217276 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21058263 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13875749 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 964547 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 125689 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 40656 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35068 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 381127 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332167 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 713294 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121438397 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52461807 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3174769 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4009322 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29478613 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 536036 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103628902 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 217385 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21065339 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13879000 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1466402 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 126510 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 31155 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35101 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 376939 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332400 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 709339 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123236608 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52461044 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3221500 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 256054 # number of nop insts executed -system.cpu.iew.exec_refs 64853171 # number of memory reference insts executed -system.cpu.iew.exec_branches 11412736 # Number of branches executed -system.cpu.iew.exec_stores 12391364 # Number of stores executed -system.cpu.iew.exec_rate 0.293583 # Inst execution rate -system.cpu.iew.wb_sent 120063166 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85640732 # cumulative count of insts written-back -system.cpu.iew.wb_producers 46459932 # num instructions producing a value -system.cpu.iew.wb_consumers 84649521 # num instructions consuming a value +system.cpu.iew.exec_nop 254617 # number of nop insts executed +system.cpu.iew.exec_refs 64851969 # number of memory reference insts executed +system.cpu.iew.exec_branches 11926568 # Number of branches executed +system.cpu.iew.exec_stores 12390925 # Number of stores executed +system.cpu.iew.exec_rate 0.296734 # Inst execution rate +system.cpu.iew.wb_sent 121860265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87426801 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47494075 # num instructions producing a value +system.cpu.iew.wb_consumers 86379183 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.207040 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.548851 # average fanout of values written-back +system.cpu.iew.wb_rate 0.210509 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549832 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59728648 # The number of committed instructions -system.cpu.commit.commitCommittedOps 77076220 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 24329020 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1287267 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625309 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149264139 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.516375 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.492760 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 60745094 # The number of committed instructions +system.cpu.commit.commitCommittedOps 78092668 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 24728606 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544400 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 625654 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151064180 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.516950 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.491641 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121340444 81.29% 81.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13976446 9.36% 90.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3929866 2.63% 93.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2230737 1.49% 94.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1774137 1.19% 95.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1064202 0.71% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1398926 0.94% 97.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 658331 0.44% 98.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2891050 1.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122872114 81.34% 81.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13991345 9.26% 90.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3943128 2.61% 93.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2231050 1.48% 94.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2009345 1.33% 96.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1063949 0.70% 96.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1402638 0.93% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 655924 0.43% 98.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2894687 1.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149264139 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59728648 # Number of instructions committed -system.cpu.commit.committedOps 77076220 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151064180 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60745094 # Number of instructions committed +system.cpu.commit.committedOps 78092668 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27513345 # Number of memory references committed -system.cpu.commit.loads 15715170 # Number of loads committed -system.cpu.commit.membars 413057 # Number of memory barriers committed -system.cpu.commit.branches 9904308 # Number of branches committed +system.cpu.commit.refs 27513363 # Number of memory references committed +system.cpu.commit.loads 15715201 # Number of loads committed +system.cpu.commit.membars 413054 # Number of memory barriers committed +system.cpu.commit.branches 10161447 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68616986 # Number of committed integer instructions. -system.cpu.commit.function_calls 995953 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2891050 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69131310 # Number of committed integer instructions. +system.cpu.commit.function_calls 995952 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2894687 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 246021016 # The number of ROB reads -system.cpu.rob.rob_writes 206855771 # The number of ROB writes -system.cpu.timesIdled 1910853 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260514433 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4591368963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59578267 # Number of Instructions Simulated -system.cpu.committedOps 76925839 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59578267 # Number of Instructions Simulated -system.cpu.cpi 6.942846 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.942846 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144033 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.144033 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 551124722 # number of integer regfile reads -system.cpu.int_regfile_writes 87730818 # number of integer regfile writes -system.cpu.fp_regfile_reads 8186 # number of floating regfile reads -system.cpu.fp_regfile_writes 2858 # number of floating regfile writes -system.cpu.misc_regfile_reads 131789755 # number of misc regfile reads -system.cpu.misc_regfile_writes 912697 # number of misc regfile writes -system.cpu.icache.replacements 991190 # number of replacements -system.cpu.icache.tagsinuse 511.611770 # Cycle average of tags in use -system.cpu.icache.total_refs 12061455 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991702 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.162378 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6426198000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.611770 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999242 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999242 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12061455 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12061455 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12061455 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12061455 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12061455 # number of overall hits -system.cpu.icache.overall_hits::total 12061455 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1076423 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1076423 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1076423 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1076423 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1076423 # number of overall misses -system.cpu.icache.overall_misses::total 1076423 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16851120991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16851120991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16851120991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16851120991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16851120991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16851120991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13137878 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13137878 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13137878 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13137878 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13137878 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13137878 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081933 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081933 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081933 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081933 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081933 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15654.738881 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15654.738881 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15654.738881 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15654.738881 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2871493 # number of cycles access was blocked +system.cpu.rob.rob_reads 249075594 # The number of ROB reads +system.cpu.rob.rob_writes 209750294 # The number of ROB writes +system.cpu.timesIdled 1905944 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260319578 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4591259733 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60594713 # Number of Instructions Simulated +system.cpu.committedOps 77942287 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60594713 # Number of Instructions Simulated +system.cpu.cpi 6.853909 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.853909 # CPI: Total CPI of All Threads +system.cpu.ipc 0.145902 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.145902 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 557815348 # number of integer regfile reads +system.cpu.int_regfile_writes 90098492 # number of integer regfile writes +system.cpu.fp_regfile_reads 8218 # number of floating regfile reads +system.cpu.fp_regfile_writes 2870 # number of floating regfile writes +system.cpu.misc_regfile_reads 134021846 # number of misc regfile reads +system.cpu.misc_regfile_writes 912706 # number of misc regfile writes +system.cpu.icache.replacements 989908 # number of replacements +system.cpu.icache.tagsinuse 511.610984 # Cycle average of tags in use +system.cpu.icache.total_refs 12068184 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990420 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.184915 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6426400000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.610984 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999240 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999240 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12068184 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12068184 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12068184 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12068184 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12068184 # number of overall hits +system.cpu.icache.overall_hits::total 12068184 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1074896 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1074896 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1074896 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1074896 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1074896 # number of overall misses +system.cpu.icache.overall_misses::total 1074896 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16638687991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16638687991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16638687991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16638687991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16638687991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16638687991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13143080 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13143080 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13143080 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13143080 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13143080 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13143080 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081784 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081784 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081784 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081784 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081784 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081784 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15479.346831 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15479.346831 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15479.346831 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15479.346831 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15479.346831 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15479.346831 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2960492 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 461 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 448 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6228.835141 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6608.241071 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 67899 # number of writebacks -system.cpu.icache.writebacks::total 67899 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84680 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84680 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84680 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84680 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84680 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84680 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991743 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 991743 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 991743 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 991743 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 991743 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 991743 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12825867499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12825867499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12825867499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12825867499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12825867499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12825867499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84437 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84437 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84437 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84437 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84437 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84437 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990459 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 990459 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 990459 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 990459 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 990459 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 990459 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12623481992 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12623481992 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12623481992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12623481992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12623481992 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12623481992 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075487 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075487 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075487 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12932.652410 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12932.652410 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075360 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075360 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075360 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075360 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075360 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075360 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.082827 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.082827 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.082827 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.082827 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.082827 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.082827 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643139 # number of replacements -system.cpu.dcache.tagsinuse 511.991335 # Cycle average of tags in use -system.cpu.dcache.total_refs 21733833 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643651 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.766487 # Average number of references to valid blocks. +system.cpu.dcache.replacements 643258 # number of replacements +system.cpu.dcache.tagsinuse 511.991338 # Cycle average of tags in use +system.cpu.dcache.total_refs 21734239 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643770 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.760876 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991335 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.991338 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13904166 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13904166 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7257095 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7257095 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 283844 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 283844 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285639 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285639 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21161261 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21161261 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21161261 # number of overall hits -system.cpu.dcache.overall_hits::total 21161261 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 765252 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 765252 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2993311 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2993311 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13765 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13765 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3758563 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3758563 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3758563 # number of overall misses -system.cpu.dcache.overall_misses::total 3758563 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14844603000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14844603000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129412035593 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129412035593 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223977000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 223977000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 405000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 405000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144256638593 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144256638593 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144256638593 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144256638593 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14669418 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14669418 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250406 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250406 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297609 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 297609 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285658 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285658 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24919824 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24919824 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24919824 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24919824 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052166 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052166 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292019 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.292019 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046252 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046252 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000067 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000067 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.150826 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.150826 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.150826 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.150826 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19398.319769 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19398.319769 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43233.742031 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43233.742031 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16271.485652 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16271.485652 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21315.789474 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21315.789474 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38380.795691 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38380.795691 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32633902 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7260500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7285 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4479.602196 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 25655.477032 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13902749 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13902749 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7257426 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7257426 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 285261 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 285261 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285646 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285646 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21160175 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21160175 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21160175 # number of overall hits +system.cpu.dcache.overall_hits::total 21160175 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 765054 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 765054 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2992955 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2992955 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13791 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13791 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 18 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3758009 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3758009 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3758009 # number of overall misses +system.cpu.dcache.overall_misses::total 3758009 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14856915000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14856915000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 130200810067 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 130200810067 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223590500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 223590500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 349500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 349500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 145057725067 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 145057725067 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 145057725067 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 145057725067 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14667803 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14667803 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250381 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250381 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299052 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 299052 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285664 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285664 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24918184 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24918184 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24918184 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24918184 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052159 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052159 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.291985 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.291985 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046116 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046116 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000063 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000063 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.150814 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.150814 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.150814 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.150814 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19419.433138 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19419.433138 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43502.428225 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43502.428225 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16212.783700 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16212.783700 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19416.666667 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19416.666667 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38599.621520 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38599.621520 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38599.621520 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38599.621520 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 34077900 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7429000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7467 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 284 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4563.800723 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 26158.450704 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607543 # number of writebacks -system.cpu.dcache.writebacks::total 607543 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379767 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 379767 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744505 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2744505 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3124272 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3124272 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3124272 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3124272 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385485 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385485 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248806 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248806 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12312 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12312 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634291 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634291 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634291 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634291 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6242554097 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6242554097 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9246380950 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9246380950 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164108000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164108000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 341500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 341500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15488935047 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15488935047 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15488935047 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15488935047 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147082070000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147082070000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41215087708 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41215087708 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188297157708 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 188297157708 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024273 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024273 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041370 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041370 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000067 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000067 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025453 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025453 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16194.025960 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16194.025960 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37163.014357 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37163.014357 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13329.109812 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13329.109812 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17973.684211 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17973.684211 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607519 # number of writebacks +system.cpu.dcache.writebacks::total 607519 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379422 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 379422 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744177 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2744177 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1481 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1481 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3123599 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3123599 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3123599 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3123599 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385632 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385632 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248778 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248778 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12310 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12310 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 18 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 18 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634410 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634410 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634410 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634410 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6262166095 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6262166095 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9286622435 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9286622435 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 163471000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 163471000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 289000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 289000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15548788530 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15548788530 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15548788530 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15548788530 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147078103000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147078103000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41268229410 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41268229410 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188346332410 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 188346332410 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026291 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026291 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024270 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024270 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041163 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041163 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000063 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000063 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025460 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025460 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025460 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025460 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.709690 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.709690 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37328.953666 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37328.953666 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13279.528838 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13279.528838 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16055.555556 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16055.555556 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.053341 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.053341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.053341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.053341 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -918,16 +916,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1298563544001 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1298563544001 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305424568773 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1305424568773 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305424568773 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1305424568773 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88049 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88047 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 1fa068d9c..2ecc483cf 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -1261,7 +1261,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1281,7 +1281,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index e7dca044c..22a267134 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 22 2012 08:05:39 -gem5 started Jul 22 2012 08:05:57 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jul 26 2012 21:30:36 +gem5 started Jul 27 2012 00:44:18 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5172902281500 because m5_exit instruction encountered +Exiting @ tick 5172910256500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 4fa4cc520..d3e4451ad 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,186 +1,186 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.172902 # Number of seconds simulated -sim_ticks 5172902281500 # Number of ticks simulated -final_tick 5172902281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.172910 # Number of seconds simulated +sim_ticks 5172910256500 # Number of ticks simulated +final_tick 5172910256500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117061 # Simulator instruction rate (inst/s) -host_op_rate 230687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1419746087 # Simulator tick rate (ticks/s) -host_mem_usage 420308 # Number of bytes of host memory used -host_seconds 3643.54 # Real time elapsed on the host -sim_insts 426515724 # Number of instructions simulated -sim_ops 840516219 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2496512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1067840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10426304 # Number of bytes read from this memory -system.physmem.bytes_read::total 13994560 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1067840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1067840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9194240 # Number of bytes written to this memory -system.physmem.bytes_written::total 9194240 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 39008 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16685 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 162911 # Number of read requests responded to by this memory -system.physmem.num_reads::total 218665 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143660 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143660 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 482613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 206430 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2015562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2705359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 206430 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 206430 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1777385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1777385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1777385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 482613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 206430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2015562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4482745 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 107419 # number of replacements -system.l2c.tagsinuse 64844.084797 # Cycle average of tags in use -system.l2c.total_refs 3992672 # Total number of references to valid blocks. -system.l2c.sampled_refs 171622 # Sample count of references to valid blocks. -system.l2c.avg_refs 23.264337 # Average number of references to valid blocks. +host_inst_rate 136129 # Simulator instruction rate (inst/s) +host_op_rate 268264 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1651021148 # Simulator tick rate (ticks/s) +host_mem_usage 373420 # Number of bytes of host memory used +host_seconds 3133.16 # Real time elapsed on the host +sim_insts 426513995 # Number of instructions simulated +sim_ops 840512563 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2464064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1067584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10442240 # Number of bytes read from this memory +system.physmem.bytes_read::total 13977280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1067584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1067584 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9176384 # Number of bytes written to this memory +system.physmem.bytes_written::total 9176384 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16681 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 163160 # Number of read requests responded to by this memory +system.physmem.num_reads::total 218395 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143381 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143381 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 476340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 206380 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2018639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2702015 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 206380 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 206380 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1773931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1773931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1773931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 476340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 206380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2018639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4475945 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 106892 # number of replacements +system.l2c.tagsinuse 64846.239814 # Cycle average of tags in use +system.l2c.total_refs 3994467 # Total number of references to valid blocks. +system.l2c.sampled_refs 171328 # Sample count of references to valid blocks. +system.l2c.avg_refs 23.314735 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50135.967843 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 12.897301 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.156788 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3372.666022 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11322.396844 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.765014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000197 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.051463 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.172766 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.989442 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 110667 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 8396 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1054432 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1345104 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2518599 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1613189 # number of Writeback hits -system.l2c.Writeback_hits::total 1613189 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 337 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 337 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 163997 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 163997 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 110667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 8396 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1054432 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1509101 # number of demand (read+write) hits -system.l2c.demand_hits::total 2682596 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 110667 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 8396 # number of overall hits -system.l2c.overall_hits::cpu.inst 1054432 # number of overall hits -system.l2c.overall_hits::cpu.data 1509101 # number of overall hits -system.l2c.overall_hits::total 2682596 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 55 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 16686 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 35012 # number of ReadReq misses -system.l2c.ReadReq_misses::total 51759 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1516 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1516 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 128839 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 128839 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 55 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 16686 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 163851 # number of demand (read+write) misses -system.l2c.demand_misses::total 180598 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 55 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 6 # number of overall misses -system.l2c.overall_misses::cpu.inst 16686 # number of overall misses -system.l2c.overall_misses::cpu.data 163851 # number of overall misses -system.l2c.overall_misses::total 180598 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2907000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 312000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 885914499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1865182494 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2754315993 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 39171500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 39171500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6715513999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6715513999 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 2907000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 312000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 885914499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 8580696493 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9469829992 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 2907000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 312000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 885914499 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 8580696493 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9469829992 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 110722 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 8402 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 1071118 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1380116 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2570358 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1613189 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1613189 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 1853 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1853 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 292836 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292836 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 110722 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 8402 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 1071118 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1672952 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2863194 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 110722 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 8402 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1071118 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1672952 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2863194 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000497 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000714 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.015578 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.025369 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020137 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.818133 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.818133 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.439970 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.439970 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000497 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000714 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.015578 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.097941 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.063076 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000497 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.000714 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.015578 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.097941 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.063076 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52854.545455 # average ReadReq miss latency +system.l2c.occ_blocks::writebacks 50145.406461 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 11.508776 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.169764 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3382.865025 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11306.289787 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.765158 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000176 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000003 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.051618 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.172520 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.989475 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 113294 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 9300 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 1056563 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1345318 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2524475 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1607595 # number of Writeback hits +system.l2c.Writeback_hits::total 1607595 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 334 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 334 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 163366 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 163366 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 113294 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 9300 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 1056563 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1508684 # number of demand (read+write) hits +system.l2c.demand_hits::total 2687841 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 113294 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 9300 # number of overall hits +system.l2c.overall_hits::cpu.inst 1056563 # number of overall hits +system.l2c.overall_hits::cpu.data 1508684 # number of overall hits +system.l2c.overall_hits::total 2687841 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 16683 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 35188 # number of ReadReq misses +system.l2c.ReadReq_misses::total 51924 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2935 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2935 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 128896 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 128896 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 46 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 16683 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 164084 # number of demand (read+write) misses +system.l2c.demand_misses::total 180820 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 46 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 7 # number of overall misses +system.l2c.overall_misses::cpu.inst 16683 # number of overall misses +system.l2c.overall_misses::cpu.data 164084 # number of overall misses +system.l2c.overall_misses::total 180820 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2412500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 364000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 885747500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1875717995 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2764241995 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 38348000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 38348000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6718316497 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6718316497 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 2412500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 364000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 885747500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 8594034492 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9482558492 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 2412500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 364000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 885747500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 8594034492 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9482558492 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 113340 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 9307 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 1073246 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1380506 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2576399 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1607595 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1607595 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 3269 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3269 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 292262 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 292262 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 113340 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 9307 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1073246 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1672768 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2868661 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 113340 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 9307 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1073246 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1672768 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2868661 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000406 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000752 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.015544 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.025489 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.020154 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.897828 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.897828 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.441029 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.441029 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000406 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000752 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.015544 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.098091 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.063033 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000406 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000752 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.015544 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.098091 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.063033 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52445.652174 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 53093.281733 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 53272.663487 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 53214.242798 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 25838.720317 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 25838.720317 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52123.301167 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52123.301167 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52854.545455 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 53092.819037 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 53305.615409 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 53236.306814 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13065.758092 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 13065.758092 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52121.993677 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52121.993677 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52445.652174 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 53093.281733 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52368.899140 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52435.962702 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52854.545455 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 53092.819037 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52375.822701 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52441.978166 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52445.652174 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 53093.281733 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52368.899140 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52435.962702 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 53092.819037 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52375.822701 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52441.978166 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -189,99 +189,99 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 96993 # number of writebacks -system.l2c.writebacks::total 96993 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 96714 # number of writebacks +system.l2c.writebacks::total 96714 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 55 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 16685 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 35011 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 51757 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 1516 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1516 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 128839 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 128839 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 55 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 16685 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 163850 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 180596 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 55 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 16685 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 163850 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 180596 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2241000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 240000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 682427500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 1437356500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2122265000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 61068000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 61068000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5163609501 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5163609501 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2241000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 240000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 682427500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 6600966001 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 7285874501 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2241000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 240000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 682427500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 6600966001 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 7285874501 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59192209064 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 59192209064 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1211526000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1211526000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 60403735064 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 60403735064 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.020136 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.818133 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.818133 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.439970 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.439970 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.097941 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.063075 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.097941 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.063075 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average ReadReq mshr miss latency +system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 46 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 16681 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 35187 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 51921 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 2935 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2935 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 128896 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 128896 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 46 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 16681 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 164083 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 180817 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 46 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 16681 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 164083 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 180817 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 1851000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 280000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 682272500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 1445683499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2130086999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 117833500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 117833500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5165552500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5165552500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 1851000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 280000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 682272500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6611235999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7295639499 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 1851000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 280000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 682272500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6611235999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7295639499 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59192780564 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59192780564 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1212414000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1212414000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 60405194564 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60405194564 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000406 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000752 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015543 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025488 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020153 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.897828 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.897828 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.441029 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.441029 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000406 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000752 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.015543 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.098091 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000406 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000752 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.015543 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.098091 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40900.659275 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41054.425752 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 41004.405201 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40282.321900 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40282.321900 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.000458 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40078.000458 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40901.174990 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41085.727655 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 41025.538780 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40147.700170 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40147.700170 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40075.351446 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40075.351446 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40900.659275 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40286.640226 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40343.498754 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40901.174990 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40292.022934 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40348.194578 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40900.659275 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40286.640226 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40343.498754 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40901.174990 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40292.022934 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40348.194578 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -289,39 +289,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47565 # number of replacements -system.iocache.tagsinuse 0.200108 # Cycle average of tags in use +system.iocache.replacements 47569 # number of replacements +system.iocache.tagsinuse 0.199376 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47581 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47585 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5000599162000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.200108 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.012507 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.012507 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 900 # number of ReadReq misses -system.iocache.ReadReq_misses::total 900 # number of ReadReq misses +system.iocache.warmup_cycle 5000598404000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.199376 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.012461 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.012461 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 904 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47620 # number of demand (read+write) misses -system.iocache.demand_misses::total 47620 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47620 # number of overall misses -system.iocache.overall_misses::total 47620 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135466932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 135466932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6926961160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6926961160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 7062428092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7062428092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 7062428092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7062428092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 900 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 900 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses +system.iocache.demand_misses::total 47624 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses +system.iocache.overall_misses::total 47624 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135906932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 135906932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6908833160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6908833160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 7044740092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7044740092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 7044740092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7044740092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47620 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47620 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47620 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47620 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -330,14 +330,14 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150518.813333 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 150518.813333 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 148265.435788 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 148265.435788 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148308.023772 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 148308.023772 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148308.023772 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 148308.023772 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150339.526549 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 150339.526549 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147877.422089 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 147877.422089 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147924.157820 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 147924.157820 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147924.157820 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 147924.157820 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked @@ -348,22 +348,22 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 900 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 900 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 904 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 904 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47620 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47620 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47620 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47620 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88635000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 88635000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4497207944 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4497207944 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4585842944 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4585842944 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4585842944 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4585842944 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47624 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47624 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47624 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47624 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88867000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 88867000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4479079912 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4479079912 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4567946912 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4567946912 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4567946912 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4567946912 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -372,14 +372,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98483.333333 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 98483.333333 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 96258.731678 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 96258.731678 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96300.775808 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 96300.775808 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96300.775808 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 96300.775808 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98304.203540 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 98304.203540 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95870.717295 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 95870.717295 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 95916.909793 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 95916.909793 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 95916.909793 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 95916.909793 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -393,107 +393,107 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 472946175 # number of cpu cycles simulated +system.cpu.numCycles 473223088 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 90027772 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 90027772 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1176455 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 84282590 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 81704922 # Number of BTB hits +system.cpu.BPredUnit.lookups 90016360 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 90016360 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1178248 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 84343978 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 81707122 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31264026 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 446943348 # Number of instructions fetch has processed -system.cpu.fetch.Branches 90027772 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 81704922 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 169792009 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5327046 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 167003 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 104616235 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 45804 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 481 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9365381 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 539972 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5058 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 310035010 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.836765 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.376817 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 31356562 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 446929489 # Number of instructions fetch has processed +system.cpu.fetch.Branches 90016360 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 81707122 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 169790434 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5330018 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 171751 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 104797996 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37968 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 45006 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 453 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9363044 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 536807 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5287 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 310312997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.834177 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.376352 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140677603 45.37% 45.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1773611 0.57% 45.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72784877 23.48% 69.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 988899 0.32% 69.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1639325 0.53% 70.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3670845 1.18% 71.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1138945 0.37% 71.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1446155 0.47% 72.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85914750 27.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140957479 45.42% 45.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1776597 0.57% 46.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72781994 23.45% 69.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 982988 0.32% 69.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1642902 0.53% 70.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3674853 1.18% 71.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1139478 0.37% 71.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1444103 0.47% 72.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85912603 27.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 310035010 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.190355 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.945019 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36438516 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100672732 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 164105371 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4706760 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4111631 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 876235114 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1005 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4111631 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 40855551 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 44279722 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10981847 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 163785428 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46020831 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 872430616 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10252 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 35253394 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3952381 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31994944 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1394146617 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2488353855 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2488353319 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 536 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1347546781 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 46599829 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 470336 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 478135 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48126988 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 18909339 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10455877 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1294020 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1017517 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 865756561 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1721302 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 864328719 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 124616 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26046990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 53600910 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 205527 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 310035010 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.787842 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.396151 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 310312997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.190220 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.944437 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36508708 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100881020 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 164105770 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4704672 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4112827 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 876214899 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 957 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4112827 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 40925858 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 44314017 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11153757 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 163784094 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46022444 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 872421528 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10519 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 35242822 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3962452 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 32001317 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1394162179 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2488413918 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2488413062 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 856 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1347546247 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 46615925 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 471039 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 478955 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48145791 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 18923985 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10455746 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1291287 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1021115 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 865765672 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1722965 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 864313181 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 123185 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26037339 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 53671952 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 207307 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 310312997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.785295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.396376 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 102334281 33.01% 33.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23751530 7.66% 40.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 19011662 6.13% 46.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7830278 2.53% 49.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 80611792 26.00% 75.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3104970 1.00% 76.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72755101 23.47% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 522761 0.17% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 112635 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 102585339 33.06% 33.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23772488 7.66% 40.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 19036495 6.13% 46.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7825788 2.52% 49.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 80603332 25.97% 75.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3104423 1.00% 76.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72752969 23.45% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 520222 0.17% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 111941 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 310035010 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 310312997 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 164564 7.88% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 164594 7.88% 7.88% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 7.88% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 7.88% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.88% # attempts to use FU when none available @@ -522,12 +522,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.88% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.88% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.88% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1763434 84.48% 92.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 159280 7.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1764434 84.50% 92.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 159044 7.62% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 297202 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 829439322 95.96% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 296261 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 829427794 95.96% 96.00% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.00% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.00% # Type of FU issued @@ -556,250 +556,248 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.00% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.00% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.00% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25154463 2.91% 98.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9437732 1.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25158656 2.91% 98.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9430470 1.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 864328719 # Type of FU issued -system.cpu.iq.rate 1.827541 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2087278 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002415 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2041042185 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 893535851 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 853927067 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 224 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 866118699 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 96 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1579181 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 864313181 # Type of FU issued +system.cpu.iq.rate 1.826439 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2088072 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002416 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2041288204 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 893536846 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 853917717 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 372 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 410 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 866104816 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 176 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1579729 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3618734 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20083 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12084 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2054359 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3631905 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20141 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12168 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2053612 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7821519 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4487 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7821470 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4399 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4111631 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27910035 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1927143 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 867477863 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 297836 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 18909339 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10455877 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 883178 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 975186 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15536 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12084 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 697834 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 626380 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1324214 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 862437508 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24726867 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1891210 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4112827 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27932530 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1927286 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 867488637 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 301587 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 18923985 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10455746 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 885039 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 975379 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15665 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12168 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 701708 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 624080 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1325788 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 862427395 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24732275 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1885785 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 33920253 # number of memory reference insts executed -system.cpu.iew.exec_branches 86495383 # Number of branches executed -system.cpu.iew.exec_stores 9193386 # Number of stores executed -system.cpu.iew.exec_rate 1.823543 # Inst execution rate -system.cpu.iew.wb_sent 861952908 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 853927121 # cumulative count of insts written-back -system.cpu.iew.wb_producers 669642895 # num instructions producing a value -system.cpu.iew.wb_consumers 1918737755 # num instructions consuming a value +system.cpu.iew.exec_refs 33921373 # number of memory reference insts executed +system.cpu.iew.exec_branches 86494176 # Number of branches executed +system.cpu.iew.exec_stores 9189098 # Number of stores executed +system.cpu.iew.exec_rate 1.822454 # Inst execution rate +system.cpu.iew.wb_sent 861944484 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 853917813 # cumulative count of insts written-back +system.cpu.iew.wb_producers 669630870 # num instructions producing a value +system.cpu.iew.wb_consumers 1918703675 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.805548 # insts written-back per cycle +system.cpu.iew.wb_rate 1.804472 # insts written-back per cycle system.cpu.iew.wb_fanout 0.349002 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 426515724 # The number of committed instructions -system.cpu.commit.commitCommittedOps 840516219 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26857823 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1515773 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1181578 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 305938932 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.747333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.861326 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 426513995 # The number of committed instructions +system.cpu.commit.commitCommittedOps 840512563 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26872606 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1515656 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1183314 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 306215725 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.744838 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.861126 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 125006118 40.86% 40.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14720749 4.81% 45.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4254060 1.39% 47.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76641454 25.05% 72.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3896789 1.27% 73.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1794252 0.59% 73.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1101361 0.36% 74.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71996786 23.53% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6527363 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 125266635 40.91% 40.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14734551 4.81% 45.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4258737 1.39% 47.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76646765 25.03% 72.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3892941 1.27% 73.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1792387 0.59% 74.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1104205 0.36% 74.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71994718 23.51% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6524786 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 305938932 # Number of insts commited each cycle -system.cpu.commit.committedInsts 426515724 # Number of instructions committed -system.cpu.commit.committedOps 840516219 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 306215725 # Number of insts commited each cycle +system.cpu.commit.committedInsts 426513995 # Number of instructions committed +system.cpu.commit.committedOps 840512563 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23692120 # Number of memory references committed -system.cpu.commit.loads 15290602 # Number of loads committed -system.cpu.commit.membars 781565 # Number of memory barriers committed -system.cpu.commit.branches 85505775 # Number of branches committed +system.cpu.commit.refs 23694211 # Number of memory references committed +system.cpu.commit.loads 15292077 # Number of loads committed +system.cpu.commit.membars 781571 # Number of memory barriers committed +system.cpu.commit.branches 85505598 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768334838 # Number of committed integer instructions. +system.cpu.commit.int_insts 768332766 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6527363 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6524786 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1166706140 # The number of ROB reads -system.cpu.rob.rob_writes 1738874776 # The number of ROB writes -system.cpu.timesIdled 2996123 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 162911165 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9872855838 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 426515724 # Number of Instructions Simulated -system.cpu.committedOps 840516219 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 426515724 # Number of Instructions Simulated -system.cpu.cpi 1.108860 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.108860 # CPI: Total CPI of All Threads -system.cpu.ipc 0.901827 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.901827 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2163141042 # number of integer regfile reads -system.cpu.int_regfile_writes 1362663536 # number of integer regfile writes -system.cpu.fp_regfile_reads 54 # number of floating regfile reads -system.cpu.misc_regfile_reads 281062978 # number of misc regfile reads -system.cpu.misc_regfile_writes 403820 # number of misc regfile writes -system.cpu.icache.replacements 1070658 # number of replacements -system.cpu.icache.tagsinuse 510.425099 # Cycle average of tags in use -system.cpu.icache.total_refs 8224431 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1071170 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.677989 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56932899000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.425099 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996924 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996924 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8224431 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8224431 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8224431 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8224431 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8224431 # number of overall hits -system.cpu.icache.overall_hits::total 8224431 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1140947 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1140947 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1140947 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1140947 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1140947 # number of overall misses -system.cpu.icache.overall_misses::total 1140947 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18841256486 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18841256486 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18841256486 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18841256486 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18841256486 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18841256486 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9365378 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9365378 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9365378 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9365378 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9365378 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9365378 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121826 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.121826 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.121826 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.121826 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.121826 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.121826 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16513.700011 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16513.700011 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16513.700011 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16513.700011 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16513.700011 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16513.700011 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3271992 # number of cycles access was blocked +system.cpu.rob.rob_reads 1166996622 # The number of ROB reads +system.cpu.rob.rob_writes 1738897212 # The number of ROB writes +system.cpu.timesIdled 2997983 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 162910091 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9872594876 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 426513995 # Number of Instructions Simulated +system.cpu.committedOps 840512563 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 426513995 # Number of Instructions Simulated +system.cpu.cpi 1.109514 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.109514 # CPI: Total CPI of All Threads +system.cpu.ipc 0.901296 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.901296 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2163164515 # number of integer regfile reads +system.cpu.int_regfile_writes 1362660599 # number of integer regfile writes +system.cpu.fp_regfile_reads 96 # number of floating regfile reads +system.cpu.misc_regfile_reads 281055752 # number of misc regfile reads +system.cpu.misc_regfile_writes 403699 # number of misc regfile writes +system.cpu.icache.replacements 1072786 # number of replacements +system.cpu.icache.tagsinuse 510.225454 # Cycle average of tags in use +system.cpu.icache.total_refs 8218240 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1073298 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.656997 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56932893000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.225454 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996534 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996534 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8218240 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8218240 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8218240 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8218240 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8218240 # number of overall hits +system.cpu.icache.overall_hits::total 8218240 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1144801 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1144801 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1144801 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1144801 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1144801 # number of overall misses +system.cpu.icache.overall_misses::total 1144801 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18871083485 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18871083485 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18871083485 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18871083485 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18871083485 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18871083485 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9363041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9363041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9363041 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9363041 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9363041 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9363041 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122268 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.122268 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.122268 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.122268 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.122268 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.122268 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16484.160553 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16484.160553 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16484.160553 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16484.160553 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16484.160553 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16484.160553 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3261491 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 399 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 378 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 8200.481203 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 8628.283069 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1605 # number of writebacks -system.cpu.icache.writebacks::total 1605 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69655 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69655 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69655 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69655 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69655 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69655 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071292 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1071292 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1071292 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1071292 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1071292 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1071292 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14719464992 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14719464992 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14719464992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14719464992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14719464992 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14719464992 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114389 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114389 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114389 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13739.918708 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13739.918708 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13739.918708 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13739.918708 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13739.918708 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13739.918708 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69972 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69972 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69972 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69972 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69972 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69972 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1074829 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1074829 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1074829 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1074829 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1074829 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1074829 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14733142991 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14733142991 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14733142991 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14733142991 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14733142991 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14733142991 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114795 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114795 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114795 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114795 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114795 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114795 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13707.429732 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13707.429732 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13707.429732 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13707.429732 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13707.429732 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13707.429732 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 10504 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.031363 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 31807 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 10516 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 3.024629 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5135227037000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.031363 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376960 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.376960 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 31848 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 31848 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 11223 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.037503 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 31260 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 11237 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.781881 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5131387386000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.037503 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.377344 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.377344 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 31468 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 31468 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 31851 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 31851 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 31851 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 31851 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11386 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 11386 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11386 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 11386 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11386 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 11386 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 182254500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 182254500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 182254500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 182254500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 182254500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 182254500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43234 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 43234 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 31471 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 31471 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 31471 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 31471 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 12107 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 12107 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 12107 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 12107 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 12107 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 12107 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 196957000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 196957000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 196957000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 196957000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 196957000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 196957000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43575 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 43575 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43237 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 43237 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43237 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 43237 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.263358 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.263358 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.263339 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.263339 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.263339 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.263339 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16006.894432 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16006.894432 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16006.894432 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16006.894432 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16006.894432 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16006.894432 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43578 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 43578 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43578 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 43578 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.277843 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.277843 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.277824 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.277824 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.277824 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.277824 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16268.026761 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16268.026761 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16268.026761 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16268.026761 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16268.026761 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16268.026761 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -808,78 +806,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1641 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1641 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11386 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11386 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11386 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 11386 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11386 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 11386 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147453030 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147453030 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147453030 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147453030 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147453030 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147453030 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.263358 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.263358 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.263339 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.263339 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.263339 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.263339 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12950.380292 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 12950.380292 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 12950.380292 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1700 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1700 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 12107 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 12107 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 12107 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 12107 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 12107 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 12107 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 159950045 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 159950045 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159950045 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 159950045 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159950045 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159950045 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.277843 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.277843 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.277824 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.277824 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.277824 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.277824 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13211.369043 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13211.369043 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13211.369043 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13211.369043 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13211.369043 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13211.369043 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 117278 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.523999 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 136775 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 117293 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.166097 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5112876101000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.523999 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.845250 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.845250 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 136779 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 136779 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 136779 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 136779 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 136779 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 136779 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 118304 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 118304 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 118304 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 118304 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 118304 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 118304 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2123660000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2123660000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2123660000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 2123660000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2123660000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 2123660000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 255083 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 255083 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 255083 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 255083 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 255083 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 255083 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.463786 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.463786 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.463786 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.463786 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.463786 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.463786 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 17950.872329 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 17950.872329 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 17950.872329 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 17950.872329 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 17950.872329 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 17950.872329 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 118986 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.873264 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 132191 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 119002 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.110830 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5112880781000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.873264 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.867079 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.867079 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 132191 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 132191 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 132191 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 132191 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 132191 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 132191 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 120057 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 120057 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 120057 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 120057 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 120057 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 120057 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2156991000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2156991000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2156991000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 2156991000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2156991000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 2156991000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 252248 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 252248 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 252248 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 252248 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 252248 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 252248 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.475948 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.475948 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.475948 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.475948 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.475948 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.475948 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 17966.390964 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 17966.390964 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 17966.390964 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 17966.390964 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 17966.390964 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 17966.390964 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -888,146 +886,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 37674 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 37674 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 118304 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 118304 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 118304 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 118304 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 118304 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 118304 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1766049009 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1766049009 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1766049009 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.463786 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.463786 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.463786 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 14928.058299 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 14928.058299 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 14928.058299 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 34205 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 34205 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 120057 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 120057 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 120057 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 120057 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 120057 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 120057 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1794187508 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1794187508 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1794187508 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1794187508 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1794187508 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1794187508 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.475948 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.475948 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.475948 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.475948 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.475948 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.475948 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 14944.463946 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 14944.463946 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 14944.463946 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1673136 # number of replacements -system.cpu.dcache.tagsinuse 511.997556 # Cycle average of tags in use -system.cpu.dcache.total_refs 19006106 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1673648 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.356095 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1672900 # number of replacements +system.cpu.dcache.tagsinuse 511.996980 # Cycle average of tags in use +system.cpu.dcache.total_refs 19011613 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1673412 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.360988 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 36854000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997556 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10928708 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10928708 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8074811 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8074811 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19003519 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19003519 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19003519 # number of overall hits -system.cpu.dcache.overall_hits::total 19003519 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2430538 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2430538 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317333 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317333 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2747871 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2747871 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2747871 # number of overall misses -system.cpu.dcache.overall_misses::total 2747871 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 45186101000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 45186101000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10603069990 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10603069990 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 55789170990 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 55789170990 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 55789170990 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 55789170990 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13359246 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13359246 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8392144 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8392144 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21751390 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21751390 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21751390 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21751390 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181937 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.181937 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037813 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037813 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.126331 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.126331 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.126331 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.126331 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18590.987263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18590.987263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33413.070781 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33413.070781 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20302.689242 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20302.689242 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20302.689242 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20302.689242 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 27875990 # number of cycles access was blocked +system.cpu.dcache.occ_blocks::cpu.data 511.996980 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10933058 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10933058 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8074504 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8074504 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19007562 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19007562 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19007562 # number of overall hits +system.cpu.dcache.overall_hits::total 19007562 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2431156 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2431156 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318255 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318255 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2749411 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2749411 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2749411 # number of overall misses +system.cpu.dcache.overall_misses::total 2749411 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 45213675500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 45213675500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10676522982 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10676522982 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 55890198482 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55890198482 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55890198482 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55890198482 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13364214 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13364214 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8392759 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8392759 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21756973 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21756973 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21756973 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21756973 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181915 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.181915 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037920 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037920 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.126369 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.126369 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.126369 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.126369 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18597.603568 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18597.603568 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33547.070689 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33547.070689 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20328.062440 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20328.062440 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20328.062440 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20328.062440 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 26730982 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4957 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4911 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5623.560621 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5443.083282 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1572269 # number of writebacks -system.cpu.dcache.writebacks::total 1572269 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1049151 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1049151 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22726 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 22726 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1071877 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1071877 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1071877 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1071877 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381387 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1381387 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294607 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 294607 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1675994 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1675994 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1675994 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1675994 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23290713035 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23290713035 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9337845997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9337845997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32628559032 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 32628559032 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32628559032 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 32628559032 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207723000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207723000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1386731000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1386731000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86594454000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 86594454000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103403 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103403 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035105 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035105 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077052 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077052 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077052 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16860.382380 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16860.382380 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31695.940684 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31695.940684 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19468.183676 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19468.183676 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19468.183676 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19468.183676 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1571690 # number of writebacks +system.cpu.dcache.writebacks::total 1571690 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1049439 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1049439 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22786 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 22786 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1072225 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1072225 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1072225 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1072225 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381717 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1381717 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 295469 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 295469 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1677186 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1677186 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1677186 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1677186 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23302977034 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23302977034 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9408800483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9408800483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32711777517 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 32711777517 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32711777517 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 32711777517 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85208357000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85208357000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1386111000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1386111000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86594468000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 86594468000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103389 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103389 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035205 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035205 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077087 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.077087 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077087 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077087 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16865.231472 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16865.231472 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31843.612978 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31843.612978 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19503.965283 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19503.965283 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19503.965283 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19503.965283 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini index 7b9ea05e8..c9fc9d3a5 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -642,30 +642,20 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=32768 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=32768 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -706,30 +696,20 @@ version=1 [system.l1_cntrl1.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=32768 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl1.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=32768 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl1.sequencer] type=RubySequencer @@ -766,16 +746,11 @@ version=0 [system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=15 replacement_policy=PSEUDO_LRU -resourceStalls=false size=4194304 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.pc] type=Pc @@ -1020,7 +995,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1040,7 +1015,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1215,9 +1190,9 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=8 +width=64 default=system.pc.pciconfig.pio -master=system.physmem.port system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave +master=system.physmem.port[0] system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave slave=system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master system.l1_cntrl0.sequencer.pio_port system.l1_cntrl1.sequencer.pio_port system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master [system.ruby] @@ -1244,104 +1219,74 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 int_links0 int_links1 int_links2 int_links3 int_links4 +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 int_links0 int_links1 int_links2 int_links3 int_links4 routers0 routers1 routers2 routers3 routers4 routers5 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 system.ruby.network.topology.routers4 system.ruby.network.topology.routers5 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers0 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl1 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers1 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.ext_links2] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.ext_links2.int_node +int_node=system.ruby.network.topology.routers2 latency=1 link_id=2 weight=1 -[system.ruby.network.topology.ext_links2.int_node] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.ext_links3] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links3.int_node +int_node=system.ruby.network.topology.routers3 latency=1 link_id=3 weight=1 -[system.ruby.network.topology.ext_links3.int_node] -type=BasicRouter -router_id=3 - [system.ruby.network.topology.ext_links4] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dma_cntrl0 -int_node=system.ruby.network.topology.ext_links4.int_node +int_node=system.ruby.network.topology.routers4 latency=1 link_id=4 weight=1 -[system.ruby.network.topology.ext_links4.int_node] -type=BasicRouter -router_id=4 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=5 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers5 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=5 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=6 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers5 weight=1 [system.ruby.network.topology.int_links2] @@ -1349,8 +1294,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=7 -node_a=system.ruby.network.topology.ext_links2.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers5 weight=1 [system.ruby.network.topology.int_links3] @@ -1358,8 +1303,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=8 -node_a=system.ruby.network.topology.ext_links3.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers3 +node_b=system.ruby.network.topology.routers5 weight=1 [system.ruby.network.topology.int_links4] @@ -1367,10 +1312,34 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=9 -node_a=system.ruby.network.topology.ext_links4.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers4 +node_b=system.ruby.network.topology.routers5 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + +[system.ruby.network.topology.routers4] +type=BasicRouter +router_id=4 + +[system.ruby.network.topology.routers5] +type=BasicRouter +router_id=5 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr index a4244c4ca..62578ab56 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr @@ -3,10 +3,8 @@ warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. warn: instruction 'fxsave' unimplemented -warn: x86 cpuid: unknown family 0x8086 warn: instruction 'wbinvd' unimplemented warn: instruction 'wbinvd' unimplemented -warn: x86 cpuid: unknown family 0x8086 hack: Assuming logical destinations are 1 << id. warn: Tried to clear PCI interrupt 14 warn: Unknown mouse command 0xe1. diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout index 00f64894a..d6cb455f2 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout -Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 22 2012 08:55:10 -gem5 started Jul 22 2012 08:55:16 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jun 4 2012 13:44:12 +gem5 started Jun 4 2012 17:11:29 +gem5 executing on zizzer command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5305568377500 because m5_exit instruction encountered +Exiting @ tick 5304689685500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index 90df3051e..b7d143468 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,107 +1,77 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.305568 # Number of seconds simulated -sim_ticks 5305568377500 # Number of ticks simulated -final_tick 5305568377500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.304690 # Number of seconds simulated +sim_ticks 5304689685500 # Number of ticks simulated +final_tick 5304689685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148548 # Simulator instruction rate (inst/s) -host_op_rate 304739 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5673062484 # Simulator tick rate (ticks/s) -host_mem_usage 518516 # Number of bytes of host memory used -host_seconds 935.22 # Real time elapsed on the host -sim_insts 138925597 # Number of instructions simulated -sim_ops 284998538 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 35160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 131880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 65368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 843619360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 40106316 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 91872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 42696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 468873856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 53484588 # Number of bytes read from this memory -system.physmem.bytes_read::total 1406451096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 843619360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 468873856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1312493216 # Number of instructions bytes read from this memory +host_inst_rate 163049 # Simulator instruction rate (inst/s) +host_op_rate 333085 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6301127704 # Simulator tick rate (ticks/s) +host_mem_usage 481488 # Number of bytes of host memory used +host_seconds 841.86 # Real time elapsed on the host +sim_insts 137264752 # Number of instructions simulated +sim_ops 280412254 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 35144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 126800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 827772912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 39626426 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 100784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 45696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 470347440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 53905938 # Number of bytes read from this memory +system.physmem.bytes_read::total 1392025556 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 827772912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 470347440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1298120352 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 32433610 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 35512400 # Number of bytes written to this memory -system.physmem.bytes_written::total 70937130 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 811 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 16485 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 8171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 105452420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 6721793 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11484 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 5337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 58609232 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8980167 # Number of read requests responded to by this memory -system.physmem.num_reads::total 179805900 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu0.data 32173132 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 35738580 # Number of bytes written to this memory +system.physmem.bytes_written::total 70902832 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 809 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 15850 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 8052 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 103471614 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 6642662 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12598 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 5712 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 58793430 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9050935 # Number of read requests responded to by this memory +system.physmem.num_reads::total 178001662 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4872539 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 4951932 # Number of write requests responded to by this memory -system.physmem.num_writes::total 9871209 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 6627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 24857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 12321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 159006406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 7559287 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 17316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 8047 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 88373916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 10080840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 265089618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 159006406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 88373916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 247380322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 563767 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu0.data 4837067 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 4982709 # Number of write requests responded to by this memory +system.physmem.num_writes::total 9866514 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 6625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 23903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 12143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 156045492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 7470074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 18999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 8614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 88666344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 10161940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 262414135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 156045492 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 88666344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 244711836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 563860 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6113126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 6693420 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13370317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 570394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 24857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 12324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 159006406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13672414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 17316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 8047 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 88373916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 16774261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 278459935 # Total bandwidth to/from this memory (bytes/s) -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl1.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl1.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl1.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl1.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.physmem.bw_write::cpu0.data 6065036 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 6737167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13366066 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 570485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 23903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 12146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 156045492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13535110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 18999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 8614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 88666344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 16899107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 275780201 # Total bandwidth to/from this memory (bytes/s) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). @@ -114,52 +84,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.numCycles 10611136755 # number of cpu cycles simulated +system.cpu0.numCycles 10608177450 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 90467113 # Number of instructions committed -system.cpu0.committedOps 191744891 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 172320091 # Number of integer alu accesses +system.cpu0.committedInsts 88690468 # Number of instructions committed +system.cpu0.committedOps 187060545 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 168469813 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 0 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 18433408 # number of instructions that are conditional controls -system.cpu0.num_int_insts 172320091 # number of integer instructions +system.cpu0.num_conditional_control_insts 17923925 # number of instructions that are conditional controls +system.cpu0.num_int_insts 168469813 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 529438037 # number of times the integer registers were read -system.cpu0.num_int_register_writes 286410601 # number of times the integer registers were written +system.cpu0.num_int_register_reads 517963630 # number of times the integer registers were read +system.cpu0.num_int_register_writes 280483339 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 19683230 # number of memory refs -system.cpu0.num_load_insts 14799913 # Number of load instructions -system.cpu0.num_store_insts 4883317 # Number of store instructions -system.cpu0.num_idle_cycles 10087385086.886099 # Number of idle cycles -system.cpu0.num_busy_cycles 523751668.113901 # Number of busy cycles -system.cpu0.not_idle_fraction 0.049359 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.950641 # Percentage of idle cycles +system.cpu0.num_mem_refs 19132508 # number of memory refs +system.cpu0.num_load_insts 14284566 # Number of load instructions +system.cpu0.num_store_insts 4847942 # Number of store instructions +system.cpu0.num_idle_cycles 10086452980.871330 # Number of idle cycles +system.cpu0.num_busy_cycles 521724469.128670 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049181 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950819 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.numCycles 10608184676 # number of cpu cycles simulated +system.cpu1.numCycles 10609379371 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48458484 # Number of instructions committed -system.cpu1.committedOps 93253647 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 88897203 # Number of integer alu accesses +system.cpu1.committedInsts 48574284 # Number of instructions committed +system.cpu1.committedOps 93351709 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 89110416 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 0 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8156142 # number of instructions that are conditional controls -system.cpu1.num_int_insts 88897203 # number of integer instructions +system.cpu1.num_conditional_control_insts 8197841 # number of instructions that are conditional controls +system.cpu1.num_int_insts 89110416 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 272264147 # number of times the integer registers were read -system.cpu1.num_int_register_writes 138280138 # number of times the integer registers were written +system.cpu1.num_int_register_reads 273178604 # number of times the integer registers were read +system.cpu1.num_int_register_writes 138760228 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 14383325 # number of memory refs -system.cpu1.num_load_insts 9129593 # Number of load instructions -system.cpu1.num_store_insts 5253732 # Number of store instructions -system.cpu1.num_idle_cycles 10274264583.773684 # Number of idle cycles -system.cpu1.num_busy_cycles 333920092.226317 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031478 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968522 # Percentage of idle cycles +system.cpu1.num_mem_refs 14426742 # number of memory refs +system.cpu1.num_load_insts 9181010 # Number of load instructions +system.cpu1.num_store_insts 5245732 # Number of store instructions +system.cpu1.num_idle_cycles 10273661233.326063 # Number of idle cycles +system.cpu1.num_busy_cycles 335718137.673937 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031644 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968356 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |